JPH0816507A - Peripheral device for ide bus - Google Patents

Abstract

PURPOSE:To prevent the reduction of the system operation speed. CONSTITUTION:The reset signal of an interface part 4 is a bidirectional signal which can be inputted and outputted, and the interface part 4 is provided with a discrimination part 402 which generates discrimination data indicating the soft reset at the time when the indication of soft reset is given. A CPU 202 executes a sort reset program 205 when the reset level is given to the reset terminal and discrimination data is generated, and the CPU 202 executes a hard reset program 204 when the reset level is given to the reset terminal and discrimination data is not generated. The time required for execution of the soft reset program 205 is made shorter than that of the hard reset program 204.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral device connected to a host device via an IDE bus.
The present invention relates to an IDE bus peripheral device that executes a hard reset program during a hard reset and executes a soft reset program during a soft reset.

[0002]

2. Description of the Related Art An IDE bus is an external bus that has an internal bus standardized as an ISA bus and is extremely easy to interface with a host device. Peripheral devices connected to this IDE bus have an interface with the IDE bus. An interface unit for performing faces is provided. Further, in this interface section, the reset terminal is a bidirectional terminal in order to avoid an increase in the number of pins when integrated into an IC. In other words, the reset level of the interface section is led to the reset level sent by the reset circuit provided inside the device. When the host device sends soft reset command data, the interface section sends the reset level to the reset terminal. On the other hand, the reset terminal of the CPU that mainly controls the peripheral device is connected to the reset terminal of the interface section. Therefore, when the host device sends command data for soft reset, the reset level generated in the interface section is given to the reset terminal of the CPU. The reset level sent by the reset circuit is also
It is given to the reset terminal of the CPU. That is, CPU
The reset terminal is provided with a reset level both when the host device sends soft reset command data and when the power is turned on. Therefore CPU
When a reset level is applied to the reset pin,
The same reset program is executed both when the host device sends command data for soft reset and when the power is turned on.

[0003]

The reset program described above is a program that is executed when the power is turned on, and is a program for starting up the apparatus. In other words, the program includes a self-diagnosis such as a memory test or a mechanical unit test, an operation of expanding a directory area stored in a storage medium into a memory area in advance, and has a long execution time. .
It is also a program that sets default values for all areas that require initial settings. Therefore, even in the case of soft reset, the time required to execute the reset program becomes long, and the time required until data can be input / output becomes long, which causes a problem that the operation speed of the entire system decreases. It was

The present invention was devised to solve the above problems, and an object of the present invention is to provide a system as a system by performing an operation according to a distinction between a soft reset and a hard reset. Another object of the present invention is to provide a peripheral device for an IDE bus which can prevent a decrease in the operating speed of the above. The object of the invention according to claim 2 is to provide an ID.
An object of the present invention is to provide an IDE bus peripheral device capable of preventing an increase in the number of terminals when the E interface portion is integrated into an IC.

[0005]

In order to solve the above problems, an IDE bus peripheral device according to a first aspect of the present invention has a reset circuit to which a reset signal line is connected and a reset signal line to a reset terminal. In addition, the reset signal line is connected to the CPU that controls according to the instruction sent by the host device connected via the IDE bus, and the ID that serves as an interface between the CPU and the IDE bus is connected.
The IDE interface unit initializes the internal circuit when the reset circuit sends the reset level to the reset signal line, and when the soft reset command data is given from the host device. It is applied to a peripheral device for an IDE bus that sends a reset level to a reset signal line, and when the soft reset command data is given to the IDE interface part, identification data indicating that the soft reset is generated is generated. An identification unit is provided, and the CPU causes the soft reset program to be executed when the reset level is applied to the reset terminal and the identification data is generated, and when the reset level is applied to the reset terminal and the identification data is not generated. Implement a hard reset program It is, has a configuration in which the time required for execution of the soft reset program shorter than the execution time required for the hard reset program. In the peripheral device for an IDE bus according to a second aspect of the present invention, the identification unit is stored in an identification register readable by the CPU as identification data.
The data set is different from the data set by the initial setting.

[0006]

The operation of the invention according to claim 1 will be described below. When the soft reset command data is sent from the host device, the CPU executes the soft reset program. When the reset circuit sends out the reset level, the CPU executes the hard reset program. Further, the execution time required for the soft reset program is shorter than the execution time required for the hard reset program. That is, of the various operations that are executed as a hard reset program, if a program that needs to be executed only when the device is started up is omitted from the soft reset program, the soft reset program is executed in response to this omission. The time required is reduced.

The operation of the invention according to claim 2 will be described below.
Since the identification data is data set in the identification register readable by the CPU, the identification data is recognized by the CPU as data on the data bus connecting the interface unit and the CPU.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a peripheral device for an IDE bus according to the present invention. Note that, in the following, for simplification of description, description of items related to recognition of connection of slave devices is omitted.

In the figure, a host device 1 is a computer having an internal bus 102 defined as an ISA bus, and includes a computer unit 101 and an interface unit 10.
3 is provided. The computer unit 101 is C
It is a block including a PU, a ROM, a RAM, a peripheral circuit, and the like, and executes main operations as a computer. The interface unit 103 is a block including an address decoder, a buffer, an I / O circuit, etc., and interfaces the internal bus 102 and the IDE bus 3.

The peripheral device for IDE bus (hereinafter simply referred to as peripheral device) 2 connected to the host device 1 via the IDE bus 3 is specifically a hard disk device which is a large-capacity external storage device. ing. The interface unit 4, the reset circuit 201, the CPU 202, the memory 203, the hard reset program 204, and the hard disk unit 206 (the resistor R is a pull-up resistor of the reset signal line 210).

The interface section 4 includes a reset signal line 2
10 is connected, the IDE bus 3 is connected, and the block is connected to the internal bus 207 via the bus 208. When the reset circuit 201 sends a reset level to the reset signal line 210, Initialize the circuit. When soft reset command data is sent from the host device 1, a reset level is sent to the reset signal line 210. Then, various data sent from the host device 1 is continuously or temporarily retained, and various data read by the host device 1 is continuously or temporarily retained.

Specifically, the decoding unit 401 and the identification unit 40
2, an initial setting unit 403, a register group 404, and two buffers 405 and 40 having open collector outputs
It is composed of six.

The register group 404 is composed of a register group forming a device control block and a register group forming a command control block, and holds various data sent from the host device 1. . It also holds various data to be read by the host device 1. The decoding unit 401 is A
Of the plurality of command data defined by the TAPI standard, the soft reset command data is the register group 4
Output 410 when written to a predetermined register 04
In addition, it is a block for transmitting a pulse of L level which is a reset level.

The identification section 402 is a block composed of a 1-bit identification register 414 and a 3-state output buffer 415. When the host device 1 sends soft reset command data, it indicates a soft reset. The identification data is sent to the output 416. Specifically, if it is a soft reset, the identification register 414 is set, and if it is a hard reset, the identification register 414 is reset. In other words, the generation of identification data
Shown as the H level at output 416. The fact that the identification data has not been generated is indicated by the L level of the output 416. Then, the identification data transmitted by the output 416 is read by the CPU 202 via the bus 208 and the internal bus 207 as data of a predetermined bit of a predetermined address transmitted to the data bus.

The initial setting section 403 includes a reset circuit 201.
Sends out the reset level (L level) and the output 410 of the decoding unit 401 is at the H level, that is, when the hard reset is performed when the power is turned on, the register group 4
It is a block for setting the data of a predetermined register of 04 to the default value. Also, the identification register 41
To set the initial value to 4, the identification register 414 is reset.

The buffer 405 is a buffer for outputting the L level sent from the decoding unit 401 to the output 410 to the reset signal line 210 as a reset level.
The buffer 406 is a buffer for sending the output of the reset signal line 411, which is one of the signal lines of the IDE bus 3, to the reset signal line 210. Reset circuit 201
Is a block that has an open collector output and sends a reset level (L level) to the reset signal line 210 when the reset switch is operated or when the power is turned on.

The hard reset program 204 uses the RO
It is a program stored in M, and internally includes a soft reset program which is a partial program thereof. In detail, it is a program for starting up the device when the power is turned on.
The operation test program of the hard disk unit 206, the program that sets a predetermined register of the register group 404 to the default value, the directory area of the hard disk unit 206 is read in advance, and the read data is stored in the memory 2
It includes programs etc. to be expanded in 03.

On the other hand, the soft reset program 205
Is a partial program of the hard reset program 204, and has a short execution time. In addition, the program does not require re-setting of parameters rewritten from the host device 1. Specifically, the program sets only the parameters other than the parameters rewritten by the host device 1 to the default values.

The hard disk unit 206 is a block including a mechanical unit as a hard disk device, a circuit for writing data to the disk, a circuit for reading data from the disk, and the like, and stores write data from the host device 1. . Also, the stored data is read and the read data is sent to the host device 1 as read data via the interface unit 4 and the IDE bus 3. The memory 203 is a block composed of a ROM and a RAM that store a control program other than the hard reset program 204.

The CPU 202 serves as a block for executing the programs stored in the memory 203, the hard reset program 204, the soft reset program 205, etc. in order to control the main operation of the peripheral device 2 seen from the host device 1. There is. Then, when the reset level is transmitted to the reset signal line 210 connected to the reset terminal, the output 416 is read. Next, when the output 416 is at the H level, it is determined that the identification data has been generated and the soft reset is performed, and the soft reset program 205 is executed. When the output 416 is at the L level, the identification data is not generated,
The hard reset program 204 is executed as the hard reset.

The operation of the embodiment having the above configuration will be described below. When the reset level is sent from the reset circuit 201 to the reset signal line 210 when the power is turned on, the initial setting unit 403 resets the identification register 414 and sets a default value in a predetermined register of the register group 404. To do. The CPU 202 also reads the output 416. The data read at this time is at the L level (identification data is not generated). Therefore, the CPU 202 executes the hard reset program 204, assuming that the hard reset is performed.

The operation executed as the hard reset is a memory test, an operation test of the hard disk unit 206, an operation of setting a predetermined register of the register group 404 to a default value, and a directory area of the hard disk unit 206 is read and read in advance. The data is expanded in the memory 203.

When the execution of the hard reset program 204 is completed, the peripheral device 2 can accept the command from the host device 1, and performs various operations under the control of the CPU 202 according to the instruction from the host device 1. The operation at this time is, for example, an operation of writing a predetermined number of sectors of data to the hard disk unit 206, an operation of reading a predetermined number of sectors of data from the hard disk unit 206, or the like. And when the execution is completed,
The CPU 202 writes the execution result in a predetermined register in the register group 404. The host device 1 reads the execution result written by the CPU 202 and grasps the operation status of the peripheral device 2.

In the above-described series of operations, when the execution result indicates the occurrence of an error that cannot be recovered by error correction, or when the execution result is not responded to the command data, the peripheral device 2 is seriously affected. Assuming that a malfunction has occurred, the host device 1 sends soft reset command data to the peripheral device 2 in order to eliminate this malfunction.

When command data instructing soft reset is written in a predetermined register of the register group 404,
The decoding unit 401 sends an L-level pulse to the output 410. This L-level pulse is applied as a reset level to the reset terminal of the CPU 202 via the reset signal line 210. Further, the identification register 414 of the identification unit 402 is set. That is, the output 416 becomes the H level indicating the generation of the identification data.

CPU 202 given a reset level
Reads the output 416. The data read at this time is at the H level (identification data is generated). Therefore, the CPU 202 starts the execution of the soft reset program 205, assuming that the soft reset is performed. The operation executed at this time is a partial operation of the operation executed as the hard reset. That is, as an initial setting of a predetermined register in the register group 404, an operation of setting a default value only for parameters other than the parameters rewritten by the host device 1 is performed. When the execution of the soft reset program 205 is completed, the operation of the peripheral device 2 can be accepted.

After this time, if the host device 1 does not need to change the previously set parameters, it immediately
It is possible to send command data or the like for reading data of a plurality of sectors to the peripheral device 2. That is, the peripheral device 2 returns to a state in which it can receive various command data in an extremely short time after receiving the command data for the soft reset.

As described above, in this embodiment, the soft reset program 205 is set to a program whose execution time is shorter than the execution time of the hard reset program 204, and the parameters rewritten from the host device 1 are used. Is not set to the default value. Therefore, in addition to the effect that the time required for executing the program is shortened, it is not necessary to set the parameters again. That is, after the soft reset command data is given, the time until data can be input / output to / from the host device 1 is further shortened. Therefore, it is possible to further prevent the decrease in the operating speed of the system.

The present invention is not limited to the above embodiment,
The peripheral device 2 has been described as a hard disk device, but it can be similarly applied to other devices such as an optical disk device or an MO / disk device capable of writing and reading data. Further, it is possible to apply to a streamer device and the like.

[0030]

In the peripheral device for an IDE bus according to the first aspect of the present invention, the reset signal of the interface section is a bidirectional signal which can be input / output, and the interface section is instructed to perform a soft reset. Is provided, an identification unit that generates identification data indicating that the reset is a soft reset is provided. Further, the CPU causes the soft reset program to be executed when the reset level is applied to the reset terminal and the identification data is generated, and the hard reset program is executed when the reset level is applied to the reset terminal and the identification data is not generated. It is running. The execution time required for the soft reset program is set shorter than the execution time required for the hard reset program. Therefore, of the various operations executed as a hard reset program, if a program that needs to be executed only when the device is started up is omitted from the soft reset program, it is necessary to execute the soft reset program in response to this omission. Since the time is shortened, it is possible to prevent a decrease in the operating speed of the system.

In the peripheral device for an IDE bus according to a second aspect of the present invention, the identification unit sets the identification register, which is readable by the CPU, as identification data, which is different from the data initially set. There is. For this reason, the identification data is recognized by the CPU as data on the data bus connecting the interface unit and the CPU, so that it is possible to prevent an increase in the number of terminals when the IDE interface unit is integrated into an IC. Has become.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of an IDE bus peripheral device according to the present invention.

[Explanation of symbols]

 1 host device 2 peripheral device for IDE bus 3 IDE bus 4 interface unit 201 reset circuit 202 CPU 204 hard reset program 205 soft reset program 210 reset signal line 402 identification unit 414 identification register 416 output indicating identification data

Claims (2)

[Claims] 1. A reset circuit to which a reset signal line is connected, and a CPU which connects the reset signal line to a reset terminal and controls according to an instruction sent by a host device connected via an IDE bus. And an IDE interface unit that is connected to the reset signal line and serves as an interface between the CPU and the IDE bus. In the IDE interface unit, the reset circuit resets the reset signal line to the reset level. In the peripheral device for the IDE bus, which initializes the internal circuit of the peripheral device when sending out, and sends a reset level to the reset signal line when soft reset command data is given from the host device. When the soft reset command data is given, A reset section for generating identification data indicating a soft reset, and causing the CPU to execute a soft reset program when a reset level is applied to the reset terminal and the identification data is being generated. An IDE characterized in that a hard reset program is executed when a reset level is applied to the terminal and the identification data is not generated, and the execution time of the soft reset program is shorter than the execution time of the hard reset program. Bus peripherals. 2. The identification unit sets, in the identification register readable by the CPU, data different from the data set by the initial setting as the identification data. Peripheral device for IDE bus.