JP2010066869A - Information processor, control method thereof and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly and easily analyze a failure factor when any failure occurs in an information processor such as a server. <P>SOLUTION: The server 100 includes a memory clear ON/OFF control circuit 103 for memorizing memory clear setting being setting not for clearing a memory 106 in reboot operation and a memory control circuit 104 for referring to the memory clear setting, and for, when not clearing the memory 106 is set, performing control not for erasing memory stored on the memory 106. Also, this server 100 is provided with an FROM 108 for memorizing a BIOS 109 having a file load setting flag for memorizing setting for starting an OS from an HDD 107 or not. When the memory control circuit 104 performs control not for clearing the memory 106, the CPU 101 refers to a file load setting flag, and when not starting the OS from the HDD 107 is set, the OS is resumed based on the memory stored on the memory 106. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, a control method therefor, and a program, and more particularly to a technology that supports analysis of a failure factor of a computer system such as a server.

As a technique related to the present invention, one described in Patent Document 1 is cited. In Patent Document 1, for example, referring to paragraph 0029 and the like, “even if a reset occurs in a recovery process from an abnormality, data is temporarily stored in a memory area (a built-in RAM of one of two CPUs). Is retained ”. However, it is assumed that the built-in RAM memory described in Patent Document 1 is not cleared.
JP 2007-316918 A

  In recent years, the wave of open standards has come in the communication field as well as the IT (Information Technology) field, and system construction based on a form factor defined by a standardization organization called a general-purpose server or PICMG has become mainstream. General-purpose servers and PICMG servers are mainly based on technology and ideas in the IT field. Therefore, when a server failure occurs in the system, the idea is to restore the system by resetting.

  However, many systems in the communication field have a redundant configuration (for example, duplication, n + 1) for the purpose of improving reliability. Therefore, there is almost no need to reset and recover a failed server. As a board, it is usually separated from the system and strives to identify the cause of failure.

  Previously, when a server failure occurred due to a hardware failure or software failure in the system, the minimum required log analysis data in memory was dumped to the HDD before resetting for the purpose of failure recovery. In some cases, log analysis data cannot be discharged to the HDD, which makes it difficult to analyze the cause of a server failure.

  In view of the above circumstances, an object of the present invention is to quickly and easily analyze a failure factor when a failure occurs in an information processing apparatus such as a server.

  In order to achieve the above object, the present invention comprises the following arrangement.

  The information processing apparatus according to the present invention has a memory clear ON / OFF control circuit that stores a memory clear setting that is a setting that does not clear a memory during a reboot operation, and a setting that is not cleared with reference to the memory clear setting. A memory control circuit that performs control not to delete the memory stored in the memory.

  The control method of the information processing apparatus according to the present invention does not clear the memory clear ON / OFF setting step for storing the memory clear setting, which is a setting that does not clear the memory during the reboot operation, and the memory clear setting. And a memory control step for performing control not to delete the memory stored in the memory in the case of setting.

  The program according to the present invention does not clear the information processing apparatus having the memory clear ON / OFF control circuit for storing the memory clear setting that does not clear the memory at the time of the reboot operation with reference to the memory clear setting. In the case of setting, a memory control procedure for performing control not to delete the memory stored in the memory is executed.

  According to the present invention, it is possible to quickly and easily analyze a failure factor when a failure occurs in an information processing apparatus such as a server.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  When a server failure occurs due to some kind of hardware failure or software failure, it is common to reset the suspect server for the purpose of early recovery of the system. However, in this embodiment, if the suspicious server is reset at that time, the memory data at the time of the server failure is not cleared, and the software is not loaded from the HDD in the reboot operation after the reset. Make analysis quick and easy.

  First, the configuration of the present embodiment will be described. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention. As shown in FIG. 1, the server 100 is configured to include a CPU 101, a CPU peripheral control circuit 102, a memory 106, an HDD 107, and a FROM 108, which are main elements.

  The CPU 101 is a central processing unit of the server 100 and controls the entire system. The memory 106 is a main memory of the server 100. The operating system (basic software; hereinafter referred to as “OS”) of the server 100 is stored in the HDD 107, which is a nonvolatile storage device, and can be executed on the memory 106 to execute predetermined information processing. It becomes possible.

  The CPU peripheral control circuit 102 includes a memory control circuit 104, a memory clear ON / OFF control circuit 103, and an IO control circuit 105. Each of these circuits can also be realized by a software program. The FROM 108 stores a BIOS (Basic I / O System) 109 having an OS file load activation flag function.

  The CPU 101 and the CPU peripheral control circuit 102 are connected by a CPU bus. The memory 106 and the CPU peripheral control circuit 102 are connected by a memory bus, and the memory 106 is controlled by the memory control circuit 104. The CPU peripheral control circuit 102 and input / output means such as the HDD 107 and FROM 108 are connected by an IO bus, and these input / output means are controlled by the IO control circuit 105.

  In the present embodiment, as shown in FIG. 1, a reset signal that prompts a system reboot is input to the CPU 101 and the CPU peripheral control circuit 102.

  Hereinafter, the operation of this embodiment will be described. FIG. 2 is a flowchart showing the flow of the reboot operation after a failure has occurred in this embodiment.

  When any failure occurs in the server 100 according to the present embodiment, a reset is input to the server 100 or an autonomous reset activation circuit (not shown) inside the server is turned on. At that time, the reset signal shown in FIG. 1 is input to the CPU 101 and the CPU peripheral control circuit 102. The CPU 101 and the CPU peripheral control circuit 102 that have received the reset signal transition to an initialization operation of the server after a certain reset period.

  In FIG. 2, when a reset signal is input to the CPU 101 or the like, the reset process of the server 100 is started (step S101), the reset process is canceled after a predetermined reset period (step S102), and the server initialization operation (step Transition to S103-113).

  As an initialization operation of the server 100, first, the CPU 101 fetches a program to execute a server initialization program of firmware called BIOS 109 built in the FROM 108 under the IO bus via the CPU peripheral control circuit 102 via the CPU bus. And execute the server initialization program. Normally, the memory 106 is initialized during the processing of the server initialization program. At this time, the memory clear ON / OFF control circuit 103 incorporated in the CPU peripheral control circuit 102 is set to OFF. The memory control circuit 104 protects the data in the memory 106 from being cleared. By incorporating this mechanism and initialization procedure into the initialization operation program, it is possible to suppress the memory data clearing operation by reset.

  In FIG. 2, the server initialization program of the BIOS 109 starts operation (step S103). Here, the CPU 101 confirms the setting of the memory clear ON / OFF control circuit 103 (step S104). If the memory initialization is OFF (not initialized) (step S105, Yes), the memory control circuit 104 stores the memory 106 in the memory 106. Is protected so as not to be cleared (step S106). Thus, the server initialization program completes the operation (step S107).

  When the BIOS 109 completes the execution of the series of server initialization programs including the above-described operation, the BIOS 109 executes a boot loader function for developing the program stored in the HDD 107 in the memory 106 in order to transfer the processing to the OS. When the processing is skipped and the OS 109 can be operated by a program already stored in the memory 106, the boot loader function of the BIOS 109 has an OS file load start flag function, and this flag is OFF. Can provide a mechanism that allows the program stored in the memory 106 to be directly executed even if the OS does not load the program stored in the HDD 107.

  In FIG. 2, the boot loader of the BIOS 109 starts operation (step S108). Here, the CPU 101 confirms the setting of the file load from the HDD of the OS set in the boot loader function of the BIOS 109 (step S109), and when the HDD file load is OFF (file load from the HDD is not performed) (step S109). S110, Yes), while the boot loader of the BIOS 109 completes the operation (step S111), the subsequent boot process is passed to the OS deployed on the memory 106 (step S112). Note that steps S111 and 112 may be executed simultaneously.

  If the memory clear setting is ON (step S105, No), or if the HDD file load ON / OFF setting is ON (step S110, No), normal startup processing is executed (step S113).

  The effects of the embodiment according to the present invention described above will be described.

  Even when a server failure occurs, especially if the server hangs up due to intermittent hardware failures or hardware / firmware / software bugs, the minimum required amount in memory before resetting Since a limited amount of log analysis data cannot be discharged to the HDD, it is possible to collect memory data after recovering from a hang-up state by reset. However, since the normal reboot operation clears the memory at the time of booting, such data collection cannot be performed.

  However, according to the present embodiment, it is possible to start up with the data developed in the memory after the reset is input, so that there is an effect that the log collection for the analysis of the server failure factor is ensured. Further, it is not necessary to consider the file load time from the HDD as the server start-up time after the reset is turned on, and there is an effect of shortening the server start-up time after the reset is turned on. Therefore, according to the present embodiment, it is possible to quickly and easily analyze a failure factor when a failure occurs in an information processing apparatus such as a server.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to this, and various modifications can be made without departing from the scope of the invention.

It is a block diagram which shows the structure of the principal part of embodiment by this invention. It is a flowchart which shows the reboot operation of embodiment by this invention.

Explanation of symbols

100 server 101 CPU
102 CPU peripheral control circuit 103 Memory clear ON / OFF control circuit 104 Memory control circuit 105 IO control circuit 106 Memory 107 HDD
108 FROM
109 BIOS

Claims (6)

A memory clear ON / OFF control circuit for storing a memory clear setting that is a setting that does not clear the memory during a reboot operation;
A memory control circuit that performs control not to delete the memory stored in the memory when the setting is not cleared with reference to the memory clear setting; and
An information processing apparatus comprising: BIOS storage means for storing a BIOS having a file load setting flag for storing a setting as to whether or not to start the operating system from the secondary storage device;
When the memory control circuit performs control that does not clear the memory, the file load setting flag is referred to, and if the setting is such that the operating system is not started from the secondary storage device, it is stored in the memory. Control means for restarting the operating system based on the memory;
The information processing apparatus according to claim 1, further comprising:   The information processing apparatus according to claim 2, wherein the storage stored in the memory is an operating system in which a file is loaded from the secondary storage device and expanded.   The information processing apparatus according to claim 1, wherein the memory is a main memory of the information processing apparatus. A memory clear ON / OFF setting step for storing a memory clear setting that is a setting that does not clear the memory during a reboot operation;
A memory control step for performing control not to delete the memory stored in the memory when the setting is not cleared with reference to the memory clear setting; and
A method for controlling an information processing apparatus, comprising: In an information processing apparatus having a memory clear ON / OFF control circuit for storing a memory clear setting that is a setting that does not clear a memory during a reboot operation,
With reference to the memory clear setting, when the setting is not cleared, a memory control procedure for performing control not to delete the memory stored in the memory,
A program characterized by being executed.

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