CN111078469A

CN111078469A - Data processing method and data processing equipment

Info

Publication number: CN111078469A
Application number: CN201911222027.4A
Authority: CN
Inventors: 徐炀
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2019-12-03
Filing date: 2019-12-03
Publication date: 2020-04-28

Abstract

The embodiment of the invention discloses a data processing method, which comprises the following steps: acquiring target data from a first chip storage space of the electronic equipment; the target data is data used for realizing hardware setting and control of the electronic equipment in a pre-starting stage of the electronic equipment; processing the target data to obtain at least first data and second data; and storing the first data to the second chip storage space and storing the second data to the third chip storage space. The embodiment of the invention also discloses data processing equipment.

Description

Data processing method and data processing equipment

Technical Field

The present invention relates to the field of electronics and information technologies, and in particular, to a data processing method and a data processing device.

Background

With the increase of the upgrading frequency of various security policies, the updating of the BIOS code data solidified on the memory chip of the computer is more and more frequent, and the abnormal power failure or misoperation phenomena are easily caused in the updating process of the BIOS version, which easily cause the data damage in the updating process of the BIOS code data. In the related art, usually, BIOS code data is backed up on a Read Only Memory (ROM) chip of a Serial Peripheral Interface (SPI), and when data is damaged in a BIOS version updating process, the BIOS code data is recovered from the SPIROM.

Disclosure of Invention

In view of this, embodiments of the present invention are expected to provide a data processing method, which can reduce hardware cost pressure caused by backing up all BIOS code data on the SPI ROM, and reduce professional requirements on tools and operators in the BIOS code data recovery.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a method of data processing, the method comprising:

acquiring target data from a first chip storage space of the electronic equipment; the target data is data used for realizing hardware setting and control of the electronic equipment in a pre-starting stage of the electronic equipment; the pre-starting stage is a starting stage before the electronic equipment loads an operating system;

processing the target data to obtain at least first data and second data;

and storing the first data to a second chip storage space, and storing the second data to a third chip storage space.

Optionally, the processing the target data to obtain at least first data and second data includes:

dividing the target data based on the function of each data in the target data in the pre-starting stage to obtain the first data and the second data; the first data is data used for realizing initialization of the electronic equipment processor and the hardware chip in the pre-starting stage; the second data is data of the target data other than the first data.

A data processing method, characterized in that the data processing method comprises:

when the electronic equipment executes a pre-starting stage, if the target data is detected to be damaged, acquiring first data from a second chip storage space and acquiring second data from a third chip storage space; the target data is data used for realizing hardware setting and control of the electronic equipment in a pre-starting stage of the electronic equipment; the pre-starting stage is a starting stage before the electronic equipment loads an operating system;

performing the pre-boot phase of the electronic device based on the first data and the second data.

Optionally, if it is detected that the target data is damaged, acquiring the first data from the second chip memory space and acquiring the second data from the third chip memory space includes:

if the target data are detected to be damaged, acquiring a data zone bit of the electronic equipment;

setting the data zone bit as a first numerical value, and acquiring the first data from the second storage space; wherein the first value is indicative of the target data corruption; the first data is data used for realizing initialization of the electronic equipment processor and the hardware chip in the pre-starting stage;

acquiring the second data from the third storage space; the second data is data of the target data other than the first data.

Optionally, the executing a pre-boot stage of the electronic device based on the first data and the second data includes:

acquiring third data based on the first data and acquiring fourth data based on the second data;

performing the pre-boot phase of the electronic device based on the third data and the fourth data.

Optionally, the obtaining third data based on the first data and obtaining fourth data based on the second data includes:

storing the first data into the first chip storage space to obtain third data;

and storing the second data into the first chip storage space to obtain the fourth data.

Optionally, the executing the pre-boot stage of the electronic device based on the third data and the fourth data includes:

executing a first sub-boot phase of the electronic device based on the third data;

executing the second sub-boot phase of the electronic device based on the fourth data; the pre-boot phase includes the first sub-boot phase and the second sub-boot phase.

Optionally, after acquiring the first data from the second storage space based on the data flag bit, the method further includes:

setting the data flag bit of the electronic device to a second value; wherein the second numerical value indicates that no corruption of the target data occurred.

A data processing apparatus, the data processing apparatus comprising: a first processor, a first memory, and a first communication bus;

the first communication bus is used for realizing communication connection between the first processor and the first memory;

the first processor is for executing a program of a data processing method in a memory to realize the steps of:

processing the target data to obtain at least first data and second data;

A data processing apparatus, the data processing apparatus comprising: a second processor, a second memory, and a second communication bus; the second communication bus is used for realizing communication connection between the first processor and the second memory;

the second processor is for executing a program of a data processing method in a memory to realize the steps of:

based on the first data and the second data, a pre-boot phase of the electronic device is performed.

The data processing method and the data processing device provided by the embodiment of the invention firstly acquire target data from a first chip storage space of the electronic device, process the target data to obtain first data and second data, then store the first data into a second chip storage space, and back up the second data in a third chip storage space. When the BIOS code data is damaged, the BIOS code data is automatically restored based on the first data and the second data, so that the target data is divided into two parts for backup, and the problem of hardware cost increase caused by the fact that the target data is completely backed up on the SPI ROM is solved.

Drawings

Fig. 1 is a flowchart of a data processing method according to an embodiment of the present invention;

FIG. 2 is a flow chart of another data processing method according to an embodiment of the present invention;

FIG. 3 is a flow chart of another data processing method according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating an implementation of a data processing method according to an embodiment of the present invention;

FIG. 5 is a flowchart of the Embedded Controller (EC) operation of the notebook computer;

FIG. 6 is a schematic diagram of the Intel Top-Swap based data read address switching mechanism; the invention provides for the embodiment of the invention;

fig. 7 is a block diagram of a data processing apparatus according to an embodiment of the present invention;

fig. 8 is a block diagram of another data processing apparatus according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It should be appreciated that reference throughout this specification to "an embodiment of the present invention" or "an embodiment described previously" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in an embodiment of the present invention" or "in the foregoing embodiments" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

It should be noted that, for descriptions of steps (or concepts) that are the same as or correspond to those in other embodiments of the present invention, reference may be made to descriptions in other embodiments, and further description is omitted here.

The invention provides a data processing method, relates to the technical field of electronics and information, and particularly relates to a data processing method and data processing equipment.

For a notebook computer, BIOS plays a very critical role in the boot process of the notebook computer, generally, BIOS code data is burned in a BIOS Read Only Memory (ROM) on a motherboard of the notebook computer, in which an important basic input/output program, a self-test program after booting, and a System self-start program are stored, as a bridge for communication between hardware and an Operating System (OS), and after a user presses a power key for booting the notebook computer, the BIOS sequentially performs initialization setting and testing on the hardware of the notebook computer according to a set order, and enters a link of loading the OS after all hardware initialization setting and testing are abnormal.

Therefore, the BIOS code data provides the bottom layer and most direct hardware setting and control for the system, and once the BIOS code data is abnormal, the operating system of the notebook computer cannot be normally loaded, so that the entire notebook computer cannot be used. Due to the importance of BIOS code data for notebook computers, the importance of normal updates to the version related to its security optimization policy and functional updates is readily apparent.

However, in the related art, when the BIOS code data is upgraded, the abnormal power failure of the notebook computer, the user misoperation and the like may occur, and these conditions all result in the failure of the BIOS code data upgrade, thereby causing the loss of the BIOS code data stored in the BIOS ROM; on the other hand, even if the upgrade process is not performed on the BIOS code data, the BIOS code data may be damaged by a virus to affect the integrity and security thereof, which may cause a problem of normally and correctly initializing core hardware devices including a processor and the like on the notebook computer.

In the related art, in order to solve the problem that the BIOS code data is lost or the integrity and the security are affected, the BIOS code data is usually backed up in the SPI ROM, and when the above-mentioned abnormal problem occurs, the BIOS code data is restored from the SPI ROM into the BIOS ROM, and the BIOS process is executed based on the BIOS code data obtained after the restoration. However, the storage space of the SPI ROM in the notebook computer is limited, and if the BIOS code data is backed up to the SPI ROM as a whole, the SPI ROM needs to be expanded to one time or more of the current storage capacity, which may increase the hardware cost of the SPI ROM.

In the related art, when the BIOS code data is lost or the integrity and the security are affected, the user may use a professional burning tool to burn the BIOS code data into the BIOS ROM and re-execute the BIOS code data loading process. However, although this method can recover the BIOS code data quickly, it requires a professional programming tool, and requires a user of the notebook computer to have a considerable level of computer system knowledge to operate, i.e., this method requires a high level of professional tools and expertise.

In the related art, when the BIOS code data is lost or the integrity and security of the BIOS code data are affected, a Crisis mechanism may be further used to perform a recovery process of the BIOS code data. Among them, Crisis is a mechanism that can solve the problem of recovering BIOS code data in ROM BIOS of a system in computer system Crisis caused by BIOS code data damage.

However, the Crisis mechanism does not function to restore BIOS code data at all times. The Crisis mechanism can play a role in recovering the BIOS code data only after the data of the Boot Block part in the BIOS code data is normally loaded.

The boot process of the BIOS can be generally divided into four stages:

the initial code detection Phase is (Security Phase, SEC) module loading Phase, which is the earliest boot Phase in the BIOS boot process, and the boot time of this Phase is short, and the amount of code is small. This phase is mainly used to enable application processors, update Central Processing Unit (CPU) patches, and so on.

The early Initialization stage is a (Pre-EFI Initialization, PEI) module loading stage, which is a second stage of BIOS startup and is also called a Pre-extensible firmware interface Initialization stage, in which a CPU operates in a protected mode 32-bit state, starts to start and initialize some core chips and hardware devices such as a memory controller, a south bridge, a north bridge, and the like, and completes some most basic hardware chip Initialization operations.

The Driver Execution Environment phase (DXE) module loading phase is the third phase of BIOS startup, in which the CPU working mode is converted into the long mode in the 64-bit protection mode, and the BIOS loads all hardware chip drivers to complete the initialization of all hardware including the audio and video codec chip and the power management chip.

The Boot Selection phase (BDS) is a module Boot phase, which is the fourth phase of BIOS Boot, in which a hardware Device to be booted is scanned and enumerated. When the BIOS is started to this stage, it means that the enumerated hardware devices are started according to a preset start sequence of the BIOS, and the operating system is started.

The data of Boot Block part of the BIOS code data comprises data in SEC stage and data in PEI stage. The Crisis mechanism has to play a role in recovering the code data of the BIOS only when the data of the Boot Block part of the BIOS is intact.

That is, during the BIOS upgrade process, or after the security of the BIOS code data is affected, if the Boot Block data of the BIOS code data is damaged, the Crisis mechanism cannot function. Boot Block is the most important file area in BIOS code data, the file area is the first executed leader in BIOS code data, if the leader is damaged, the Crisis mechanism cannot be executed. In other words, the Crisis mechanism requires that the BIOS environment of the component can execute after the correct loading of the data by means of Boot Block.

Therefore, the method for recovering the BIOS code data using the Crisis mechanism cannot recover the entire BIOS code data under any condition, or cannot guarantee that any part of the BIOS code data can be recovered.

Based on the defects of various solutions for solving the problem that BIOS code data is damaged in the relative technology, the embodiment of the present invention provides a data processing method, which may be implemented by data processing equipment, where the data processing equipment may be a BIOS ROM and an SPI ROM of a notebook computer, and other hardware storage equipment on the notebook computer besides the above storage equipment, as shown in fig. 1, the method includes the following steps:

step 101, obtaining target data from a first chip storage space of the electronic device.

The target data is data used for realizing hardware setting and control of the electronic equipment in a pre-starting stage of the electronic equipment; the pre-boot phase is a boot phase before the electronic device loads the OS.

In step 101, an electronic device, which may be a computer notebook device, is provided.

In one embodiment, the electronic device may also be a desktop computer device.

In one embodiment, the electronic device may be a personal computer device.

In one embodiment, the electronic device may also be a server-class computer device.

In step 101, the target data may be BIOS code data. BIOS code data can realize the bottom layer and most direct hardware setting and control of the electronic equipment.

In step 101, the pre-boot phase may be a phase of loading BIOS code data, i.e., a BIOS boot phase. The BIOS start-up phase is the start-up phase before the electronic device loads the OS. Accordingly, the hardware setting and control of the electronic equipment can be realized in the BIOS starting stage.

In step 101, the first chip may be a BIOS ROM chip. Accordingly, the memory space of the first chip may be the memory space of the BIOS ROM chip.

In step 101, the obtained target data is complete BIOS code data that has not been damaged.

102, processing the target data to obtain at least first data and second data

In step 102, the first data is part of the target data. In one embodiment, the first data is a portion of the BIOS code data, and in particular, the first data may be data of an SEC phase and data of a PEI phase of the BIOS code data. Accordingly, the second data may be the BIOS code data excluding the data of the SEC phase and the data of the PEI phase, i.e., the data of the DXE phase and the data of the BDS phase.

In one embodiment, the first data may also be data of an SEC phase, data of a PEI phase, and data of a DXE phase in the BIOS code data, and correspondingly, the second data may be data of the BIOS code data excluding data of the SEC phase, data of the PEI phase, and data of the DXE phase, that is, data of a BDS phase.

In one embodiment, in step 102, processing the target data to obtain at least first data and second data may be implemented as follows:

and dividing the target data based on the function of each data in the target data in the pre-starting stage to obtain first data and second data.

The first data is data used for realizing initialization of a processor and a hardware chip of the electronic equipment in a pre-starting stage; the second data is data of the target data other than the first data.

In an embodiment, the target data is divided to obtain the first data and the second data based on a function of each data in the target data in the pre-boot phase, and the BIOS code data may be divided to obtain the first data and the second data based on respective functions of the data in the SEC phase, the data in the PEI phase, the data in the DXE phase, and the data in the BDS phase in the BIOS code data.

In an embodiment, the target data is divided based on a function of each data in the target data in a pre-boot phase to obtain the first data and the second data, and the BIOS code data may be divided based on respective functions and a loading sequence of SEC phase data, PEI phase data, DXE phase data, and BDS phase data in the BIOS code data to obtain the first data and the second data.

In an embodiment, the target data is divided based on a function of each data in the target data in a pre-boot phase to obtain the first data and the second data, and the BIOS code data may be divided based on respective functions, loading order and data loading importance of the data in an SEC phase, a PEI phase, a DXE phase and a BDS phase in the BIOS code data to obtain the first data and the second data.

In one embodiment, the first data is data used for realizing initialization of a processor and a hardware chip of the electronic device in a pre-boot phase, that is, the first data may be data in an SEC phase and data in a PEI phase in a BIOS boot phase; accordingly, the second data may be data of DXE phase and BDS phase in BIOS boot phase.

In one embodiment, the first data is data used for implementing initialization of a processor and a hardware chip of the electronic device in a pre-boot phase, that is, the first data may be data in an SEC phase and data in a PEI phase in a BIOS boot phase, and data in a DXE phase; accordingly, the second data may be data of the BDS phase in the BIOS boot phase.

And 103, storing the first data in a second chip storage space, and storing the second data in a third chip storage space.

In step 103, the second chip memory space may be the memory space of the SPI ROM chip.

In step 103, the third chip memory space may be a memory space of the electronic device excluding the memory space of the BIOS ROM chip and the memory space of the SPI ROM.

In one embodiment, the third chip storage space may be a Solid State Drive (SSD), where the SSD is also called a Solid State hard Disk, and the SSD is a hard Disk made of a Solid State electronic storage chip array, and is composed of a control unit and a storage unit, and is widely applied in various electronic devices, especially computer devices, which need to have a large capacity storage capability.

In one embodiment, the third chip storage space may be a Hard Disk Drive (HDD), which is the most basic storage widely used on a computer, i.e. a normal Hard Disk.

In the data processing method provided in the embodiment of the present invention, first, target data is obtained from a first chip storage space, and then, according to functions of each part of data in the target data, the target data is divided into at least first data and second data, and then the first data is stored in a second chip storage space, and the second data is stored in a third chip storage space.

Based on the foregoing embodiments, an embodiment of the present invention provides a data processing method, as shown in fig. 2, where the data processing method may be implemented by the following steps:

step 201, when the electronic device executes a pre-boot stage, if it is detected that the target data is damaged, acquiring the first data from the storage space of the second chip, and acquiring the second data from the storage space of the third chip.

In step 201, when the electronic device executes the pre-boot phase, the electronic device may be a boot button pressed by a user of the electronic device, or a boot phase executed after the electronic device is powered on, and the pre-boot phase is a boot phase before the electronic device loads the OS.

In step 201, the target data is corrupted, which may be the integrity of the target data is corrupted.

In one embodiment, the target data is damaged, and may be that the target data is partially lost, so that in the pre-boot stage, the target data corresponding to the operation to be performed next cannot be found.

In one embodiment, the target data is corrupted, which may be that the target data is modified, resulting in the inability to correctly perform operations corresponding to the uncorrupted target data during the pre-boot phase.

In one embodiment, the detection of the target data corruption may be obtained by monitoring a start-up duration of the pre-start-up phase, for example, if the start-up duration of the pre-start-up phase exceeds a threshold time of the pre-start-up phase, the target data corruption may be determined.

In an embodiment, the detection of the target data being damaged may also be obtained by monitoring whether the pre-boot stage can be normally started, for example, after the user presses the start switch, the electronic device cannot execute the pre-boot stage, or the electronic device cannot enter the pre-boot stage, and it may be determined that the target data is damaged.

In step 201, when the electronic device executes a pre-boot phase, if it is detected that the target data is damaged, the first data is obtained from the second chip memory space, and then the second data is obtained from the third chip memory space.

Step 202, based on the first data and the second data, a pre-boot phase of the electronic device is performed.

In step 202, based on the foregoing description of the embodiment, it can be seen that the first data and the second data are obtained by dividing the target data, that is, the target data can be obtained based on the first data and the second data.

In one embodiment, the target data may be obtained based on the first data and the second data, and the pre-boot stage of the electronic device may be executed based on the target data.

In one embodiment, the method may perform a boot phase corresponding to the first data based on the first data, and then perform a boot phase corresponding to the second data based on the second data.

In the data processing method provided in the embodiment of the present invention, when the electronic device executes the pre-boot stage, if it is detected that the target data is damaged, the first data is obtained from the second chip memory space, the second data is obtained from the third chip memory space, and then the pre-boot stage of the electronic device is executed based on the first data and the second data. Therefore, the data processing method provided by the embodiment of the invention can ensure that the pre-boot stage can still be executed based on the first data and the second data when the target data is damaged, thereby realizing the technical effect that the pre-boot stage can be executed when any part of the data of the BIOS code data is damaged.

Based on the foregoing embodiments, an embodiment of the present invention provides a data processing method, as shown in fig. 3, where the data processing method may be implemented by the following steps:

step 301, if the target data is detected to be damaged, acquiring a data zone bit of the electronic equipment;

in step 301, the data flag bit of the electronic device may be a flag bit indicating whether target data of the electronic device is damaged, for example, if the target data is damaged, the data flag bit may be set as first data, and if the target data is not damaged, the data flag bit may be set as second data.

In one embodiment, the data flag of the electronic device may be used to indicate that the first data needs to be retrieved from the second chip memory space and the second data needs to be retrieved from the third chip memory space.

In one embodiment, the data flag of the electronic device may also be used to indicate that only the first data needs to be retrieved from the second chip memory space.

In one embodiment, the data flag of the electronic device may also be used to indicate that only the second data needs to be retrieved from the third chip memory space.

In one embodiment, the data flag of the electronic device may also be used to indicate an address for the electronic device to read data, and the electronic device needs to switch from the first chip memory space to the second chip memory space, or switch from the second chip memory space to the third chip memory space.

In an embodiment, the data flag of the electronic device may also be used to indicate an address for the electronic device to read data, and the data flag needs to be switched from the first chip storage space to the second chip storage space and then from the second chip storage space to the third chip storage space.

Step 302, setting the data flag bit to a first value, and obtaining the first data from the second storage space.

Wherein the first value is used to indicate target data corruption; the first data is data used to implement initialization of the electronic device processor and hardware chip during the pre-boot phase.

Step 303, acquiring second data from a third storage space; the second data is data of the target data other than the first data.

In step 302 and step 303, the data flag is a first value, which can be used to indicate that the target data is damaged, and at this time, the address of the data currently read by the electronic device needs to be switched from the first chip storage space to the second chip storage space, or from the first chip storage space to the third chip storage space.

In an embodiment, if only the first data is damaged, the data flag is set to be a first value, and the address of the data currently read by the electronic device is switched from the first chip storage space to the second chip storage space to obtain the first data, and then the address of the data read by the electronic device is switched from the second chip storage space to the first chip storage space to continue to obtain the data portion corresponding to the second data in the target data.

In one embodiment, if only the second data is damaged, the data identification bit is set to be the first value, and after the electronic device reads the data portion corresponding to the first data in the current target data, the address of the read data is switched from the first chip storage space to the third chip storage space to obtain the second data.

In an embodiment, if both the first data and the second data are damaged, the data flag is set to be a first value, and the address of the data currently read by the electronic device is switched from the first chip storage space to the second chip storage space to obtain the first data, and then switched from the second chip storage space to the third chip storage space to obtain the second data.

Step 304, based on the first data and the second data, a pre-boot phase of the electronic device is performed.

In one embodiment, step 304 may be implemented by step a1 and step a 2:

step A1: third data is acquired based on the first data, and fourth data is acquired based on the second data.

Step A2: and executing a pre-starting stage of the electronic equipment based on the third data and the fourth data.

The third data may be obtained by copying the first data, and the fourth data may be obtained by copying the second data. That is, the third data and the fourth data are two parts of data obtained by dividing the target data, and therefore, the pre-boot stage of the electronic device can be performed based on the third data and the fourth data.

In one embodiment, obtaining the third data based on the first data and obtaining the fourth data based on the second data may be implemented by:

storing the first data into a first chip storage space to obtain third data; storing the second data into the first chip storage space to obtain fourth data

The first data is stored in the first chip storage space, and the third data is obtained under the condition that the data flag bit is set to be the first numerical value.

When the data identification bit is the first value, the electronic device reads the address of the data, may switch from the first chip storage space to a location in the second chip storage space where the first data is stored, and obtain the first data from the location, and then copy the first data to the storage space of the first chip to obtain the third data.

Correspondingly, when the data identification bit is the first value, the electronic device reads the address of the data, and can also switch from the second chip storage space to a position in the third chip storage space where the second data is stored, obtain the second data from the position, and copy the second data to the storage space of the first chip to obtain the fourth data.

In an embodiment, if only a data portion corresponding to the first data in the target data is damaged, when the data identification bit is a first value, the electronic device reads an address of the data, switches from the first chip storage space to a location in the second chip storage space where the first data is stored, obtains the first data from the location, and copies the first data to the storage space of the first chip to obtain the third data. And then, the data reading address of the electronic equipment is not switched to the third chip storage space any more.

In an embodiment, if only the data portion corresponding to the second data in the target data is damaged, when the data identification bit is the first value, the electronic device reads the address of the data, switches from the first chip storage space to a location in the third chip storage space where the first data is stored, obtains the second data from the location, and copies the second data to the storage space of the first chip to obtain the fourth data. And then, the data reading address of the electronic equipment is not switched to the storage space of the second chip any more.

In one embodiment, the execution of the pre-boot phase of the electronic device based on the third data and the fourth data may be implemented as follows:

executing a first sub-boot phase of the electronic device based on the third data; executing a second sub-boot phase of the electronic device based on the fourth data; the pre-start-up phase comprises a first sub-start-up phase and a second sub-start-up phase.

In the embodiment of the present invention, the first sub-boot stage is a partial stage in the pre-boot stage corresponding to the first data, and the second sub-boot stage is a partial stage in the pre-boot stage corresponding to the second data.

Based on the foregoing description of the embodiment, it is understood that the third data is part of the target data corresponding to the first data, and the fourth data is part of the target data corresponding to the second data, and therefore, the first sub-boot stage may be performed based on the third data, and then the second sub-boot stage may be performed based on the fourth data. Thus, the entire operation of the pre-boot stage of the electronic device is completed.

Based on the foregoing embodiment, in other embodiments of the present invention, after the setting the data flag to the first value and obtaining the first data from the second chip memory space in step 302, the following operations may also be performed:

setting a data zone bit of the electronic equipment to be a second numerical value; wherein the second numerical value indicates that the target data is not corrupted.

After the electronic device reads the first data, the data flag of the electronic device may be set to a second value.

In one embodiment, the data flag of the electronic device is a second value, which may be used to indicate that the target data of the electronic device is not damaged.

In one embodiment, the data flag of the electronic device is a second value, which can be used to indicate the address of the data currently read by the electronic device without switching from the first chip memory space to any other memory space.

In one embodiment, the data flag of the electronic device is a second value, which can be used to indicate an address of the electronic device currently reading data without switching from the first chip memory space to the first chip memory space and the second chip memory space.

In one embodiment, the data flag of the electronic device is a second value, which can be used to indicate an address of the electronic device currently reading data without switching from the first chip storage space to the first chip storage space or the second chip storage space.

In the data processing method provided by the embodiment of the invention, when the electronic device executes a pre-boot stage, if it is detected that the target data is damaged, the data flag bit of the electronic device is acquired, and the data flag bit is set to be the first data, so that the first data can be acquired from the second chip storage space of the electronic device, the second data can be acquired from the third chip storage space of the electronic device, and the pre-boot process of the electronic device is executed based on the first data and the second data. Therefore, the data processing method provided by the embodiment of the invention can acquire the target data of the part corresponding to the damaged part of data from the corresponding chip storage space after any data in the pre-starting stage of the electronic equipment is damaged, so that the normal operation of the pre-starting stage can be ensured under the condition that any part of the target data is damaged.

Based on the foregoing embodiment, taking an actual starting process of a notebook computer as an example, the embodiment of the present invention provides a data processing method, as shown in fig. 4:

the EC of the notebook computer starts to boot up when the user presses the start button, where EC is a 16-bit single chip machine that is a unique part of notebook computers, and it is because of the use of EC that represents an important difference between notebook computers and desktop computers. In notebook computers, portability is achieved. It is necessary to use a built-in keyboard (matrix-interpreted keyboard) and a built-in mouse (e.g., a touch pad and a pointing stick are all built-in mouse devices). For this purpose, a special keyboard controller is required, and the special EC of the notebook computer has the function. Moreover, the most important problem in designing a notebook computer is to make the system more power-saving, increase the endurance of the battery, have good heat dissipation performance, and minimize the noise of the system, so the CPU fan should be controlled to stop according to the temperature. Some power management of the notebook computer, such as the notebook computer entering a standby or power-off mode, power scheduling of the external power system. The important functions of power detection, charging and discharging tasks and some practical shortcut buttons of the intelligent battery are all completed by the EC.

Therefore, the EC plays an important role in the portable, intelligent and personalized design of the notebook computer. The Flash with certain capacity is arranged in the EC storage box to store codes of the EC. The EC has a position in the system no less than that of the north-south bridge, and controls the time sequence of most important signals in the system starting process. In notebooks, the EC is always on, whether in power on or off, unless the battery and power adapter are completely removed. In the shutdown state, the EC is kept running all the time and waits for the user's startup information. After the system is started, the EC is used for controlling devices such as a keyboard controller, a charging indicator light and a fan, and even controlling the standby state, the dormant state and the like of the system.

Both the EC and BIOS are at the lowest level of the machine. The EC is a single processor and has global management on the whole system before and during the boot process. The BIOS is run after the EC initializes the internal physical environment.

Fig. 5 is a flowchart of the EC operation in the embodiment of the present invention, after detecting that a user presses a power key, the EC is powered on and started, a Timer, also called a Watchdog (WDT), is set, then a BIOS code data loading normal loading and starting process is executed, and at the same time, whether the WDT is cleared is detected, if the WDT is cleared, other operations in the notebook computer starting process are continuously executed, and if the WDT is not cleared, after waiting for the WDT timeout, a Top swap Reset unit is enabled, and a restart process is executed. The WDT is used for preventing the startup process from being blocked due to the problems of endless loop or blockage of a program and the like.

In the implementation process of the data processing method, after detecting that a user presses a boot key, an EC sets a WDT, and then an Intel Management Engine (ME) starts an Authenticated Code Module (ACM) in BIOS Code data to check whether the ACM is credible or not.

The ME is an independent chip in the Intel CPU, the chip starts to work earlier than the CPU, the main function of the ME is to verify whether ACM data in BIOS data is trustable or not, when the Intel boot guard function is started, the ACM data is contained in the BIOS data, and before the BIOS code data is started to be executed, the ME firstly confirms whether the ACM exists or not and whether the ACM is trustable or not.

After the ACM data reliability check is finished, checking whether Boot Block Firmware (FW Boot Block) is trusted, if not, detecting whether WDT is overtime, if WDT is overtime, enabling a Top Swap pin Reset unit, trying to execute a restart once, if Boot Block is trusted, notifying EC by a PEI module, and reading an instruction (actually a jump instruction, which is set by CPU hardware) in a specific address in BIOS, that is, reading BIOS code data, at this time, checking whether BIOS code data are damaged, and if BIOS code data are damaged, setting Top-Swap to be in a state of needing to switch data reading address.

FIG. 6 is a flow chart of the data read address switching operation under the cooperation of the Top-Swap flag bit provided by Intel. In fig. 6, FV Main data corresponds to BIOS code data corresponding to a DXE module loading phase and a BDS module loading phase, and FVMain data is stored in the BOIS ROM; IBB _ P is Intel Boot Block Primary, namely Boot Block data, and IBB _ B is Intel Boot Block Backup, namely Backup Boot Block data.

When Top-Swap is in a state where no data read address needs to be switched, i.e. IBB _ P data is read from the first address at the bottom address FV _ MAIN in the left block diagram of fig. 6, the value of the pointer indicating the data address is decremented every time data is read. When Top-Swap is in need of switching data read address status, a data recovery process is performed to switch the address of the current read data from the first address pointing to IBB _ P to the second address, i.e. the part IBB _ B shown in the right block diagram of fig. 6, that is, to switch the address of the current read data to the address storing the backup data, and to read the backup data.

FIG. 6 mainly illustrates that after the top-swap pin is set, the BIOS data that is active at the time of actual startup is switched from IBB _ P to IBB _ B.

It should be noted that, during each BIOS code data loading process, it is detected whether Top-Swap is set.

If the Top-Swap is set to be in a state of needing to switch the data reading address, the BIOS code data is damaged, at this time, the EC is notified to clear the WDT, then the address of the currently read data is switched from the BIOS ROM to the SPI ROM for backing up the first data, the first data is copied from the SPI ROM to obtain third data, the third data is stored in the BIOS ROM, meanwhile, the second data stored in the HDD/SSD is copied to obtain fourth data, and the fourth data is stored in the BIOS ROM. After the copy storage operation is completed, checking whether the BIOS code data is normally recovered or not, if the BIOS code data is normally recovered, executing a restart, if the BIOS code data is normally recovered, notifying the EC to set the Top-Swap to be in a state that the data reading address does not need to be switched, namely recovering a default value, and then executing a restart.

After a new restart is started, if the BIOS code data has been recovered, Top-Swap is in a state where it is not necessary to switch the data read address, and after the phase corresponding to the PET module is executed, the EC is notified to clear the WDT, and then a normal start procedure is executed.

In any normal starting process, whether the SPI ROM stores first data or not is checked, if the first data is not stored, the first data is backed up to the SPI ROM, whether second data is stored in the HDD/SSD or not is checked, and if the second data is not stored, the second data is backed up to the HDD/SSD and a normal process is executed.

If the SPI ROM is detected to store the first data in any normal starting process, the operation of backing up the first data into the SPI ROM is not executed any more, and if the HDD/SSD is detected to back up the second data, the second data is not backed up into the HDD/SSD any more, and the execution of the normal starting process is continued.

Based on the foregoing embodiments, an embodiment of the present invention provides a data processing apparatus 7, and as shown in fig. 7, the data processing apparatus 7 includes: a first processor 71, a first memory 72 and a first communication bus 73, wherein the first chip memory space is located in the first processor 71, the first communication bus 73 is used for implementing communication connection between the first processor 71 and the first memory 72, the first processor 71 is used for executing a program of a data processing method in the first memory, so as to implement the following steps:

processing the target data to obtain at least first data and second data;

and storing the first data to the second chip storage space and storing the second data to the third chip storage space.

In other embodiments of the present invention, the first processor 71 is further configured to implement the following steps:

processing the target data to obtain at least first data and second data, including:

dividing the target data based on the function of each data in the target data in a pre-starting stage to obtain first data and second data; the first data is data used for realizing initialization of a processor and a hardware chip of the electronic equipment in a pre-starting stage; the second data is data of the target data other than the first data.

In the data processing apparatus provided in the embodiment of the present invention, first, target data is obtained from a first chip storage space, and then, according to functions of each part of data in the target data, the target data is divided into at least first data and second data, and then the first data is stored in a second chip storage space, and the second data is stored in a third chip storage space.

Based on the foregoing embodiments, an embodiment of the present invention provides a data processing apparatus 8, and as shown in fig. 8, the data processing apparatus 8 includes: a second processor 81, a second memory 82 and a second communication bus 83, wherein the first chip memory space is located in the second processor 81, the second communication bus 83 is used for implementing communication connection between the second processor 81 and the second memory 82, the second processor 81 is used for executing a program of a data processing method in the second memory 82, so as to implement the following steps:

In other embodiments of the present invention, the second processor 81 is further configured to implement the following steps:

if the target data is detected to be damaged, acquiring first data from a second chip storage space and acquiring second data from a third chip storage space, wherein the steps of:

if the target data is detected to be damaged, acquiring a data zone bit of the electronic equipment;

setting a data flag bit as a first numerical value, and acquiring first data from a second chip storage space; wherein the first value is used to indicate target data corruption; the first data is data used for realizing initialization of a processor and a hardware chip of the electronic equipment in a pre-starting stage;

acquiring second data from a third chip storage space; the second data is data of the target data other than the first data.

based on the first data and the second data, a pre-boot phase of the electronic device is performed, comprising:

and executing a pre-starting stage of the electronic equipment based on the third data and the fourth data.

acquiring third data based on the first data and acquiring fourth data based on the second data, comprising:

storing the first data into a first chip storage space to obtain third data;

and storing the second data into the first chip storage space to obtain fourth data.

based on the third data and the fourth data, a pre-boot phase of the electronic device is performed, comprising:

executing a second sub-boot phase of the electronic device based on the fourth data; the pre-start-up phase comprises a first sub-start-up phase and a second sub-start-up phase.

after the first data is obtained from the second storage space based on the data flag bit, the method further includes:

In the data processing apparatus provided in the embodiment of the present invention, when the electronic apparatus executes a pre-boot stage, if it is detected that the target data is damaged, the data flag of the electronic apparatus is obtained, and the data flag is set to be the first data, so that the first data can be obtained from a second chip storage space of the electronic apparatus, the second data can be obtained from a third chip storage space of the electronic apparatus, and a pre-boot process of the electronic apparatus is executed based on the first data and the second data. Therefore, the data processing device provided by the embodiment of the invention can acquire the target data of the part corresponding to the damaged part of data from the corresponding chip storage space after any data in the pre-starting stage of the electronic device is damaged, so that the normal operation of the pre-starting stage can be ensured under the condition that any part of the target data is damaged.

Based on the foregoing embodiments, the embodiments of the present invention provide a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps of any of the data processing methods provided by the embodiments corresponding to fig. 1-3.

The computer-readable storage medium may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a magnetic Random Access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical Disc, or a Compact Disc Read-Only Memory (CD-ROM); and may be various electronic devices such as mobile phones, computers, tablet devices, personal digital assistants, etc., including one or any combination of the above-mentioned memories.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method described in the embodiments of the present invention.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A method of data processing, the method comprising:

processing the target data to obtain at least first data and second data;

2. The method of claim 1, wherein the processing the target data to obtain at least first data and second data comprises:

3. A data processing method, characterized in that the data processing method comprises:

4. The method of claim 3, wherein the obtaining the first data from the second chip memory space and the second data from the third chip memory space if the target data is detected to be corrupted comprises:

5. The method according to claim 3 or 4, wherein the performing a pre-boot phase of the electronic device based on the first data and the second data comprises:

6. The method of claim 5, wherein obtaining third data based on the first data and fourth data based on the second data comprises:

storing the first data into the first chip storage space to obtain third data;

7. The method of claim 5, wherein performing the pre-boot phase of the electronic device based on the third data and the fourth data comprises:

8. The method of claim 4, further comprising, after the retrieving the first data from the second storage space based on the data flag bit:

9. A data processing apparatus, characterized in that the data processing apparatus comprises: a first processor, a first memory, and a first communication bus;

processing the target data to obtain at least first data and second data;

10. A data processing apparatus, characterized in that the data processing apparatus comprises: a second processor, a second memory, and a second communication bus; the second communication bus is used for realizing communication connection between the first processor and the second memory;