JPH08154292A - Level compression circuit - Google Patents

Abstract

PURPOSE: To obtain a level compression circuit in which nonlinear distortion is reduced without causing deterioration in S/N. CONSTITUTION: An input signal ei is fed to a voltage division circuit 12 comprising a resistor 3 and a parallel circuit 13, in which the input signal is divided. After the voltage division signal is amplified by an amplifier circuit 7 and fed to peak rectifier circuits 8A, 8B and positive and negative peak rectifier signals PDa, PDb are fed to bases of transistors(TRs) 5A, 5B of series circuits 13A, 13B being components of the parallel circuit 13 as a control signal and an output signal vo subject to level compression control is obtained from the voltage division circuit 12. Dominant even order harmonic distortion components due to nonlinearity of the TRs 5A, 5B included in currents ia, ib flowing to the series circuits 13A, 13B among even and odd harmonic distortion components are opposite in the polarity to each other, and only the odd order harmonic distortion components are included in a current ip flowing to the parallel circuit 12 in addition to a fundamental component. Only the odd harmonic distortion components in addition to the fundamental component are in existence in the output signal vo and the nonlinear distortion is considerably reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level compression circuit suitable for application to, for example, a speaker device with a built-in amplifier.

[0002]

2. Description of the Related Art Conventionally, in a speaker device with a built-in amplifier, it has been known to provide a level compression circuit in the preceding stage of the speaker in order to prevent an excessive input to the speaker.

FIG. 5 shows the structure of a conventional level compression circuit. In the figure, 1a and 1b are input terminals,
An input audio signal ei is supplied between the input terminals 1a and 1b. The input terminal 1b is grounded and the input terminal 1b
a is a resistor 3, a resistor 4 and an N which constitute the voltage dividing circuit 2.
The PN transistor 5 is grounded via a collector-emitter series circuit. Then, the output terminal of the voltage dividing circuit 2,
Therefore, from the connection point of the resistors 3 and 4 to the output terminal 6
The output terminal 6b is grounded as a is derived. In this case, in the voltage dividing circuit 2, the audio signal ei is divided by the resistor 3 and the series impedance of the resistor 4 and the collector-emitter of the transistor 5, and the divided signal is output between the output terminals 6a and 6b. It is output as the output audio signal vo.

The voltage division signal output from the voltage division circuit 2, that is, the voice signal vo, is amplified by the amplification circuit 7 and then supplied to the peak rectification circuit 8. That is, the output terminal of the amplifier circuit 7 is grounded via the series circuit of the anode / cathode of the diode 9 and the capacitor 10. Also, the output terminal of the peak rectification circuit 8, and hence the diode 9
And the connection point of the capacitor 10 is connected to the base of the transistor 5 via the resistor 11, and the peak rectification signal PD
Is supplied to the base of the transistor 5 as a control signal.

In the above configuration, assuming that the resistance values of the resistors 3 and 4 are R ₁ and R ₂ , respectively, and the impedance value between the collector and the emitter of the transistor 5 is Rx, the level of the input audio signal ei is small and the peak rectification signal is low. PD is about 0.6
When V or less, Rx >> R ₁ and R ₂ , and therefore the output audio signal vo becomes substantially equal to the input audio signal ei. However, when the level of the input audio signal ei becomes large and the peak rectified signal PD exceeds 0.6V, the impedance value Rx between the collector and the emitter of the transistor 5 exponentially decreases exponentially. Due to the level compression operation by, the increase in the level of the output audio signal vo is limited.

A solid line a in FIG. 6 shows the level compression characteristic of the level compression circuit of the example of FIG. E ₁ is an input signal level for the peak rectified signal PD to be about 0.6 V (compression start input level), and E ₂ is an input signal level for the peak rectified signal PD to be a voltage at which the transistor 5 is saturated. is there. In this case, level compression range is in the range of E ₁ to E _2, the level compression range is dependent on the value of R ₁ / R _2, it becomes wider as the value of the R ₁ / R ₂ is greater. The compression ratio depends on the magnitude of the value of R ₂ . The broken line b in FIG. 6 shows the input / output characteristics when the level compression control is not performed while the transistor 5 is in the off state.

[0007]

By the way, in the level compression circuit of the example of FIG.
There is a problem in that the output signal is distorted due to the non-linearity. If the compression start input level E ₁ is made considerably low by increasing the gain of the amplifier circuit 7, the above-mentioned non-linear distortion can be kept sufficiently small, but in that case, there is a problem that the SN ratio deteriorates. Occurs.

Therefore, the present invention provides a level compression circuit capable of reducing non-linear distortion without degrading the SN ratio.

[0009]

A level compression circuit according to a first aspect of the present invention is a parallel circuit comprising a first resistor, a second resistor and two collector / emitter series circuits connected in parallel. A voltage dividing means for dividing the voltage with the combined impedance of the two, and the transistors forming one and the other of the two series circuits are NPN-type transistors and PNP-type transistors, respectively, and the input signal is supplied to the voltage-dividing means and divided. The voltage-divided signal output from the voltage-dividing means is directly or amplified and then supplied to the first and second peak rectifying means for peak rectification, and the positive peak rectification output from the first peak rectifying means. The signal is supplied as a control signal to the base of the NPN type transistor which constitutes one of the series circuits, and the negative polarity peak output from the second peak rectifying means is supplied. The rectified signal is supplied as a base to a control signal of the PNP type transistor constituting the other series circuit, it is characterized in that the output signal of the divided signal outputted from the voltage dividing means.

[0010]

In the invention of claim 1, since the control signal corresponding to the output signal level is supplied to the bases of the transistors of the one and the other series circuits which form the parallel circuit of the voltage dividing means to control the impedance, The voltage dividing means performs level compression control according to the input signal level, and the output signal output from the voltage dividing means is level-compressed.

In this case, the currents flowing through the one series circuit and the other series circuit are nonlinearly distorted due to the nonlinearity of the transistors in the level compression range. However, NP is used as the transistor of the series circuit of one side and the other side, respectively.
Since the N-type transistor and the PNP-type transistor are used, the even harmonic distortion components included in the currents flowing in the one and the other series circuits have polarities opposite to each other, and the currents flowing in the one and the other series circuits are changed. The dominant even harmonic distortion components are canceled by combining.

Therefore, the current flowing through the parallel circuit has only odd-order harmonic distortion components other than the fundamental wave component, and the output signal output from the voltage dividing means has only odd-order harmonic distortion components other than the fundamental wave component. In the level compression range, it is possible to significantly reduce the non-linear distortion caused by the non-linearity of the transistor. Further, unlike the conventional method, the compression start input level is lowered to keep the non-linear distortion small.
It does not cause deterioration of the ratio.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the level compression circuit according to the present invention will be described below with reference to FIG. This example is an example applied to the level compression control of an audio signal. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals.

In the figure, 1a and 1b are input terminals, and an input audio signal ei is supplied between these input terminals 1a and 1b. The input terminal 1b is grounded. Input terminal 1a
Is a resistor 3 and a parallel circuit 1 that constitute the voltage dividing circuit 12.
3 through a series circuit. The parallel circuit 13 is a collector of the resistor 4A and the NPN transistor 5A.
Emitter series circuit 13A and resistor 4B and PNP transistor 5B collector-emitter series circuit 13
B and B are connected in parallel. In this case, when the resistance value of the resistor 4A of the series circuit 13A is set to R ₂ ,
The resistance value of the resistor 4B of the series circuit 13B is also set to R ₂ .

The output terminal of the voltage dividing circuit 12, and thus the resistor 3
The output terminal 6a is led out from the connection point of the parallel circuit 13 and the output terminal 6b is grounded. In this case, in the voltage dividing circuit 12, the input audio signal ei is divided by the impedance of the resistor 3 and the parallel circuit 13, and the divided signal is output as the output audio signal vo between the output terminals 6a and 6b. .

Further, the divided voltage signal output from the voltage dividing circuit 12, that is, the output voice signal vo is amplified by the amplifying circuit 7 and then supplied to the peak rectifying circuit 8A. That is, the output terminal of the amplifier circuit 7 is grounded through the series circuit of the anode / cathode of the diode 9A and the capacitor 10A. The output terminal of the peak rectification circuit 8A, that is, the connection point of the diode 9A and the capacitor 10A is connected to the base of the transistor 5A forming the series circuit 13A via the resistor 11A, and the positive peak rectification signal P
Da is supplied to the base of the transistor 5A as a control signal.

Further, the divided signal output from the voltage dividing circuit 12, that is, the output voice signal vo is amplified by the amplifying circuit 7 and then supplied to the peak rectifying circuit 8B. That is, the output terminal of the amplifier circuit 7 is grounded via the series circuit of the cathode / anode of the diode 9B and the capacitor 10B. The output terminal of the peak rectification circuit 8B, that is, the connection point of the diode 9B and the capacitor 10B is connected to the base of the transistor 5B forming the series circuit 13B via the resistor 11B, and the peak rectification signal P of the negative polarity is generated.
Db is supplied to the base of the transistor 5B as a control signal.

In the above configuration, the resistance value of the resistor 3 is R ₁ , the resistance values of the resistors 4A and 4B are R ₂ , respectively, and the collector-emitter impedance values of the transistors 5A and 5B are Rxa and Rxb. If the impedance value of 13 is Rp and the level of the input audio signal ei is small and the absolute values of the peak rectified signals PDa and PDb are about 0.6 V or less, then Rxa, Rxb >> R ₁ and R ₂ , Rp >>
Since it becomes R ₁ , the divided voltage signal output from the voltage dividing circuit 12 becomes substantially equal to the input audio signal ei.

However, the level of the input audio signal ei increases and the absolute value of the peak rectified signals PDa and PDb becomes 0.6.
When the voltage exceeds V, the impedance values Rxa and Rxb between the collector and the emitter of the transistors 5A and 5B decrease exponentially and exponentially. Therefore, the level compression operation by the voltage dividing circuit 12 limits the level increase of the voltage divided signal. . Therefore, the output audio signal vo obtained between the output terminals 6a and 6b
Is subjected to level compression control as in the example of FIG. 5 (see the level compression characteristic indicated by the solid line a in FIG. 6).

By the way, the current flowing through the series circuits 13A and 13B forming the parallel circuit 13 of the voltage dividing circuit 12 is represented by ia,
When ib is set, the currents ia and ib have nonlinear distortion due to the nonlinearity of the transistors 5A and 5B in the level compression range, but the output audio signal vo output from the voltage dividing circuit 12 has nonlinear distortion. Is greatly reduced.

FIG. 2 shows the principle of reducing nonlinear distortion. The nonlinearity of the transistors 5A and 5B is shown in FIG.
The second-order nonlinearity is assumed as indicated by the solid line a and the one-dot chain line b. In this case, transistor 5
The quadratic non-linearity of A and 5B is completely symmetrical with respect to the origin (0,0). The solid line c in FIG. 2B is a characteristic that is a characteristic obtained by combining the quadratic nonlinearities of the transistors 5A and 5B and is a straight line.

When an input audio signal ei (positive signal) as shown by the solid line d in FIG. 2A is supplied to the voltage dividing circuit 12,
The current ia flowing through the series circuit 13A is expanded on the positive side and compressed on the negative side as shown by the solid line e in FIG. 2C to become a positive current having an asymmetrical waveform distortion.
The current ib flowing through B is compressed on the positive side and expanded on the negative side as shown by the alternate long and short dash line f in FIG. 2C, and becomes a positive current having asymmetric waveform distortion.

Therefore, the current i flowing in the parallel circuit 13
The combined current ip of a and ib is obtained by removing the asymmetrical waveform distortion as shown by the solid line g in FIG. 2C. Therefore, the output voice signal vo output from the voltage dividing circuit 12 is the transistor 5
The non-linear distortion caused by the non-linearity of A and 5B is removed.

By the way, the reduction principle of FIG. 2 assumes a second-order nonlinearity as the nonlinearity of the transistors 5A and 5B. In that case, only even-order harmonic distortion is generated as the nonlinear distortion. . However, in reality, the transistor 5
A and 5B do not have perfect second-order nonlinearity, and in addition to the even-order harmonic distortion that is the main nonlinear distortion described above, odd-order harmonic distortion also occurs.

In this case, since the transistors 5A and 5B are NPN type and PNP type, respectively, the currents ia and ib are
The even-order harmonic distortion components generated in 1) have opposite polarities and are canceled by combining these currents ia and ib.
Therefore, the current ip flowing through the parallel circuit 13 has only odd-order harmonic distortion components other than the fundamental wave component, and the output audio signal vo output from the voltage dividing circuit 12 also has odd-order harmonic distortion components other than the fundamental wave component. In this case, the non-linear distortion caused by the non-linearity of the transistors 5A and 5B is reduced in the level compression range.

For example, when the input audio signal ei is a positive sine wave signal of Eisinωt, the current ia flowing through the series circuit 13A is expressed by the equation (1). here,
Ei is the amplitude of the sine wave signal, I ₁ is the amplitude of the fundamental wave component,
I ₂ , I ₃ , I ₄ , ... Are secondary, tertiary, quaternary, respectively.
Amplitude of harmonic distortion component of Φ ₂ , Φ ₃ , Φ ₄ ,
Indicate the phase angles of the second, third, fourth, ... Harmonic distortion components, respectively.

Ia = I ₁ sin ωt + I ₂ sin (2ωt + φ ₂ ) + I ₃ sin (3ωt + φ ₃ ) + I ₄ sin (4ωt + φ ₄ ) + I ₅ sin (5ωt + φ ₅ ) + ... (1) At this time, (1) Assuming that the equation (1) uses the NPN transistor, the polarity of only the even harmonic distortion component of the current ib flowing in the series circuit 13B using the PNP transistor is inverted, It is expressed as in equation (2).

Ib = I ₁ sin ωt−I ₂ sin (2ωt + φ ₂ ) + I ₃ sin (3ωt + φ ₃ ) −I ₄ sin (4ωt + φ ₄ ) + I ₅ sin (5ωt + φ ₅ ) −... (2) Therefore, The current ip flowing through the parallel circuit 13 is (3)
It is expressed as an expression. That is, the even harmonic distortion components are canceled out, and only the fundamental wave component and the odd harmonic distortion components are left.

Ip = 2I ₁ sin ωt + 2I ₃ sin (3ωt + φ ₃ ) + 2I ₅ sin (5ωt + φ ₅ ) + 2I ₇ sin (7ωt + φ ₇ ) + ... (3) Thus, according to this example, the parallel circuit 13 Current i flowing through
p, therefore the output audio signal vo output from the voltage dividing circuit 12
Is only the fundamental wave component and the odd harmonic distortion component, and it is possible to reduce the non-linear distortion caused by the non-linearity of the transistors 5A and 5B in the level compression range. Here, the odd harmonic distortion is smaller than the even harmonic distortion, and by canceling the even harmonic distortion components, the total harmonic distortion rate can be greatly reduced.

A curve a in FIG. 3 shows an example of actual measurement of the distortion characteristic in the embodiment of FIG. 1 in the case of having the level compression characteristic as shown by the solid line a in FIG. 4 (the broken line b in FIG. 4 indicates the level compression). Input / output characteristics when no control is performed). A solid line b in FIG. 3 is an example of actual measurement of distortion characteristics in the conventional example of FIG.
As is clear from FIG. 3, the total harmonic distortion can be greatly reduced in the embodiment. The level compression characteristics and distortion characteristics are
It hardly changes in the audio frequency range.

In the above embodiment, the voltage dividing circuit 1
Although the divided voltage signal output from 2 is amplified by the amplifier circuit 7 and then supplied to the peak rectifier circuits 8A and 8B,
Depending on the level of the voltage-divided signal, it is possible to directly supply the voltage-divided signal to the peak rectifier circuits 8A and 8B, or to supply it to the peak rectifier circuits 8A and 8B after the level is attenuated. Further, in the above embodiment, the one having the two peak rectification circuits 8A and 8B is shown.
Only one peak rectification circuit may be provided, and peak rectification signals of other polarities may be obtained through the polarity inverting circuit. Further, in the above-mentioned embodiment, the example in which the present invention is applied to the level compression control of the audio signal is shown, but it goes without saying that the present invention can also be applied to the level compression control of other signals.

[0032]

According to the invention of claim 1, an NPN type transistor and a PNP are respectively used as transistors of one and the other series circuits constituting the parallel circuit of the voltage dividing means.
-Type transistors are used, the even harmonic distortion components contained in the currents flowing in one and the other series circuits have opposite polarities, and are controlled by combining the currents flowing in these one and the other series circuits. The even harmonic distortion components are canceled out. Therefore, the current flowing through the parallel circuit has only odd-order harmonic distortion components other than the fundamental wave component, and the output signal output from the voltage dividing means also has only odd-order harmonic distortion components other than the fundamental wave component, and level compression is performed. The non-linear distortion caused by the non-linearity of the transistor can be significantly reduced within the range, and the non-linear distortion is not kept small by lowering the compression start input level as in the past, and the SN ratio is not deteriorated. .

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a level compression circuit according to the present invention.

FIG. 2 is a diagram showing a principle of reducing nonlinear distortion according to an embodiment.

FIG. 3 is a diagram showing an example of actual measurement of distortion characteristics of an example and a conventional example.

FIG. 4 is a diagram showing an example of level compression characteristics according to the embodiment.

FIG. 5 is a configuration diagram showing a conventional level compression circuit.

FIG. 6 is a diagram showing an example of level compression characteristics.

[Explanation of symbols]

 1a, 1b Input terminal 3, 4A, 4B Resistor 5A NPN type transistor 5B PNP type transistor 6a, 6b Output terminal 7 Amplifying circuit 8A, 8B Peak rectifying circuit 12 Voltage dividing circuit 13 Parallel circuit 13A, 13B Series circuit

Claims (1)

[Claims] 1. A voltage dividing means for dividing a voltage by a first resistance and an impedance of a parallel circuit formed by connecting two series circuits of a second resistor and a collector / emitter of a transistor in parallel. Of the series circuit of NPN type transistor and PN, respectively.
It is a P-type transistor, the input signal is supplied to the voltage dividing means to divide the voltage, and the divided signal output from the voltage dividing means is supplied to the first and second peak rectifying means as it is or after being amplified, and then the peak is obtained. The NPN that rectifies the positive peak rectified signal output from the first peak rectifying means and constitutes the one series circuit.
Of the negative polarity peak rectification signal supplied from the second peak rectification means as a control signal to the base of the transistor and forming the other series circuit.
A level compression circuit characterized in that it is supplied as a control signal to the base of a transistor and the divided voltage signal output from the voltage dividing means is used as an output signal.