JPS62285508A - Freequency characterstic adjusting circuit - Google Patents

Abstract

PURPOSE:To vary the gain at an optional frequency without changing the phase characteristic and the delay characteristic by constituting the titled circuit with a 1st, a 2nd and a 3rd amplifiers whose output signal is fed to an inverting input respectively, a capacitor and a control circuit. CONSTITUTION:The frequency characteristic adjusting circuit suitable for the sharpness control of a VTR is provided with the 1st and the 2nd amplifiers 1, 2 whose noninverting input receives an input signal and whose output signal is fed to the inverting input 5, the 3rd amplifier 3 whose noninverting input 5 receives a noninverting output of the 2nd amplifier 2 and whose output signal is fed to the inverting input 5, a 1st capacitor 6 inserted between the input and output, a capacitor 7 provided between the noninverting output of the 2nd amplifier 2 and ground, and a control circuit 4 controlling the mutual conductance of the lst amplifier 1. Thus, the gain of an optional frequency is varied without changing the phase characteristic and the delay characteristic.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a frequency characteristic adjustment circuit suitable for use, for example, in sharpness control of a VTR.

[Summary of the invention]

The present invention provides a frequency characteristic adjustment circuit suitable for use, for example, in sharpness control of a VTR, in which an input signal is supplied to a positive-phase input terminal, and an output signal is supplied to a negative-phase input terminal. A second amplifier, a third amplifier whose positive phase output of the second amplifier is supplied to the positive phase input terminal, and whose output signal is supplied to the negative phase input terminal, are inserted between the input and the output. By providing the first capacitor, the capacitor provided between the positive phase output of the second amplifier and ground, and the control circuit that controls the mutual conductance of the first amplifier, the phase characteristics and delay characteristics are changed. This allows the gain of any frequency to be varied without any interference.

[Conventional technology]

Sharpness control on a VTR uses high frequency components such as 2M1L.
This is achieved by increasing the gain of, for example, the 2M Ilz frequency component in the reproduced video signal using a frequency characteristic adjustment circuit that controls the gain of the z frequency component.

That is, by increasing the high-frequency components in the reproduced video signal, the edge portions of the video signal are emphasized and the outline is emphasized.

In this way, any frequency in the video signal, e.g. 2 M
Conventionally, a frequency characteristic adjustment circuit for controlling the Hz gain has been configured as shown in FIG.

In Fig. 5, 151 indicates that the center frequency f0 is 2MH, for example.
z bandpass filter. A video signal from input terminal 152 is supplied to adder circuit 153 and also to bandpass filter 151 . A bandpass filter 151 extracts a 2 MHz frequency component signal from the video signal. The output of the bandpass filter 151 is supplied to a variable gain amplifier 154. amplifier 15
The gain of 4 is varied by a control signal from terminal 155. The output of amplifier 154 is supplied to adder circuit 153. The adder circuit 153 outputs the video signal from the input terminal 152 and the bandpass filter 151 outputs the video signal to the amplifier 1.
For example, a signal having a frequency component of 2 MHz, the gain of which has been adjusted in step 54, is added. The output of adder circuit 153 is taken out from output terminal 156.

[Problem that the invention seeks to solve]

In the conventional frequency characteristic adjustment circuit described above, not only its gain characteristic but also its delay characteristic and phase characteristic change. If the delay characteristics and phase characteristics change, a problem arises in that ringing appears and the screen becomes distorted. Therefore, this delay characteristic and phase characteristic may be
It is necessary to compensate with an equalizer as shown in the specification of the above patent.

However, in the conventional frequency characteristic adjustment circuit described above, when the gain characteristic is changed, the delay characteristic and phase characteristic also change. Therefore, it is necessary to perform phase compensation according to the change, and the equalizer having fixed characteristics as described above cannot perform this compensation.

Therefore, an object of the present invention is to provide a frequency characteristic adjustment circuit that can vary the gain of any frequency without changing the phase characteristics and delay characteristics.

[Means for solving problems]

This invention includes first and second amplifiers in which an input signal is supplied to a positive phase input terminal and an output signal is supplied to a negative phase input terminal, and a positive phase output of the second amplifier is supplied to a positive phase input terminal. a third amplifier whose output signal is supplied to the terminal and whose output signal is supplied to the input terminal of opposite phase; a first capacitor inserted between the input and the output; and a first capacitor inserted between the positive phase output of the second amplifier and ground. This is a frequency characteristic adjustment circuit that includes a capacitor that is connected to the first amplifier, and a control circuit that controls the mutual conductance of the first amplifier.

[Effect]

Amplifier 1. Amplifier 2. Amplifier 3. The transfer function of the circuit consisting of capacitor 6° and capacitor 7 is H = r3
It becomes r3. This transfer function is the sum of the transfer function of the characteristics of the bandpass filter and the transfer function of the equalizer. Here, when the mutual conductance (1, /r3) of the amplifier 1 is changed, the gain of the center frequency of the bandpass filter is changed. At this time, the delay characteristics of the equalizer also change accordingly. As a result, the output delay characteristics and phase characteristics hardly change.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. A description of this embodiment will follow in the following order.

・a, basic configuration, concrete configuration a, basic configuration In FIG. 1, 1, 2.3 are amplifiers each having a differential circuit as a basic configuration. The amplifier 1 is configured such that its mutual conductance gm can be arbitrarily set by the output of the gm control circuit 4.

Non-inverting input terminals of amplifier 1 and amplifier 2 are connected to input terminal 5, and amplifier 1. Amplifier 2. An inverting input terminal of amplifier 3 is connected to output terminal 8. An inverted output terminal of amplifier 1 is connected to output terminal 8.

A non-inverting output terminal of amplifier 2 is connected to a non-inverting input terminal of amplifier 3, and a non-inverting output terminal of amplifier 3 is connected to output terminal 8. A capacitor 6 is connected between the input terminal 5 and the output terminal 8. A capacitor 7 is connected between the non-inverting output terminal of the amplifier 2 and ground.

The gm'MI control circuit 4 is configured to set the mutual conductance gm of the amplifier 1 based on its current value. g
A variable current circuit 9 is connected to the m control circuit 4. By varying the current of this variable current circuit 9, the mutual conductance gm of the amplifier 1 can be arbitrarily set.

1 In this embodiment, by changing the mutual conductance gm of the amplifier 1, the gain at an arbitrary frequency can be varied. Even when the frequency characteristics are varied in this way, the delay characteristics hardly change. This will be explained below.

The transfer function of the embodiment of the present invention shown in FIG. 1 is determined as follows.

In Figure 1, the mutual conductance gm of amplifier 1 is 1/r3, and the mutual conductance gm of amplifier 2 is 1/r3.
/r2, and the mutual conductance gm of amplifier 3 is 1/
The capacitance of the capacitor 6 is C, and the capacitance of the capacitor 7 is 02. The input signal is Vin, the output signal is Vo, and the signal vy at the intermediate point Y is
Then, it becomes rz JωC2. Therefore, from the formula 00, the transfer function H can be obtained as r+'''...■.

In general, the quadratic transfer function is denoted by Q and ω. is obtained from the formula (■) and the formula (■).

However, it is assumed that r<r3.

Here, if we transform the formula 0, r:I
r31+jωc2rz(1--) +(jω)
“Car, car.

′°　　　　　・・・■ becomes.

■The formula is 1-jωczrz(1-)+(jω)”clr+ctr
2−−1−−−−−−−−−−−−−−−−−1−=
−・・・■1+jωCzl”z(1--)+(jω)2
clr+czrz formula and jωcart (12) 1−−−−−−−−−−−−−−−−・・・■1+j
ωCzrz (1) + (Jω)”clr+czi The equation 0 shows the characteristics of an equalizer with constant gain.The equation 0 shows the characteristics of the i<nd pass filter. Therefore, this embodiment has characteristics that combine the characteristics of an equalizer and those of a bandpass filter.

r*=2. If r+ is set to (, then the 0 expression becomes 0.

At this time, the force has the characteristics of an equalizer.

If r3 is set to a large value, equation 0 takes a negative value. At this time, a dip occurs at the center frequency.

When r is set to a small value, the value obtained by the formula 0 becomes large, and the peak at the center frequency becomes large.

In this way, the frequency characteristics are set by changing the mutual conductance g m (g m = 1 /rs) of the amplifier 1.

In other words, this frequency characteristic adjustment and phase compensation circuit supplies the input signal Vin to the equalizer 12 and the bandpass filter 13, as shown in the equivalent block diagram in FIG.
This is equivalent to adding the output of the equalizer 12 and the output of the bandpass filter 13 using the adder 14. In order to change the frequency characteristics of the bandpass filter 13, the terminal 1
When the mutual conductance 1/r of the amplifier 1 is changed by supplying a control signal to the bandpass filter 13, the delay characteristics of the bandpass filter 13 are changed. At this time, when the mutual conductance 1/r of the amplifier 1 is changed, the delay characteristics of the equalizer 12 are changed to compensate for the delay characteristics of the bandpass filter 13. As a result, the output delay characteristics hardly change at all times.

Hereinafter, specific numerical values will be substituted to show the characteristics in each case, and it will be shown that the delay characteristics and phase characteristics are approximately constant. FIGS. 3A to 3F show the respective characteristics in the cases shown in the table below. The Q of the circuit is determined by r, rt, r, and the center frequency f0 is determined by rl and r2. In this example, r.

is 3468Ω, r2 is 31050Ω, center circumference fatigue number r0
is set to 2MH2.

As is clear from the graphs shown in Figures 3A to 3F,
The delay characteristics and phase characteristics are approximately constant no matter how the mutual conductance g m (= 1 /r3) of the amplifier l is changed and the gain of the center frequency f0 is changed.

b. Specific configuration FIG. 4 shows a specific configuration of an embodiment of the present invention.

In FIG. 4, numerals 51, 52, and 53 are amplifiers each having a differential circuit as a basic configuration. These amplifiers 51-53 are of modified Gilbert type.

These amplifiers 51, 52, and 53 correspond to amplifiers 1, 2, and 3 in FIG. 1 described above, respectively. Further, capacitors 54 and 55 in FIG. 4 correspond to capacitors 6 and 7 in FIG. 1, respectively.

The amplifier 51 is composed of transistors 56 and 57 whose emitters are commonly connected. transistor 56
and a transistor 58 whose emitter of 57 serves as a current source.
．． 59 and connected to the collector of transistor 58.59
The emitter of is connected to the ground terminal 50 via a resistor 60.

The collector of the transistor 56 is connected to the collector of a PNP transistor 61 serving as a current source, and is also connected to one end of the capacitor 54.

The emitter of transistor 1 is connected to +Vc through resistor 62.
It is connected to the power supply terminal 49 of c. A collector of the transistor 57 is connected to the power supply terminal 49.

The bases of the transistors 61 are commonly connected to the bases of the transistors 63, and this connection point is connected to the output terminal of the gm control and variable current circuit 120! The emitter of transistor 63 is connected to power supply terminal 49 via resistor 65. The collector of transistor 63 is connected to the collector of transistor 66 and to the base of transistor 67. The emitter of the transistor 66 is the resistor 68
It is connected to the ground terminal 50 via. transistor 67
The collector of is connected to the power supply terminal 49. The emitter of transistor 67 is connected to ground terminal 50 via resistor 69, the emitter of transistor 67 and the base of transistor 66 are commonly connected, and this connection point is connected to the bases of transistors 58 and 59.

The gm*I control and variable current circuit 120 performs voltage-to-current conversion on the side control voltage from the terminal 121, and forms a current based on this control voltage. This g, m
Depending on the current generated by the ar control and variable current circuit 120, the current flowing through the transistor 63 and the current flowing through the transistor 61 are determined by the current mirror circuit. Further, the current flowing through the transistor 63 determines the current flowing through the transistor 66, and the current flowing through the transistors 58 and 59 which are connected to the transistor 66 in a current mirror manner. Therefore, when the control voltage supplied to terminal 121 is varied, the current flowing through transistor 61 and the current flowing through transistors 58 and 59 changes.

The base of the transistor 56 is connected to the emitter of the transistor 71 via a resistor 70, and the diode 7
7 to the collector of a transistor 78 which operates as a current source. The emitter of transistor 78 is connected to ground terminal 50 via resistor 79. A collector of transistor 71 is connected to power supply terminal 49 . The base of the transistor 71 is connected to the other end of the capacitor 54, and is also connected to a PNP type transistor transmitter. The emitter of transistor 72 is connected to the collector of transistor 73 as a current source. The emitter of transistor 73 is connected to power supply terminal 49 via resistor 74 . The base of the transistor 72 is the input terminal 12
2, and the collector of the transistor 72 is connected to the ground terminal 50.

A non-inverting input of amplifier 51 is supplied to the base of transistor 56. This input is connected to emitter follower transistor 72. It is supplied via an emitter follower transistor 71. Transistor 73 drives emitter follower transistor 72. Transistor 78 drives emitter follower transistor 71. Amplifier 5
The inverting input of 1 is provided to the base of transistor 57.

The inverted output of amplifier 56 is taken from the collector of transistor 56. Transistor 61 operates as an active load.

The amplifier 52 is composed of transistors 81 and 82 whose emitters are commonly connected. transistor 81
and the emitter of 82 is a transistor 83 as a current source.
connected to the collector of

The emitter of transistor 83 is connected to ground terminal 50 via resistor 84. The base of transistor 83 is connected to terminal 85.

A collector of transistor 81 is connected to power supply terminal 49 . The collector of transistor 82 is PN as a current source.
It is connected to the collector of the PN upper type resistor 86, and
Connected to the base of transistor 87. Capacitor 55 is connected between the base of transistor 87 and ground.

The emitter of transistor 86 is connected to power supply terminal 49 via resistor 88 .

The base of transistor 81 is connected to the base of transistor 56. The base of transistor 82 is connected to the emitter of transistor 90 via resistor 89 and to the collector of transistor 78 via diode 91. A collector of transistor 90 is connected to power supply terminal 49. The base of transistor 90 is connected to output terminal 92.

A non-inverting input of amplifier 52 is supplied to the base of transistor 81. Since the base of transistor 81 is commonly connected to the base of transistor 56, this input, like amplifier 51, is connected to emitter follower transistors 72 . It is supplied via an emitter follower transistor 71. The inverting input of the amplifier 52 is connected to the transistor 82.
supplied to the base of This input is provided via emitter follower transistor 90. The non-inverting output of amplifier 52 is taken from the collector of transistor 82. Transistor 86 operates as an active load.

The amplifier 53 is composed of transistors 93 and 94 whose emitters are commonly connected. The emitters of transistors 93 and 94 are connected to the collectors of transistors 95 and 96, which act as current sources. transistor 95
．． The emitter of 96 is connected to the ground terminal 50 via a resistor 97. The bases of transistors 95 and 96 are connected to terminal 8.
Connected to 5.

A collector of transistor 93 is connected to power supply terminal 49 . A collector of transistor 94 is connected to a collector of a PNP transistor 98 that operates as a current source, and is also connected to output terminal 92 . The emitter of transistor 98 is connected to power supply terminal 49 via resistor 99.

The base of transistor 93 is connected to the emitter of transistor 87 via resistor 100, and is also connected via diode 101 to the collector of transistor 02 as a current source. The emitter of transistor 02 is connected to ground terminal 50 via resistor 103. The base of transistor 94 is connected to the emitter of transistor 05 via resistor 104 and to the collector of transistor 02 via diode 106. The collector of transistor 05 is connected to power supply terminal 49. The base of transistor 05 is connected to output terminal 92.

A non-inverting input of amplifier 53 is supplied to the base of transistor 93. This input is supplied via an emitter and lower transistor 87. The inverting input of amplifier 53 is supplied to the base of transistor 94. This input is provided via emitter follower transistor 105. The non-inverting output of the amplifier 53 is connected to the transistor 94.
from the collector. Transistor 98 operates as an active load.

Terminal 85 is connected to the base of transistor 107, and the emitter of transistor 107 is connected to ground terminal 50 through a resistor. The collector of transistor 107 is connected to the collector of transistor 109, and
Connected to the base of transistor 110. The emitter of the transistor 109 is connected to the power supply terminal 49 via the resistor 111.
connected to. The base of transistor 109 is connected to transistor 73. Transistor 86. Commonly connected to the base of transistor 98. The emitter of the transistor 110 is connected to the power supply terminal 49 via the resistor 112, and
Connected to the base of transistor 109. A collector of transistor 110 is connected to ground terminal 50.

A DC voltage Vr, for example 0.9V, is supplied to the terminal 85. This allows the transistor 8 to operate as a constant current source.
3. Transistors 95, 96. ) The transistor 107 is activated. The current flowing through the transistor 107 drives the transistors 109, 110, and the transistors 73, 86, and 98 connected in a current mirror with the transistor 109, 110.

The bases of the transistors 78 and 102 are the transistor 11
Connected to the base of 3. The emitter of transistor 113 is connected to ground terminal 50 via resistor 114. The collector of transistor l13 is connected to terminal 106 via resistor 115 and to the base of transistor 118. The emitter of transistor 118 is connected to ground terminal 50 via resistor 117 and to the base of transistor 113. transistor 1
18 collectors are connected to a power supply terminal 49.

A DC voltage Vr is applied to the terminal 116, for example (4,2V-V■)
is supplied (■, = base-emitter voltage). This DC voltage causes current to flow through the resistor 1.15, thereby driving the transistors 113 and 118. The current flowing through transistor 113 causes transistor 78 .
Transistor 102 is activated.

An input signal is provided to an input terminal 122 derived from the base of emitter follower transistor 72 . This input signal is supplied from the emitter of the transistor 72 via the emitter follower transistor 71 to the base of the transistor 56, which is the non-inverting input terminal of the amplifier 51, and the base of the transistor 81, which is the non-inverting input terminal of the amplifier 52. supplied to The output signal from the output terminal 92 is supplied to the base of a transistor 94 which is an inverting input terminal of the amplifier 53 via an emitter follower transistor 105, and is also supplied to the base of a transistor 94 which is an inverting input terminal of the amplifier 52 via an emitter follower transistor 90. 82 and the base of the transistor 57 which is the inverting input terminal of the amplifier 51. A capacitor 54 is connected between the collector of the transistor 56, which is the inverting output terminal of the amplifier 51, and the emitter of the emitter follower transistor 72, and the output of the collector of the transistor 56 is outputted to the output terminal 92. The output of the collector of the transistor 82, which is the non-inverting output terminal of the amplifier 52, is connected to the amplifier 3 via an emitter follower transistor 87.
The non-inverting input terminal of the transistor 93 is supplied to the base of the transistor 93. Between the collector of transistor 82 and ground,
A capacitor 55 is connected. The output of the collector of transistor 94, which is the non-inverting output terminal of amplifier 53, is supplied to output terminal 92.

Therefore, the circuit configuration consisting of these amplifiers 51, 52, 53 and capacitors 54, 55 is similar to the configuration shown in FIG.

The mutual conductance gm of amplifier 51 is equal to the current flowing through transistor 61 and transistor 58.

This is done by controlling the current flowing through 59.

This current is gm
It is controlled by the current generated by the control and variable current circuit 121.

〔Effect of the invention〕

According to this invention, the gain of any frequency can be varied without substantially changing the phase characteristics and delay characteristics. Furthermore, the phase and delay characteristics in the low range do not change due to changes in the gain characteristics. Therefore, ringing will not occur and the screen will not be disturbed.

Further, according to the present invention, since it can be configured with only an amplifier and a capacitor, it is easy to integrate it into an integrated circuit.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the basic configuration of an embodiment of this invention, Fig. 2 is an equivalent block diagram used to explain an embodiment of this invention, and Fig. 3 is used to explain an embodiment of this invention. 4 is a connection diagram showing a specific configuration of an embodiment of the present invention, and FIG. 5 is a block diagram of a conventional frequency characteristic adjustment circuit. Explanation of main symbols in the drawings 1.2.3: Amplifier, 6, 7: Capacitor, 4:
gm control circuit, 9: variable current circuit. Agent Patent Attorney Masato Sugiura Figure 5 Figure 3 A Figure 3 C

Claims (1)

[Claims] first and second amplifiers in which an input signal is supplied to a positive-phase input terminal and an output signal is supplied to a negative-phase input terminal; and a positive-phase output of the second amplifier is supplied to a positive-phase input terminal. a third amplifier to which the output signal is supplied to an input terminal of opposite phase; a first capacitor inserted between the input and the output; and a first capacitor connected between the positive phase output of the second amplifier and ground. and a control circuit for controlling mutual conductance of the first amplifier.