JP2002198798A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit that can suppress fluctuations in a bias point due to the effect by the load while suppressing ringing. SOLUTION: A 1st resistor R1-1 and a 2nd resistor R2-2 are connected in series between output terminals providing a couple of differential voltages in a monolithic integrated circuit and a bias circuit 1-3 providing a center bias voltage of a modulation voltage is connected to a connection point between the 1st resistor R1-1 and the 2nd resistor R2-2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit for outputting voltages complementary to each other in a monolithic integrated circuit.

[0002]

2. Description of the Related Art Conventionally, an emitter follower is often used as an output circuit, and since it has a low output impedance characteristic, it is widely known as an output circuit which is hardly affected by a load. In particular, in a semiconductor integrated circuit,
It is common practice to use an emitter follower in combination with the output circuit after the differential amplifier circuit, and the output difference voltage signal is capable of removing various common-mode noises and outputting a very good waveform. . However, when the emitter follower is equivalently loaded with a capacitive load due to, for example, wiring or an input circuit at the next stage, the output waveform may cause oscillation called ringing. This ringing is a phenomenon that appears remarkably as the modulation speed increases. on the other hand,
Although various common-mode noises can be removed by using a differential signal, this ringing also occurs in a differential mode, and therefore cannot be removed. In particular, as the operation speed increases, this problem becomes greater, and the degree of waveform deterioration also increases. This waveform deterioration can be suppressed by inserting a resistor into the input and output of the emitter follower, but the band characteristic is deteriorated.

For example, when a capacitive load C7_1 is connected to an emitter follower constituting an output circuit as shown in FIG. 7, a transfer function F (s) is represented by the following equation (1).

[0004]

(Equation 1)

However, τ_π = C_π × R_π, τ_L = C
7_1 × R7_2, and C_π, R_π, and β0 are a base-emitter capacitance, a small signal input resistance, and a small signal input gain, respectively. If the poles in this equation have complex poles, the response will be oscillating, causing the ringing described above. It has a complex pole when the denominator discriminant is negative, which is clearly τ_L ≒
τ_π. Τ_L = τ_ to simplify explanation
Consider the case where π = τ. At this time, the denominator of Equation 1 is given by Equation (2)
Put like.

[0006]

(Equation 2)

Here, ω is called a resonance frequency, ζ is called a braking constant, and ζ is expressed as in equation (3).

[0008]

(Equation 3)

When ζ is 0 <ζ <1, the response is oscillatory, and the closer the 減 衰 is to 0, the slower the attenuation of the vibration. Making ζ larger than this is an important point in suppressing ringing. Conventionally, attempts have been made to suppress ringing by inserting a resistor in the base of the transistor and forming a low-pass filter with the parasitic capacitance of the transistor. This also means that the signal source output impedance R7_1 is not a pure resistance but an inductive one. It is also effective in suppressing continuous vibrations that occur during sex. However, this method leads to band degradation, which is not always desirable from the viewpoint of operation speed, and is not effective in some cases. To reduce ζ, R
7_2 may be reduced, but in this method, R7_2 must be extremely small, and the bias current increases, so that the number of transistors must be increased accordingly.

On the other hand, as a technique for solving such a problem,
In the pulse circuit described in Japanese Patent Application Laid-Open No. 60-41815, it has been proposed to connect a resistor between the output terminals of a pair of emitter followers. According to this, without changing the bias point and the bias current, it is possible to equivalently increase the braking constant に し て, equivalently to connecting a resistor between the output terminal and the AC ground, Thereby, ringing can be suppressed.

[0011]

However, in the pulse circuit, when the resistance value between the output terminals of the emitter follower is small, a large transient current flows. Therefore, in some cases, the emitter follower may fail. However, there is a problem that the collector current flowing through the device becomes excessively large and exceeds an appropriate operation range. Further, when the scale of the circuit connected to the next stage of the output circuit is large, the resistance value tends to decrease, and the bias point tends to fluctuate.

The present invention has been made to solve the above-mentioned problem, and it is an object of the present invention to provide an output circuit comprising a pair of output circuit terminals for outputting a differential signal, such as an emitter follower, connected to a resistor, while suppressing ringing. It is another object of the present invention to provide an output circuit capable of suppressing a fluctuation of a bias point due to an influence of a load and adjusting a transient fluctuation due to a resistance of a collector current of a transistor constituting an emitter follower.

[0013]

To achieve the above object,
An output circuit according to a first aspect of the present invention is a monolithic integrated circuit, comprising:
A first resistor and a second resistor having the same resistance value are connected in series, and a connection point of the first resistor and the second resistor is connected to a bias circuit for applying a center bias voltage of a modulation voltage. Thus, the bias voltage of the output voltage can be stabilized while suppressing the ringing, and the output waveform can be shaped.

According to a second aspect of the present invention, an output circuit is configured as a differential amplifier that receives a pair of differential signals from the outside and outputs a pair of differential voltages between two output terminals. is there. As a result, the circuit configuration of the output circuit can be unitized and downsized, and handling can be facilitated.

According to a third aspect of the present invention, in the monolithic integrated circuit, the output circuit receives a pair of differential signals and a center bias signal output from two sets of differential amplifiers and receives a pair of differential voltages and a center bias signal. A first resistor and a second resistor having the same resistance value are connected in series between output terminals that output a bias voltage and output the pair of differential voltages, and a center point of the modulation voltage is connected to a connection point between these resistors. The bias voltage is applied. As a result, the bias of the modulation signal is applied to the connection point of the two resistors, and the effect of suppressing waveform deterioration is enhanced by stabilizing the bias point.

The output circuit according to a fourth aspect of the present invention is the output circuit, wherein one of the two sets of differential amplifiers comprises:
Each collector is connected to a power supply via a resistor, and each emitter is composed of a first transistor and a second transistor that are grounded via a common first current source. The collector is connected to a power supply via a resistor, and each emitter comprises a third transistor and a fourth transistor grounded via a common second current source. Each base is connected, one differential signal is input, the respective bases of the second transistor and the fourth transistor are connected, the other differential signal is input, and the second transistor and the third transistor are input. Each collector is connected, the collector potential of the first transistor is output as a positive-phase output signal, and the collector potential of the second transistor or the third transistor is output as a central bias. Signals, each collector potential of the fourth transistor as a negative-phase output signal, is obtained so as to output the pair of differential voltages and the center bias voltage on the basis of these. Thus, the bias of the modulation signal can be applied to the connection point of the resistor by using a simple transistor circuit, and the bias point can be stabilized.

According to a fifth aspect of the present invention, in the monolithic integrated circuit, a modulation current source is connected as a load to two emitter followers, and an output terminal of a differential voltage output from each emitter follower. A resistor is connected in between, and the modulation current source is modulated in synchronization with a change in the current flowing through the resistor. Thereby, even if the current flowing through the resistor changes,
The change can be adjusted to an optimum value.

Further, in the output circuit according to the present invention, a load of the emitter follower is a constant current source composed of a transistor, and the current value of the constant current source on the positive-phase signal side output from each emitter follower is provided. The modulation is performed by the negative-phase signal, and the current value of the constant current source on the negative-phase signal side is modulated by the positive-phase signal. Thus, the amount of change in the current flowing through the transistor can be adjusted to an optimum value.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an output circuit in which a bias point is stabilized. The output circuit 1_1 having a differential output has the following stage.
The input circuit 1_2 is connected, and two resistors R1_1 and R1_2 having the same size are connected in series between each one node on a line connecting the output circuit 1_1 and the input circuit 1_2. A bias circuit 1_3 that outputs a bias voltage is connected to a node connecting the resistors R1_1 and R1_2. This stabilizes the output bias point and has the effect of suppressing waveform deterioration.

FIG. 2 shows an embodiment of an output circuit including a bias circuit. The amplifier circuit installed before the output circuit is a combination of two differential amplifiers, and the differential inputs IN_P, I_P
For N_N, three output signals of normal phase, reverse phase, and center bias are output. This amplifier circuit has a transistor Q2_
1, Q2_2 to form a differential pair, a differential amplifier A having a first current source I2_1 at the emitter thereof, and a differential pair comprising transistors Q2_3, Q2_4, and a second current source I2_2 to the emitter thereof. And a base of Q2_1 and Q2_3, and Q2_2 and Q2
2_4 bases are connected respectively, and Q2_2 and Q2_3
The collector is connected. The input terminal is Q2_1
The base and output terminals of (or Q2_3) and Q2_2 (or Q2_4) are the three terminals of the collector of Q2_1, the collector of Q2_2 (or Q2_3), and the collector of Q2_4. The node P2 and the node N2 become the positive and negative phases of the differential signal, and the node I2 becomes the center bias. An emitter follower composed of transistors Q2_5 (or Q2_6, Q2_7) is connected as an output circuit to the next stage of the amplifier circuit, and a resistor R2_8,
R2_9 are connected in series. Thereby, the node I2
Is always biased at the center between the node P2 and the node N2, and the bias point is stabilized. In addition, 2_
1 is an input circuit. FIGS. 3 and 4 show a pair of complementary output circuits when a capacitive load is connected to the output circuit pair constituted by the conventional emitter follower and the output circuit according to the present invention.
The differential voltage waveform of the output positive phase signal and the negative phase signal with respect to the voltage input at 2.5 Gbps is shown. Here, the horizontal axis represents time, and the vertical axis represents the difference voltage. While ringing is visible in the conventional waveform, ringing is suppressed in the present invention.

FIG. 5 shows another embodiment of the present invention. This is a diagram of an output circuit having a current value adjusting function. The loads of the emitter followers of the output circuit composed of the transistors Q5_1 and Q5_2 are respectively changed to modulation current sources I5_1 and I5_.
2, a resistor R5_1 is connected between the output terminals of the emitter followers. 5_1 is an input circuit. This resistor R5_
1 is connected, the voltage difference between the positive and negative phases is
A current Iterm having a current value divided by the resistance value of 5_1 flows through the resistor R5_1, and the direction of this current Term changes in synchronization with signal modulation. Then, this current Term
Will flow through the emitter follower transistors Q5_1 and Q5_2, and the current flowing through the transistors Q5_1 and Q5_2 will deviate from the bias current determined by the modulation current sources I5_1 and I5_2 by that amount.
This current Iterm may be large enough to greatly affect the characteristics. However, by modulating the modulation current sources I5_1 and I5_2 in synchronization with the change of the current Iter, the waveform deterioration of the output circuit can be prevented without deteriorating the characteristics. It becomes possible to suppress.

FIG. 6 shows a specific example of an output circuit having a modulation current source. The modulation current source in FIG. 5 includes two transistors Q6_5 and Q6_6.
Transistor Q6_2 and resistors R6_6, R6
The modulation voltage generated from the emitter follower constituted by the transistor Q6_3 is input, and the value of the current flowing through the transistor Q6_6 is modulated in the opposite phase to the modulation voltage input to the emitter follower constituted by the transistor Q6_4. The transistor Q6_3 and the resistor R
The modulation voltage generated from the emitter follower composed of the transistors 6_5 and R6_2 is input, and the current flowing through the transistor Q6_5 is modulated in the opposite phase to the modulation voltage input to the emitter follower composed of the transistor Q6_1, so that the waveform is deteriorated. Has been prevented. 6_1 is an input circuit. Further, the resistors R6_1, R6_2, R6_3, R6_4,
By adjusting the values of R6_5 and R6_6, the modulation current value can be adjusted to an optimum value.

[0023]

As described above, according to the present invention, in a monolithic integrated circuit, a first resistor and a second resistor having the same resistance are connected in series between a pair of differential voltage output terminals. By connecting a bias circuit for applying a center bias voltage of the modulation voltage to a connection point between the first resistor and the second resistor, the ringing is suppressed while a bias point due to the influence of a load connected to the output circuit is suppressed. Can be suppressed and can be stabilized. Also, a modulation current source is connected to these two emitter followers as these loads, and a resistor is connected between the output terminals of the differential voltage output by each emitter follower, in synchronization with the change in the current flowing through these resistors. By modulating the modulation current source, it is possible to obtain an effect that the modulation current can be adjusted to an optimum value according to a change in the current flowing through the resistor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an output circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an output circuit according to another embodiment of the present invention.

FIG. 3 is a waveform diagram showing a state in which ringing is included in an output waveform in a conventional output circuit.

FIG. 4 is a waveform diagram showing an output waveform in which ringing is suppressed by the output circuit of the present invention.

FIG. 5 is a circuit diagram showing an output circuit according to another embodiment of the present invention.

FIG. 6 is a circuit diagram showing an output circuit according to another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional output circuit.

[Explanation of symbols]

 R1_1 First resistor R1_2 Second resistor R2_1, R2_2, R2_3, R2_4, R5_1 Resistor 1-1 Output circuit A, B Differential amplifier I2-1 First current source I2_2 Second current source I5_1, I5_2 Modulated current source 1_3 Bias circuit Q2_1 First transistor Q2_2 Second transistor Q2_3 Third transistor Q2_4 Fourth transistor Q6_5, Q6_6 Transistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J056 AA04 BB24 CC01 CC23 DD02 DD23 FF09 KK01 5J066 AA01 AA12 CA23 CA81 FA09 FA15 HA02 HA25 KA05 KA12 MA01 MA21 ND01 ND22 ND23 PD02 TA01 TA06 5J100 AA01 BA05 BB01 BB07 BB07

Claims (6)

[Claims] In a monolithic integrated circuit, a first resistor and a second resistor having the same resistance are connected in series between an output terminal for outputting a pair of differential voltages, and the first resistor and the second resistor are connected in series. A bias circuit for applying a center bias voltage of the modulation voltage to a connection point of the resistors. 2. The output circuit according to claim 1, wherein the differential circuit is configured to receive a pair of differential signals from outside and output a pair of differential voltages between two output terminals. . 3. A monolithic integrated circuit, comprising: receiving a pair of differential signals and a center bias signal output by two sets of differential amplifiers, and outputting a pair of differential voltages and a center bias voltage; A first resistor and a second resistor having the same resistance value are connected in series between output terminals for outputting a voltage, and a center bias voltage of the modulation voltage is applied to a connection point between the first resistor and the second resistor. An output circuit characterized in that: 4. A set of differential amplifiers of the two sets of differential amplifiers, wherein each collector is connected to a power supply via a resistor,
Each pair of differential amplifiers includes a first transistor and a second transistor, each emitter connected to ground via a common first current source, and another set of differential amplifiers wherein each collector is connected to a power supply via a resistor and each emitter Comprises a third transistor and a fourth transistor that are grounded via a common second current source, and each base of the first transistor and the third transistor is connected and one differential signal is input. And the respective bases of the second transistor and the fourth transistor are connected and the other differential signal is input, the respective collectors of the second transistor and the third transistor are connected, and the first transistor The collector potential is the positive-phase output signal, the collector potential of the second transistor or the third transistor is the center bias output signal, the fourth transistor is the The output circuit according to claim 3, the collector potential as a negative-phase output signal, and outputs the pair of differential voltages and the center bias voltage on the basis of these. 5. In a monolithic integrated circuit, a modulation current source is connected as a load to two emitter followers, and a resistor is connected between output terminals of a differential voltage output from each emitter follower. An output circuit, wherein the modulation current source is modulated in synchronization with a change in flowing current. 6. A load of the emitter follower is a constant current source composed of a transistor, and the current value of the constant current source on the positive-phase signal side output by each emitter follower is modulated by a negative-phase signal. 6. The output circuit according to claim 5, wherein a current value of a constant current source on a phase signal side is modulated by a positive phase signal.