JPS6012381Y2 - Image quality adjustment circuit - Google Patents

Image quality adjustment circuit

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Publication number
JPS6012381Y2
JPS6012381Y2 JP12935075U JP12935075U JPS6012381Y2 JP S6012381 Y2 JPS6012381 Y2 JP S6012381Y2 JP 12935075 U JP12935075 U JP 12935075U JP 12935075 U JP12935075 U JP 12935075U JP S6012381 Y2 JPS6012381 Y2 JP S6012381Y2
Authority
JP
Japan
Prior art keywords
image quality
resistor
quality adjustment
signal
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12935075U
Other languages
Japanese (ja)
Other versions
JPS5243822U (en
Inventor
照男 川畑
Original Assignee
株式会社富士通ゼネラル
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社富士通ゼネラル filed Critical 株式会社富士通ゼネラル
Priority to JP12935075U priority Critical patent/JPS6012381Y2/en
Publication of JPS5243822U publication Critical patent/JPS5243822U/ja
Application granted granted Critical
Publication of JPS6012381Y2 publication Critical patent/JPS6012381Y2/en
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は例えばテレビジョン受像機等に於けるアパーチ
ャ補償回路を簡略且つ安価に提供する画質調整回路の改
良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of an image quality adjustment circuit that provides a simple and inexpensive aperture compensation circuit for use in, for example, television receivers.

先ず、従来の画質調整回路を第1図及び第3図によって
説明すると、1は増幅用トランジスタ、2は信号源イン
ピーダンス、3はエミッタ抵抗、4.5はコンデンサ、
6は高周波変圧器、7はダンピング抵抗、8は信号加算
用可変抵抗器、9は信号源、10.10’は信号出力端
、11は直流電源端子である。
First, a conventional image quality adjustment circuit will be explained with reference to FIGS. 1 and 3. 1 is an amplification transistor, 2 is a signal source impedance, 3 is an emitter resistor, 4.5 is a capacitor,
6 is a high frequency transformer, 7 is a damping resistor, 8 is a variable resistor for signal addition, 9 is a signal source, 10.10' is a signal output terminal, and 11 is a DC power supply terminal.

斯かる回路に於いて、入力信号9として第3図aに示す
ようなパルス波形が増幅用トランジスタ1のベースに印
加されると、トランジスタ1のエミッタには抵抗3とコ
ンデンサ4の並列回路が接続されているが、出力インピ
ーダンスが低いことにより、エミッタ側の出力はベース
入力信号と略等しい波形が得られる。
In such a circuit, when a pulse waveform as shown in FIG. 3a is applied as an input signal 9 to the base of the amplifying transistor 1, a parallel circuit of a resistor 3 and a capacitor 4 is connected to the emitter of the transistor 1. However, due to the low output impedance, the output on the emitter side has a waveform approximately equal to that of the base input signal.

このエミッタ出力が信号加算用可変抵抗器8の中点に印
加される。
This emitter output is applied to the midpoint of the signal addition variable resistor 8.

一方、増幅用トランジスタ1のコレクタ[圧ハ抵抗3と
コンデンサ4の作用により一次微分され、第3図すのよ
うになる。
On the other hand, the collector of the amplifying transistor 1 is first differentiated by the action of the piezoelectric resistor 3 and the capacitor 4, as shown in FIG.

更にこの電圧は高周波変圧器6の一次側コイルによって
再度微分され、同図Cに示すような波形になる。
Furthermore, this voltage is differentiated again by the primary coil of the high frequency transformer 6, resulting in a waveform as shown in FIG.

然るのち、二度微分された波形は高周波変圧器6の二次
側に誘起され、信号加算用可変抵抗器8の一方に加えら
れる。
Thereafter, the twice differentiated waveform is induced on the secondary side of the high frequency transformer 6 and applied to one side of the signal summing variable resistor 8.

こうしてエミッタ側からの信号と、コレクタ側からの信
号は信号加算用可変抵抗器8によって加算され、同図d
に示すようになるが、プリシュート及びオーバーシュー
トは信号加算用可変抵抗器8の可動によって調整される
In this way, the signal from the emitter side and the signal from the collector side are added by the signal addition variable resistor 8.
As shown in FIG. 2, the preshoot and overshoot are adjusted by moving the variable resistor 8 for signal addition.

しかしこのような従来方式は、高周波変圧器を使用して
いるための共振周波数の調整を必要とし、又該高周波変
圧器及び中点付可変抵抗器等も使用しているためコスト
的にも不利な点が多かった。
However, this conventional method requires adjustment of the resonant frequency because it uses a high-frequency transformer, and is also disadvantageous in terms of cost because it also uses the high-frequency transformer and a variable resistor with a center point. There were many points.

本考案は、上記従来方式の欠点を簡単な回路構成を以て
解消し、生産コストを大巾に低減し得る画質調整回路を
提供せんとするのみならず更に微分作用と積分作用との
いずれかに基づく補正を、微分用インダクタンスと並列
にせる1個の可変抵抗器により調整できるような回路構
成となるため、その調整の範囲を大巾に拡大できる回路
が得られる。
The present invention aims not only to eliminate the drawbacks of the above-mentioned conventional method with a simple circuit configuration and to provide an image quality adjustment circuit that can significantly reduce production costs, but also to provide an image quality adjustment circuit that is based on either differential action or integral action. Since the circuit configuration is such that the correction can be adjusted by one variable resistor placed in parallel with the differential inductance, a circuit that can greatly expand the range of adjustment can be obtained.

以下、第2図及び第3図に基づき本考案を説明するが、
第2図に於いて第1図との対応部分には同一符号を付し
てその説明を省略する。
The present invention will be explained below based on FIGS. 2 and 3.
In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals, and their explanations will be omitted.

先ず、増幅用トランジスタ1のコレクタと直流電源端子
11との間には微分用インダクタンス12と中点性でな
い通常の可変抵抗器からなる画質調整用可変抵抗器13
の並列回路を挿入し、コレクタ・エミッタ間にはコンデ
ンサ14及び結合抵抗15の直列回路を接続し、該直列
回路が微分回路を構成する如く、コンデンサ14と結合
抵抗15の接続点からは信号出力端10.10’を取り
出す。
First, between the collector of the amplification transistor 1 and the DC power supply terminal 11, there is a differential inductance 12 and an image quality adjustment variable resistor 13 consisting of a normal variable resistor that is not a midpoint type.
A parallel circuit is inserted between the collector and the emitter, and a series circuit of a capacitor 14 and a coupling resistor 15 is connected between the collector and the emitter, and a signal is output from the connection point of the capacitor 14 and the coupling resistor 15 so that the series circuit constitutes a differential circuit. Take out the end 10.10'.

斯かる構成に於いて次にその動作を説明すると、9の入
力信号として第3図aに示すようなパルス波形がトラン
ジスタ1のベースに印加され、該トランジスタ1のエミ
ッタ側には前記ベース入力信号と略等しい波形が得られ
、その出力信号は結合抵抗15を介して信号出力端10
.10’に導出される。
Next, the operation of such a configuration will be explained.A pulse waveform as shown in FIG. A substantially equal waveform is obtained, and the output signal is sent to the signal output terminal 10 via the coupling resistor 15.
.. 10'.

一方、トランジスタ1のコレクタ負荷とインダクタンス
12及び画質調整用可変抵抗器13は、定電流源で駆動
された形となり、コレクタ側の出力はインダクタンス1
2により一次微分され、コレクタ電圧は第3図すに示す
ような波形となる。
On the other hand, the collector load of the transistor 1, the inductance 12, and the variable resistor 13 for adjusting image quality are driven by a constant current source, and the output on the collector side is the inductance 12.
2, and the collector voltage has a waveform as shown in FIG.

更に該−次微分電圧はコンデンサ14、抵抗15の直列
回路からなる微分回路で再び微分されて、出力端子10
.10’には同図Cの信号波形が得られる。
Furthermore, the negative differential voltage is differentiated again by a differentiating circuit consisting of a series circuit of a capacitor 14 and a resistor 15, and then outputted to an output terminal 10.
.. 10', the signal waveform shown in C of the figure is obtained.

こうして、エミッタ側からの信号とコレクタ側からの信
号か出力端10,10’で加算され同図dのような波形
が得られる。
In this way, the signal from the emitter side and the signal from the collector side are added at the output terminals 10, 10' to obtain a waveform as shown in the figure d.

なお、上記加算において、前記両信号の時間的な差を厳
密に合わせる必要があるならば、設計時に例えばエミッ
タ側からの信号導出回路中に信号遅延用としてインダク
ターを挿入する様考慮すると良い。
In addition, in the above addition, if it is necessary to strictly match the time difference between the two signals, consideration should be given to inserting an inductor for signal delay into the signal derivation circuit from the emitter side, for example, at the time of design.

一方画質調整用可変抵抗器13がO〔Ω〕の時はコレク
タ側には何ら信号電圧は発生せず、−次二次微分回路共
に動作せず、エミッタ側出力波形は結合抵抗15、コン
デンサ14の低域フィルタ回路で積分された波形となり
、出力端10.10’には同図eに示すような信号波形
が得られる。
On the other hand, when the variable resistor 13 for adjusting image quality is set to O [Ω], no signal voltage is generated on the collector side, the -order second-order differential circuit does not operate, and the output waveform on the emitter side is the coupling resistor 15 and capacitor 14. The signal waveform is integrated by the low-pass filter circuit, and a signal waveform as shown in the figure e is obtained at the output terminal 10.10'.

叙上の如く、本考案によれば、微分作用に基づくプリシ
ュート、オーバーシュートによるハード(輪郭強調)の
画面から積分作用に基づくソフト(輪郭ぼかし)の画面
に至る迄の広範囲に亘る視聴者の好みに応じた画質を容
易に得ることができ、微分インダクタンスと並列の1個
の可変抵抗器と微分または積分共用のコンデンサ及び抵
抗とにより上記広範囲の調整が可となることと相俟って
、その回路構成も非常に簡略化できる等の実用上の効果
を発揮するものである。
As mentioned above, according to the present invention, a wide range of viewers can enjoy the screen, from hard (contour enhancement) screens based on preshoot and overshoot based on differential action to soft (contour blurring) screens based on integral action. It is possible to easily obtain the image quality according to one's preference, and together with the fact that the above-mentioned wide range of adjustment is possible by using one variable resistor in parallel with the differential inductance, and the capacitor and resistor for both differentiation and integration, The circuit configuration can also be greatly simplified, which provides practical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示す回路図、第2図は本考案による一
実施例を示す回路図、第3図は第1図及び第2図の説明
に供する波形図である。 図中、1は増幅用トランジスタ、2は信号源インピーダ
ンス、3はエミッタ抵抗、9は信号源、10.10’は
信号出力端、11は直流電源端子、12は微分用インダ
クタンス、13は画質調整用可変抵抗器、14は微分ま
たは積分用コンデンサ、15は微分または積分用及び結
合抵抗である。
FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining FIGS. 1 and 2. In the figure, 1 is an amplification transistor, 2 is a signal source impedance, 3 is an emitter resistance, 9 is a signal source, 10.10' is a signal output terminal, 11 is a DC power supply terminal, 12 is a differential inductance, and 13 is an image quality adjustment 14 is a differential or integral capacitor, 15 is a differential or integral resistor and a coupling resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号をベースに印加し且つ抵抗を介してエミッタを
接地してなる増幅用トランジスタからなる画質調整回路
に於いて、該増幅用トランジスタのコレクタを直流電源
端子間には微分用インダクタンスと画質調整用可変抵抗
器からなる並列回路を挿入すると共に、該コレクタとエ
ミッタ間にはコレクタに一端を結合せるコンデンサと抵
抗とからなる直列回路を挿入し、更い該コンデンサの他
端と抵抗との結合点から出力端を導出した画質調整回路
In an image quality adjustment circuit consisting of an amplification transistor to which an input signal is applied to the base and whose emitter is grounded via a resistor, a differential inductance and an image quality adjustment inductance are connected between the collector of the amplification transistor and the DC power terminal. In addition to inserting a parallel circuit consisting of a variable resistor, a series circuit consisting of a capacitor and a resistor whose one end is connected to the collector is inserted between the collector and the emitter, and a connecting point between the other end of the capacitor and the resistor is inserted. Image quality adjustment circuit whose output end is derived from.
JP12935075U 1975-09-20 1975-09-20 Image quality adjustment circuit Expired JPS6012381Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12935075U JPS6012381Y2 (en) 1975-09-20 1975-09-20 Image quality adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12935075U JPS6012381Y2 (en) 1975-09-20 1975-09-20 Image quality adjustment circuit

Publications (2)

Publication Number Publication Date
JPS5243822U JPS5243822U (en) 1977-03-28
JPS6012381Y2 true JPS6012381Y2 (en) 1985-04-22

Family

ID=28609661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12935075U Expired JPS6012381Y2 (en) 1975-09-20 1975-09-20 Image quality adjustment circuit

Country Status (1)

Country Link
JP (1) JPS6012381Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500018A (en) * 1981-01-02 1983-01-06 キング,ウイリアム Device

Also Published As

Publication number Publication date
JPS5243822U (en) 1977-03-28

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