JPH08153780A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPH08153780A
JPH08153780A JP7124399A JP12439995A JPH08153780A JP H08153780 A JPH08153780 A JP H08153780A JP 7124399 A JP7124399 A JP 7124399A JP 12439995 A JP12439995 A JP 12439995A JP H08153780 A JPH08153780 A JP H08153780A
Authority
JP
Japan
Prior art keywords
substrate
film
polishing
oxide film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7124399A
Other languages
Japanese (ja)
Inventor
Shinsuke Sakai
慎介 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP7124399A priority Critical patent/JPH08153780A/en
Publication of JPH08153780A publication Critical patent/JPH08153780A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a semiconductor substrate which has no polysilicon film, but a laminated SOI structure, and to simplify the manufacturing process of the substrate. CONSTITUTION: After a silicon oxide film 13 with steps is formed on at least one surface of an active-layer substrate A, the film 13 is polished on a rigid turntable by using an abrasive composed mainly of colloidal silica. Then a silicon wafer having an SOI structure is obtained by putting and sticking the mirror surface of a supporting substrate B on and to the polished joint surface 13a of the substrate 13. Therefore, the conventional polysilicon film which has been formed on the surface of the oxide silicon film for joint is not required. The polishing of the joint surface is performed in such a way that, after the surface of the silicon dioxide film 13 is flattened by using an abrasive composed of true-spherical colloidal silica which is manufactured by a wet colloidal method and has an average particle diameter of 70nm, steps having large level differences are removed by raising the polishing rate, and then, the film 13 is polished with colloidal silica having an average particle size of 30nm.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体基板に関し、特
に薄膜SOI構造の半導体基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate, and more particularly to a semiconductor substrate having a thin film SOI structure.

【0002】[0002]

【従来の技術】SOI(Silicon・on・Ins
ulator)構造の半導体基板においては、素子を形
成する活性層を薄くすればするほど、pn接合の寄生容
量を減少させ、素子の動作速度を高めることができる。
このため、活性層の超薄膜化が検討されている。
2. Description of the Related Art SOI (Silicon on Ins)
In a semiconductor substrate having an ululator structure, the thinner the active layer forming the element, the more the parasitic capacitance of the pn junction can be reduced and the operating speed of the element can be increased.
For this reason, ultra-thin active layers are being studied.

【0003】ところで、薄膜SOI構造の半導体基板を
得るための手法として、張り合わせ法が知られている。
図3は従来の張り合わせ法によるSOI構造の半導体基
板の製造方法を示す断面図である。
By the way, a bonding method is known as a method for obtaining a semiconductor substrate having a thin film SOI structure.
FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor substrate having an SOI structure by a conventional bonding method.

【0004】この製造方法では、まず、パターニングさ
れたシリコン基板1(活性層基板)の表面に、SiO2
膜3を形成し(図3(a)参照)、この酸化膜3上にポ
リシリコン層4を形成する(図3(b))。次に、この
ポリシリコン層4の表面をメカノケミカル研磨して平坦
化した後(図3(c))、この研磨面4aに別のシリコ
ン基板5(支持体基板)を張り合わせる(図3
(d))。最後に、活性層基板1の表面(張り合わせ面
と反対側の面)を、酸化膜3が露出するまで研磨する
(図3(e))。
In this manufacturing method, first, SiO 2 is formed on the surface of the patterned silicon substrate 1 (active layer substrate).
A film 3 is formed (see FIG. 3A), and a polysilicon layer 4 is formed on the oxide film 3 (FIG. 3B). Next, after the surface of the polysilicon layer 4 is planarized by mechanochemical polishing (FIG. 3C), another silicon substrate 5 (support substrate) is attached to the polishing surface 4a (FIG. 3C).
(D)). Finally, the surface of the active layer substrate 1 (the surface opposite to the bonding surface) is polished until the oxide film 3 is exposed (FIG. 3E).

【0005】すなわち、このようにして作製した従来の
SOI構造の半導体基板は、支持体基板5の上にポリシ
リコン層4を有し、このポリシリコン層4の上に酸化膜
3が形成されていた。酸化膜3の上には単結晶シリコン
層1が積層され、この単結晶シリコン層1はパターニン
グされた酸化膜3によって絶縁分離されていた。
That is, the conventional SOI structure semiconductor substrate thus manufactured has the polysilicon layer 4 on the support substrate 5, and the oxide film 3 is formed on the polysilicon layer 4. It was The single crystal silicon layer 1 was laminated on the oxide film 3, and the single crystal silicon layer 1 was insulated and separated by the patterned oxide film 3.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のSOI構造の半導体基板にあっては、製造上
の必要からポリシリコン層4を有していた。ポリシリコ
ン層を研磨して平坦化し、張り合わせるものだからであ
る。よって、SOI構造の半導体基板としては無用なポ
リシリコン層を形成するために無駄な工程が必要となる
という課題があった。
However, in such a conventional semiconductor substrate having an SOI structure, the polysilicon layer 4 is provided due to the necessity of manufacturing. This is because the polysilicon layer is polished and flattened and then laminated. Therefore, there is a problem that a wasteful process is required to form a polysilicon layer that is unnecessary for a semiconductor substrate having an SOI structure.

【0007】そこで、発明者は、シリコン基板の表面に
形成した酸化シリコン膜を直接研磨して満足する平坦度
が得られれば、ポリシリコン層の形成工程を省略するこ
とができる点に着目し、酸化シリコン膜を研磨する手法
を鋭意研究・検討した結果、研磨剤と研磨法を適切に構
成すれば、張り合わせに要求される平坦度を満足し得る
研磨面を得ることができることを確認し、この発明を完
成するに至った。
Therefore, the inventor has noticed that the step of forming the polysilicon layer can be omitted if the silicon oxide film formed on the surface of the silicon substrate is directly polished to obtain a satisfactory flatness. As a result of diligent research and examination of a method for polishing a silicon oxide film, it was confirmed that a polishing surface capable of satisfying the flatness required for bonding can be obtained by appropriately configuring an abrasive and a polishing method. The invention was completed.

【0008】この発明は、例えば酸化膜を直接研磨して
張り合わせることにより、ポリシリコン膜被着工程を省
略し、簡単に製造することができるSOI構造の半導体
基板を提供することを目的としている。
An object of the present invention is to provide an SOI structure semiconductor substrate which can be easily manufactured by omitting the step of depositing a polysilicon film by directly laminating and bonding an oxide film. .

【0009】[0009]

【課題を解決するための手段】請求項1に記載の発明
は、単結晶シリコンで構成された支持基板部と、酸化膜
で構成され、この支持基板部の表面を覆う絶縁層と、こ
の絶縁層の表面を覆う単結晶シリコン層と、を含む半導
体基板であって、この単結晶シリコン層表面に上記酸化
膜の一部を露出させた半導体基板である。
According to a first aspect of the present invention, there is provided a support substrate portion made of single crystal silicon, an insulating layer made of an oxide film and covering the surface of the support substrate portion, and the insulating layer. A single crystal silicon layer covering the surface of the layer, and a semiconductor substrate in which a part of the oxide film is exposed on the surface of the single crystal silicon layer.

【0010】[0010]

【作用】この請求項1の発明によれば、絶縁層を構成す
る酸化膜の一部を露出させて単結晶シリコン層同士を絶
縁したため、各単結晶シリコン層にデバイスをそれぞれ
形成することができる。また、SOI構造の半導体基板
として無用なポリシリコン層を廃止することができ、そ
の製造を簡単に行える。
According to the invention of claim 1, since a part of the oxide film forming the insulating layer is exposed to insulate the single crystal silicon layers from each other, a device can be formed in each single crystal silicon layer. . Further, the unnecessary polysilicon layer as the semiconductor substrate having the SOI structure can be eliminated, and the manufacturing thereof can be easily performed.

【0011】[0011]

【実施例】この発明の一実施例に係る半導体基板につい
て、図面に基づいて具体的に説明する。図1(a)〜図
1(d)は、一実施例に係るSOI構造のシリコンウェ
ーハの製造工程を示す断面図である。図1(d)に示す
ように、SOI構造のシリコンウェーハは、単結晶シリ
コン基板部15の上に酸化絶縁膜13を積層し、この酸
化膜13上には薄い単結晶シリコン層11が酸化膜13
に絶縁分離されて島状に形成されている。すなわち、活
性層11が島状の酸化膜13で分離された状態の薄膜S
OI構造のシリコンウェーハである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor substrate according to an embodiment of the present invention will be specifically described with reference to the drawings. 1A to 1D are cross-sectional views showing a manufacturing process of a silicon wafer having an SOI structure according to an embodiment. As shown in FIG. 1D, in the silicon wafer having the SOI structure, the oxide insulating film 13 is laminated on the single crystal silicon substrate portion 15, and the thin single crystal silicon layer 11 has the oxide film 13 on the oxide film 13. Thirteen
Is insulated and separated into islands. That is, the thin film S in a state where the active layer 11 is separated by the island-shaped oxide film 13.
It is a silicon wafer having an OI structure.

【0012】この薄膜SOI構造のシリコンウェーハは
以下の工程を経て形成される。まず、図1(a)に示す
ように、単結晶シリコンからなる半導体基板11(活性
層基板A)を準備し、この基板11の片面に、フォトリ
ソグラフィ技術やエッチング技術を用いて、例えば深さ
が0.1μmの溝12を500μmの間隔で形成する。
この表面を熱酸化して、厚さ0.1μmのSiO2膜を
形成する。さらに、この熱酸化によるSiO2膜上に、
CVD法によって厚さ0.9μmのSiO2膜を形成す
る。この結果積層された1.0μmのSiO2膜13
が、活性層基板の表面絶縁層13を構成する。この酸化
膜13はパターニングされた活性層基板Aの表面形状に
したがって段差をもった表面として形成される。
The silicon wafer having the thin film SOI structure is formed through the following steps. First, as shown in FIG. 1A, a semiconductor substrate 11 (active layer substrate A) made of single crystal silicon is prepared, and one surface of the substrate 11 is formed to a depth, for example, by using a photolithography technique or an etching technique. The grooves 12 having a thickness of 0.1 μm are formed at intervals of 500 μm.
This surface is thermally oxidized to form a SiO 2 film having a thickness of 0.1 μm. Furthermore, on the SiO 2 film formed by this thermal oxidation,
A SiO 2 film having a thickness of 0.9 μm is formed by the CVD method. As a result, the laminated SiO 2 film 13 of 1.0 μm
Form the surface insulating layer 13 of the active layer substrate. The oxide film 13 is formed as a surface having a step according to the surface shape of the patterned active layer substrate A.

【0013】そして、この酸化膜13を直接研磨する。
酸化膜13の研磨にあたっては、例えば主成分にコロイ
ダルシリカを含む研磨剤が用いられる。この研磨剤に占
めるコロイダルシリカの固形分(NV)については、特
に限定されないが、1〜10%程度で使用することが好
ましい。また、研磨剤のpHについても特に限定されな
いが、pH=7前後の中性となるように調整すると、酸
化シリコン膜に対する研磨性能に有利である。この実施
例で使用した研磨剤は、SC112(キャボ社製)また
はILD1200(ロデール社製)の各研磨剤からヒュ
ームドシリカを除去し、この調整剤にコロイダルシリカ
を入れる。コロイダルシリカは湿式コロイダル法で作製
したものを使用する。この場合のコロイダルシリカは真
球であって、その径は10nm〜100nmである。研
磨は2段階研磨で行う。すなわち、まず平均粒径70n
mのコロイダルシリカの研磨剤を用い、二酸化シリコン
膜表面の平坦化研磨を行う。この第1段階研磨で研磨レ
ートを高めかつ大きな段差の除去を行うものである。そ
の後、平均粒径が30nmのコロイダルシリカの研磨剤
で研磨する。仕上げ研磨である。この結果、段差の大き
な二酸化シリコン膜を平坦に研磨することができる。ま
た、このようにして研磨したウェーハを支持体基板であ
る基盤ウェーハに張り合わせた場合、ボイドの発生は低
減された。
Then, the oxide film 13 is directly polished.
For polishing the oxide film 13, for example, an abrasive containing colloidal silica as a main component is used. The solid content (NV) of the colloidal silica in the abrasive is not particularly limited, but it is preferably used in the range of 1 to 10%. Further, the pH of the polishing agent is not particularly limited, but it is advantageous to the polishing performance for the silicon oxide film if it is adjusted to be neutral around pH = 7. The abrasive used in this example removes fumed silica from each of SC112 (manufactured by Cabo) or ILD1200 (manufactured by Rodel), and colloidal silica is added to the modifier. As the colloidal silica, one produced by a wet colloidal method is used. The colloidal silica in this case is a true sphere, and its diameter is 10 nm to 100 nm. Polishing is performed in two steps. That is, first, the average particle size is 70n.
The surface of the silicon dioxide film is flattened and polished by using an abrasive of m colloidal silica. This first-stage polishing increases the polishing rate and removes large steps. After that, polishing is performed with a colloidal silica abrasive having an average particle diameter of 30 nm. It is finish polishing. As a result, the silicon dioxide film having a large step can be polished flat. Further, when the wafer thus polished was bonded to a base wafer which is a support substrate, the occurrence of voids was reduced.

【0014】図1(b)に示す研磨工程では、上述した
研磨剤を用い、また、剛体定盤を用いて酸化膜13を研
磨する。剛体定盤は機械的、熱的変形の少ない平坦な、
例えばセラミックなどにより構成する。この剛体定盤の
研磨面の表面に、上述した酸化セリウムを主成分とする
研磨剤を混入したホットメルトワックスを薄く塗布して
もよい。
In the polishing step shown in FIG. 1B, the oxide film 13 is polished by using the above-mentioned polishing agent and a rigid surface plate. Rigid surface plate is flat with little mechanical and thermal deformation.
For example, it is made of ceramic or the like. The surface of the polishing surface of this rigid surface plate may be thinly coated with the hot melt wax mixed with the above-mentioned abrasive containing cerium oxide as a main component.

【0015】この実施例の研磨方法では、弾性変形しな
い剛体定盤を用いているため、図1(a)に示すような
段差を有する研磨面であれば、まず定盤に圧接された凸
部のみが徐々に研磨されてゆく。このようにして凸部と
凹部との段差が徐々に小さくなってゆき、結果的に平坦
な研磨面を得ることができる。
In the polishing method of this embodiment, since a rigid surface plate which is not elastically deformed is used, if the polishing surface has a step as shown in FIG. 1 (a), first the convex portion pressed against the surface plate is pressed. Only the pieces are gradually polished. In this way, the step between the convex portion and the concave portion is gradually reduced, and as a result, a flat polished surface can be obtained.

【0016】このような研磨剤と剛体定盤によって酸化
シリコン膜13を研磨した場合の結果を図2に示す。図
2(A)は研磨する前の酸化シリコン膜13の表面を表
面粗度計で測定して示すチャートであり、約0.1μm
の酸化シリコン膜13の段差が観察される。これに対し
て、図2(B)は、上記研磨剤と剛体定盤とを用いて、
研磨圧を200g/cm2、研磨剤とウェーハとの相対
速度を75rpm、研磨速度を70nm/minという
条件の下、図2(A)に示す酸化シリコン膜の研磨を行
った後の状態を表面粗度計で測定したチャートである。
この結果からも明かなように、酸化シリコン膜13の表
面粗度は、張り合わせを行うに必要な5nm以下の条件
を十分に満たしている。
FIG. 2 shows the result of polishing the silicon oxide film 13 with such an abrasive and a rigid surface plate. FIG. 2A is a chart showing the surface of the silicon oxide film 13 before polishing, which is measured by a surface roughness meter, and is about 0.1 μm.
The steps of the silicon oxide film 13 are observed. On the other hand, FIG. 2 (B) uses the abrasive and the rigid surface plate,
Under the conditions that the polishing pressure is 200 g / cm 2 , the relative speed between the polishing agent and the wafer is 75 rpm, and the polishing rate is 70 nm / min, the state after polishing the silicon oxide film shown in FIG. It is a chart measured by a roughness meter.
As is clear from this result, the surface roughness of the silicon oxide film 13 sufficiently satisfies the condition of 5 nm or less necessary for bonding.

【0017】以上の工程によって、SOI構造の半導体
基板を構成するための一方の半導体基板である活性層基
板Aを得る。
Through the above steps, the active layer substrate A, which is one of the semiconductor substrates for forming the semiconductor substrate having the SOI structure, is obtained.

【0018】図1(b)に示す鏡面状態の接合面13a
を得ると、次に、この接合面13aに支持基板Bとなる
他の半導体基板15の鏡面を密着させ、OH基の水素結
合により熱接合させて両者を張り合わせる(図1(c)
参照)。張り合わせ強度は、例えば200kg/cm2
以上、張り合わせ温度は1100℃とし、また、熱膨張
差によるSOI基板の反りを防止するために、支持基板
15として活性層基板11と同一のシリコン基板を用い
ることが好ましい。
The joining surface 13a in a mirror state shown in FIG. 1 (b).
Then, the mirror surface of the other semiconductor substrate 15 to be the supporting substrate B is brought into close contact with the bonding surface 13a, and the two are bonded by thermal bonding by hydrogen bond of the OH group (FIG. 1 (c)).
reference). The bonding strength is, for example, 200 kg / cm 2
As described above, it is preferable that the bonding temperature is 1100 ° C. and that the same silicon substrate as the active layer substrate 11 is used as the support substrate 15 in order to prevent the warp of the SOI substrate due to the difference in thermal expansion.

【0019】図1(c)に示すように活性層基板Aと支
持基板Bとを張り合わせたのちに、側周部分の面取りな
どを施すとともに、活性層基板11の厚さが約2μmと
なるように予め研削を施しておく。
As shown in FIG. 1C, after laminating the active layer substrate A and the supporting substrate B, chamfering of the side peripheral portion is performed and the thickness of the active layer substrate 11 becomes about 2 μm. Grind in advance.

【0020】最後に、図1(d)に示すように、活性層
基板Aの選択研磨を行う。この選択研磨は、例えば表面
粗さが0.01μmのセラミック製定盤を回転させ、こ
の定盤の表面に粒度が0.02μmの高純度シリカの微
粒子を5.0wt%分散させたpH=10.5のアルカ
リ溶液(研磨液)を滴下しつつ、この定盤表面に活性層
基板の単結晶基板部分11を100g/cm2の圧力で
圧着摩擦させることにより行う。
Finally, as shown in FIG. 1D, the active layer substrate A is selectively polished. In this selective polishing, for example, a ceramic surface plate having a surface roughness of 0.01 μm is rotated, 5.0 wt% of fine particles of high-purity silica having a particle size of 0.02 μm are dispersed on the surface of the surface plate, pH = 10. While dropping the alkaline solution (polishing solution) of 5, the single crystal substrate portion 11 of the active layer substrate is pressed and rubbed against the surface plate at a pressure of 100 g / cm 2 .

【0021】この選択研磨によって単結晶基板部分11
が徐々に研磨されてゆく。定盤がSiO2からなる酸化
膜13まで達すると、酸化膜13が選択研磨のストッパ
となって研磨速度が急速に低下する。この酸化膜13は
単結晶基板部分11に比べてメカノケミカル研磨され難
いからである。この研磨速度の変化を検出することによ
り、図1(d)に示すような酸化膜13が単結晶基板部
分11の表面から露出した状態、すなわち、活性層16
が島状の酸化膜13で分離された状態の薄膜SOI構造
のシリコンウェーハを得ることができる。
By this selective polishing, the single crystal substrate portion 11 is formed.
Is gradually polished. When the platen reaches the oxide film 13 made of SiO 2 , the oxide film 13 serves as a stopper for the selective polishing, and the polishing rate rapidly decreases. This is because the oxide film 13 is less likely to be mechanochemically polished than the single crystal substrate portion 11. By detecting the change in the polishing rate, the oxide film 13 as shown in FIG. 1D is exposed from the surface of the single crystal substrate portion 11, that is, the active layer 16 is exposed.
It is possible to obtain a silicon wafer having a thin film SOI structure in which the islands are separated by the island-shaped oxide film 13.

【0022】[0022]

【発明の効果】この発明によれば、従来の製造方法で必
要とされていた接合用のポリシリコン膜の形成工程が不
要となる。SOI構造の半導体基板を簡単に製造するこ
とができる。
According to the present invention, the step of forming the polysilicon film for bonding, which is required in the conventional manufacturing method, becomes unnecessary. A semiconductor substrate having an SOI structure can be easily manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例に係る半導体基板の各製造
工程を示す断面図である。
FIG. 1 is a cross-sectional view showing each manufacturing process of a semiconductor substrate according to an embodiment of the present invention.

【図2】この発明の一実施例に係る張り合わせ前の半導
体基板の酸化膜の研磨結果を説明するものであって、
(A)は研磨前、(B)は研磨後の各表面粗度を示す。
FIG. 2 is a view for explaining a result of polishing an oxide film on a semiconductor substrate before laminating according to an embodiment of the present invention,
(A) shows each surface roughness before polishing, and (B) shows each surface roughness after polishing.

【図3】従来の半導体基板の製造方法を示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a conventional method of manufacturing a semiconductor substrate.

【符号の説明】[Explanation of symbols]

A 活性層基板 B 支持基板 11 活性層基板側のシリコン基板 13 表面層(酸化膜) 13a 接合面 15 支持基板側のシリコン基板 16 活性層 A active layer substrate B support substrate 11 active layer substrate side silicon substrate 13 surface layer (oxide film) 13a bonding surface 15 support substrate side silicon substrate 16 active layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 単結晶シリコンで構成された支持基板部
と、 酸化膜で構成され、この支持基板部の表面を覆う絶縁層
と、 この絶縁層の表面を覆う単結晶シリコン層とを含む半導
体基板であって、 この単結晶シリコン層表面に上記酸化膜の一部を露出さ
せた半導体基板。
1. A semiconductor including a supporting substrate portion made of single crystal silicon, an insulating layer made of an oxide film and covering the surface of the supporting substrate portion, and a single crystal silicon layer covering the surface of the insulating layer. A semiconductor substrate in which a part of the oxide film is exposed on the surface of the single crystal silicon layer.
JP7124399A 1995-04-24 1995-04-24 Semiconductor substrate Pending JPH08153780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7124399A JPH08153780A (en) 1995-04-24 1995-04-24 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7124399A JPH08153780A (en) 1995-04-24 1995-04-24 Semiconductor substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP581893A Division JPH06216093A (en) 1993-01-18 1993-01-18 Polishing method for semiconductor substrate and manufacture of the substrate using same

Publications (1)

Publication Number Publication Date
JPH08153780A true JPH08153780A (en) 1996-06-11

Family

ID=14884484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7124399A Pending JPH08153780A (en) 1995-04-24 1995-04-24 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH08153780A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008516439A (en) * 2004-10-06 2008-05-15 コミツサリア タ レネルジー アトミーク Method for manufacturing a mixed laminate structure having various insulating regions and / or local vertical conductive regions
WO2009128494A1 (en) * 2008-04-16 2009-10-22 日立化成工業株式会社 Polishing solution for cmp and polishing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008516439A (en) * 2004-10-06 2008-05-15 コミツサリア タ レネルジー アトミーク Method for manufacturing a mixed laminate structure having various insulating regions and / or local vertical conductive regions
WO2009128494A1 (en) * 2008-04-16 2009-10-22 日立化成工業株式会社 Polishing solution for cmp and polishing method
JP2014057071A (en) * 2008-04-16 2014-03-27 Hitachi Chemical Co Ltd Polishing liquid for cmp and polishing method
JP5513372B2 (en) * 2008-04-16 2014-06-04 日立化成株式会社 Polishing liquid and polishing method for CMP

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