JPH08137793A - Recording and reproducing device and data transfer control method - Google Patents

Abstract

PURPOSE: To restrict time length while transfer is interrupted owing to WAIT signal. CONSTITUTION: An I/F circuit 104 reads data from a recorder 108 and receives the access of a host CPU 90 at every specified data quantity. A WAIT control circuit 101 indicates a wait to restrict the above access for a previously fixed time as against the host CPU 90 at every access. The occupation of a buss owing to the transfer of a DMA circuit 106 is released by the forcible wait at every access, the bus right of a internal CPU 103 is secured and the address of a transfer destination or a transfer source and the number of transfer data in the succeeding transfer of the DMA circuit 106 can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a case where data transfer is not in time for access from a host CPU of an external recording device that reads and writes data according to an access request from a host device (hereinafter referred to as a host CPU). ,access
The present invention relates to a data transfer control method and a transfer control device that limit a maximum WAIT time to a host CPU in a recording / reproducing device that delays access of a host device by a WAIT signal to control data transfer timing.

[0002]

2. Description of the Related Art A buffer RAM (Random Ac
cess Memory) is built in and used as a cache, and the contents recorded in the buffer RAM are discontinuous.
As a conventional technique for intermittently transferring data to the host CPU, there is an external recording device incorporating a disk cache control device as disclosed in Japanese Patent Laid-Open No. 3-28944. As an external recording device, a CD-ROM (Compac
There is a disk device such as t disk Read Only Memory).

In the external recording apparatus using this disk cache control, the buffer RAM is divided into sectors, and the sector requested by the host CPU and the sector in the vicinity are temporarily stored in the buffer RAM, and the same sector is stored. If the access is repeated, I try to access the buffer RAM instead of the disk. The structure of the buffer RAM of this external recording device is shown in FIG.
In FIGS. 10A, 10B, and 10C, a state in which data is recorded in sector units in the buffer RAM is shown, and sector identification numbers 1 to 7 are shown. For example, as shown in FIG. 10A, first, sectors 1, 2,
Read data of 3, 4 and 5, then host CPU
When there is a rewrite request for sector 3, the sector 3 is rewritten as shown in FIG. In addition, from the host CPU, sectors 4, 5, 6 and 7
When there is an access request for
Data of sectors 6 and 7 not recorded in M are read and recorded in the buffer RAM as shown in FIG. 10C, but sectors 5 and 6 are originally continuous when accessing the host CPU. Buffer, despite being data
It is recorded in non-contiguous areas in RAM.

For such an external recording device, a host
A case where the CPU performs reception processing assuming that data is always continuously obtained will be described with reference to FIG. FIG. 11A shows the structure of the buffer RAM of the external recording device and the structure of the internal memory of the host CPU. FIG. 11A shows blocks A, B, and C when a plurality of sectors are combined into one block. In addition, in the external recording device, the buffer RAM and the host CPU, and the buffer RAM and the disk are DMA (Dir
ect Memory Access), it is possible to transfer simultaneously in one DMA transfer if the recording areas of a plurality of blocks are continuous. Also the host CP
U is connected to the interface circuit of the external recording device via the interface bus, and the interface circuit, the buffer RAM and the disk are connected by the data bus for transferring data and the control bus for transferring control signals. Has been done. The access to the data bus is occupied by those who have acquired the bus right which is the access right of the bus.

At this time, when each block to be recorded in the buffer RAM of the external recording device is recorded in a divided state as shown in FIG. 11A, the host CPU
When an attempt is made to transfer data in continuous data blocks A, B, and C by one DMA transfer, the buffer RAM of the external recording device divides the data transfer into a plurality of DMA transfers. In addition, before each DMA transfer, the internal CPU provided in the external recording device calculates the address of which position in the buffer RAM to transfer the data. During the DMA transfer, the DMA has acquired the bus right, and the internal CPU has not acquired the bus right, so the state of the buffer RAM cannot be confirmed.
It is not possible to proceed with the processing such as the calculation described above. Therefore, the internal CPU acquires the bus right at the time when the DMA transfer is completed, and calculates which position of the buffer RAM to transfer the data next. Data cannot be transferred between the buffer RAM and the host CPU until the calculation of the address of the buffer RAM is completed.

On the other hand, generally, the data transfer rate between the host CPU and the interface circuit is higher than the data transfer rate in the external recording device. For example, the data transfer rate between the host CPU and the interface circuit is 4 Mbytes.
/ S, the data transfer rate in the external recording device is 150 kb
It is about yte / s. Therefore, the external recording device
The access of the host CPU is delayed by the access WAIT signal that suppresses the access of the host CPU, and the data access timing of the host CPU is controlled. Access to Figure 12
The time chart when controlling the access of the host CPU by the WAIT signal is shown. In FIG. 12, an access signal 111 is a signal output from the host CPU when the host CPU accesses the interface circuit, and an interface data bus 112 is a data bus connecting the host CPU and the interface circuit. . access
As described above, the WAIT signal 110 is a signal output from the external recording device to the host CPU, and access is suppressed when it is at the low level. The data bus 113 is a bus for transferring data, which is connected to the interface circuit, the buffer RAM, and the disk, and the bus right indicates where the access right to the data bus is acquired.

FIG. 12 shows a time chart when the host CPU reads data from the external recording device by one continuous DMA transfer of continuous data. In FIG. 12, at timings a and b, data has already been output to the data bus 113 inside the external recording device, and the access request of the access signal 111 is in time, so that the I / F data bus 112 is directly transferred by DMA transfer. It is possible to output the data 1 and the data 2. But the host CP
When U continues to read as it is, at timing c,
Since the data 3 is not yet prepared in the data bus 113, the WAIT signal 110 is set to Low from the external recording device to delay the access of the host CPU. When the data is output to the data bus 113, the external recording device waits for the WAIT signal 1
By setting 10 to High to allow the access of the host CPU, the host CPU can surely take in the data 3 at the timing d. Looking at the status of the data bus 113 during this time, first, the internal CPU uses the data bus 113 for processing such as DMA address setting. Then, when the DMA is activated, the internal CPU cannot occupy the data bus and suspends the operation to allow the DMA to transfer the data. During the data transfer, as shown in FIG. 12, DM
A occupies the data bus.

As described above, when the data is recorded in the discontinuous position, the access from the host CPU is performed by the access WAIT signal while the address of the buffer RAM is calculated for each DMA transfer. Is further delayed. As shown in FIG. 11B, a long WAIT period occurs for the host CPU between DMA transfers at the data discontinuity in the buffer RAM.

[0009]

The host CPU includes an interface bus, a DRAM (Dyna
nic Random Access Memory) and other devices are connected. There is a problem in that not only the external recording device can be accessed by the access WAIT signal described above, but also the device connected to another interface circuit cannot be accessed. For example, in the case of DRAM, it is necessary to refresh the host CPU at regular intervals.
Since the instruction of the DRAM refresh signal from U is also stopped, if WAIT is required for a certain period or longer, DRA
Problems such as the memory contents of M being destroyed occur. Also, if the host CPU access is delayed due to WAIT, the DMA remains in possession of the bus right until the data transfer ends, so the internal CPU cannot acquire the bus right and does other processing. The problem arises that you cannot do it.

An object of the present invention is to provide an external recording device,
It is an object of the present invention to provide a data transfer control method and a control device capable of controlling the transfer waiting time.

[0011]

In order to achieve the above object, the present invention provides:
In a recording / reproducing device that reads data from a recording device that records information, a transfer control unit that reads data from the recording device and receives an access of the upper device for each specific data amount, and for each access of the upper device,
A wait control unit for instructing a weight for suppressing the access to the host device for a predetermined time, and an instruction unit for instructing the weight control unit for the predetermined time in advance. .

Further, as a data transfer control method in the recording / reproducing apparatus, a step of reading data from the recording apparatus, and a step of accepting the access of the upper apparatus to the read data for each specific data amount, For each access of the host device, a step of instructing the host device of a weight for inhibiting the access for a predetermined time is included.

[0013]

The transfer controller reads data from the recording device and accepts an access from the host device (host CPU) for each specific amount of data. Specifically, the transfer control unit is connected to the host device and stores interface data (interface circuit) for temporarily holding data to be transferred to the host device, and data read from the recording device. In the buffer means (buffer RAM), the transfer between the recording device and the buffer means, and the transfer between the buffer means and the interface means, transfer of data in which addresses stored in the buffer means are continuous is performed once. Transfer means (DMA circuit) for controlling transfer,
Control means (internal CPU) for instructing the transfer means the transfer destination or transfer source address in the buffer means and the number of transfer data for each transfer, the interface means, the buffer means, the transfer means And a bus connected to the control means, wherein the control means controls the use of the bus by a bus right which permits the use of the bus, and the transfer of the bus right is controlled at the time of transfer control by the transfer means. The transfer means gives the transfer means an instruction to the control means after the transfer of the specific amount of data, and when the control means receives an interrupt from the transfer means, the control means gives the right to the control means. , And the address of the transfer destination or the transfer source and the number of transfer data in the next transfer by the transfer means are obtained. Since the address of the transfer destination or transfer source and the number of transfer data in the next transfer are obtained in advance, the value obtained in the transfer means can be immediately set at the time of the next transfer.

The wait control unit (WAIT control circuit) instructs, for each access of the host device, a wait time for inhibiting the access to the host device for a predetermined time. With this compulsory wait for each access, the bus occupation due to the transfer of the transfer means is released,
It is possible to secure the bus right of the control means (internal CPU) and obtain the transfer destination or transfer source address and the number of transfer data in the next transfer. Further, the predetermined time is set in consideration of the transfer time between the interface means and the host device and the transfer time between the storage device and the buffer means. For example, when the transfer time between the storage device and the buffer means is longer than the transfer time between the interface means and the host device, the transfer time difference must be weighted for the host device. The time obtained by dividing the time of the difference by the total number of accesses can be set as the predetermined time.

As described above, the wait time can be controlled by inserting a wait of a predetermined time for each access from the host device. Further, by ensuring the processing time of the control means during the transfer by the transfer means and calculating the next transfer address, the intermittent period between the transfers can be minimized.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a CD-ROM drive device (recording / reproducing device) using a data transfer control method and a transfer control device according to the present invention.

In FIG. 1, the host CPU 90 and the CD-ROM drive device 120 are the interface data bus 11
2, the host CPU 90 reads data from the CD-ROM drive device 120. Also,
The host CPU 90 is, in addition to the CD-ROM drive device 120,
A memory such as the DRAM 131 can also be accessed. Since the DRAM 131 needs to be refreshed within a fixed time, the host CPU 90 uses the refresh signal 130 to refresh the DRAM within a fixed time.
Instruct to 131.

The CD-ROM drive device 120 includes an internal CPU 103 for controlling the inside of the drive device, a buffer RAM 102 for temporarily storing data during data transfer, a DMA circuit 106 for controlling DMA transfer, and a specific CD-ROM recording. CD-ROM data conversion circuit 105 for converting the data format for use and the data format in the host CPU 90, a CD drive 107 for driving the mounted CD disk 108, and a host CP
WAIT control circuit 101 that outputs a WAIT signal to U90
And host via interface data bus 112
It has an I / F circuit 104 connected to the CPU 90. In addition, the host CPU 90, for the buffer RAM 102,
Data can be written and read via the I / F circuit 104.

WAIT control circuit 101, I / F circuit 104, CD-
ROM data conversion circuit 105, DMA circuit 106, buffer RA
The M102 and the internal CPU 103 are mutually connected to a data bus 113 for transferring data and a control bus 114 for transferring control signals. The control bus 114 has a bus right for the data bus 113 and the control bus 114, an address bus indicating an address, an R / W signal indicating a read / write instruction, a clock signal, etc. It is summarized in the control bus 114.

The internal CPU 103 uses the data bus 113.
The buffer RAM 102 can be accessed through the control bus 114 and the control bus 114, and the data transfer source or transfer destination address and the transfer data number can be set in the DMA circuit 106. Host C through circuit 104
It can communicate with the PU 90. Also, the internal CPU 103
The data transfer request from the host CPU 90 is
If the MA transfer does not end, the data transfer source or transfer destination address and the transfer data number in the next transfer are calculated, and the calculated next data transfer source address is set as a variable NEXT_SOURCE in the internal memory. Also, the number of transfer data is stored in the variable NEXT_LENGTH.
Further, the internal CPU 103 instructs a WAIT signal in the WAIT control circuit 101 and sets a fixed WAIT time by the WAIT signal.

The DMA circuit 106 uses the data bus 113.
And the buffer RAM 102 and the I / F via the control bus 114.
Data is transferred between the circuits 104 and between the buffer RAM 102 and the CD-ROM data conversion circuit. While data transfer is being performed by the DMA circuit 106, the internal CPU 103 passes the bus right to the DMA circuit 106 and interrupts the processing by the program. The DMA circuit 106 performs data transfer when the bus right is acquired, and when the set data transfer ends, notifies the internal CPU 103 of the end by the interrupt signal 115.

The I / F circuit 104 is connected to the CD-R from the host CPU 90.
For data transfer to the OM drive unit 120, the host CP
The data from U90 is taken in once, and the internal CPU 103
Alternatively, the data is held until the DMA circuit 106 reads it. If the host CPU 90 tries to write the next data before the internal CPU 103 or the DMA circuit 106 reads out the held data, the I / F control circuit 104 causes the WAI
A WAIT can be applied to the host CPU 90 via the T control circuit 101 (access is suppressed by the WAIT signal), and the write access of the host CPU 90 is delayed until the internal CPU 103 or the DMA circuit 106 reads data. On the other hand, the I / F control circuit 104 keeps the internal CPU 103 or the DMA circuit 106 until the host CPU writes data.
Read-out can be instructed to be delayed via control bus 114. In the case of data transfer from the CD-ROM drive device 120 to the host CPU 90, the internal C
The data sent from the PU 103 or the DMA circuit 106 is once fetched and waits for the host CPU 90 to read it. If there is no data in the I / F control circuit 104 and the host CPU 90 makes an access to read the data, the I / F control circuit 104 puts a WAIT on the host CPU 90 via the WAIT control circuit 101, and the internal CPU 103 or DM
The read access of the host CPU 90 is delayed until the A circuit 106 writes data. On the other hand, the I / F control circuit 104
The internal CPU 103 until the host CPU reads the data.
Alternatively, writing from the DMA circuit 106 is performed by the control bus 1
Instruct to delay via 14.

Further, the internal CPU 103 controls the CD drive 107 by the drive control signal 117 to read the data from the CD disk 108. CD drive 1
07 reproduces the data of the CD disk 108 to generate a CD reproduction signal 116. CD-ROM data conversion circuit 105
Converts the CD reproduction signal 116 into a data format that can be read by the internal CPU 103. For example, if the CD reproduction signal is serial data, it is converted into parallel 8-bit data. The internal CPU 103 uses DMA during playback of CD-ROM data.
The circuit 106 is controlled to transfer the output of the CD-ROM data conversion circuit 105 to the buffer RAM 102. Also, the buffer R
The AM 102 has a capacity several times as large as the minimum data transfer unit of the CD disk 108.

The CD-ROM drive device 120 uses the WAIT signal 1
10, access signal 111 and I / F data bus 112
Are connected to the host CPU 90 respectively. The access signal is, for example, an address signal of the host CPU 90, C
It consists of D signal and R / W signal. In this embodiment,
For the sake of simplicity, those signals are put together into an access signal 11
The access signal 111 is set to 1 when the data is read / written from the host CPU 90. Further, it is assumed that WAIT can be applied to access from the host CPU while the WAIT signal 110 is Low. Host CPU
The access signal 111 to L while the WAIT signal 110 is low.
Wait while keeping it ow, and access the data when the WAIT signal 110 is High.

The CD-ROM drive device 120 will be described below.
The access operation will be described by taking the reading of data from the memory as an example.

To read the data stored in the disk 108, the host CPU 90 takes the following procedure. The host CPU 90 receives the I signal by the access signal 111.
A data reproduction command (a command including a read instruction for reading the data stored in the disk 108 and an address of the disk 108) is written in the / F circuit 104.
The internal CPU 103 sends the data reproduction command to the I / F circuit 104.
From the data bus 113, and accordingly controls each of the components of the CD-ROM drive device 120 to read the data from the instructed address of the disk 108 and control the DMA circuit 106 to control the buffer RAM.
The read data is stored in 102. In addition, the internal CPU
103 controls the DMA circuit 106 to transfer the contents of the buffer RAM 102 to the I / F circuit 104. The I / F circuit 104 uses the access signal 1 when the host CPU 90 reads the data.
The data is detected by referring to 11, and the data is sequentially transmitted to the I / F data bus 112 in accordance with the reading. If the host CPU 90 does not read the data, it instructs via the control bus 114 to temporarily suspend the data transfer of the DMA circuit 106, and the DMA circuit 106 receives the bus right by the interrupt signal when this instruction is given. Is returned to the internal CPU 103. On the other hand, when the host CPU 90 reads data, I / F
When the circuit 104 is not in a state where data can be transmitted, the WAIT signal 110 is set to Low, the access of the host CPU 90 is WAIT, and the access cycle is extended.

Although the access from the host CPU 90 is performed in this way, in the present embodiment, the WAIT control circuit 101 inserts a WAIT of a fixed time for each access of the host CPU 90, so that the WAIT time is equal to or longer than the fixed time. It is controlled not to become.

The WAIT control circuit 101 includes a host CPU 90
For the WAIT signal 110, the wait instruction section 142 for instructing WAIT, and W for setting the WAIT time by the WAIT signal 110 (the time during which the WAIT signal 110 is low)
An AIT time setting unit 140 and a measuring unit 141 that is a counter for measuring the WAIT time are provided. FIG. 4 shows a time chart of data access in this embodiment. The operation of the WAIT control circuit 101 will be described with reference to FIG.

The WAIT time setting unit 140 includes the internal CPU 103.
The time is set to n times (n is a natural number) times the clock signal based on the clock signal of the control bus 114. The WAIT time can be set, for example, in consideration of the refresh time of the DRAM 131, the read time from the CD drive 107, the access time of the host CPU, and the like in advance. The wait instruction unit 142 monitors the access signal 111 output from the host CPU 90, and as shown in FIG.
When data is read / written to the / F control circuit 104, that is, when the access signal 111 becomes low, the WAIT signal 110 is made low to instruct WAIT. In addition, the WAIT control circuit 101 waits for the internal CPU 103.
The WAIT time n set in the time setting unit 140 is measured by the measuring unit 1
The counter 41 is set, and the measuring unit 141 counts down based on the clock signal of the control bus 114 during the time when the WAIT signal 110 is Low. When the count value of the measurement unit 141 becomes 0, the wait instruction unit 142 waits
The signal is set to High to allow the host CPU 90 to access. In this way, a WAIT can be applied for each access request from the host CPU 90, and the WAIT time is the internal CPU
The WAIT time is set to 103. Alternatively, instead of counting down by the measuring unit 141, the WAIT signal 110
During the time when is low, the measuring unit 141 counts up based on the clock signal and the count value of the measuring unit 141 and WA.
When the WAIT time n set in the IT time setting unit 140 is compared and they match, the wait instruction unit 142 outputs the WAIT signal.
It may be set to High.

In this way, the WAIT control circuit 101 is
By setting the CPU 103, the WAIT signal 110 can be set to Low for a certain period for each access with respect to the access from the host CPU 90. As a result, after the DMA circuit 106 performs data transfer, the internal CPU 103 makes the data bus 1
You will be able to use 13. In FIG. 4, the location accessed by the host CPU 90 at timing a is shown.
The WAIT signal 110 delays until timing c. DM
The A circuit 106 can return the bus right to the CPU 103 because the host CPU 90 has not read the data at the timing b after transferring the data 1 to the I / F circuit 104. Can be used. When the set time has passed since the WAIT was applied, the WAIT control circuit 101 sets the WAIT signal 110 to High. Since the host CPU 90 reads the data at this timing c, the DMA circuit 106 transfers the data 2 to the I / F circuit 104 after waiting the timing d when the CPU 103 releases the bus right. Similarly, the bus right is assigned to the DMA circuit 106 and the CPU 1
Can be obtained alternately in 03, and in this way, the data of data 1, data 2 ... Can be transferred as one DMA transfer. If the capacity of the data 1 is, for example, 1 byte, WAIT can be applied for each access of 1 byte.

Further, the internal CPU 103 or the DMA circuit 10
6 reads data when the host CPU 90 tries to write the next data before reading the data held in the I / F control circuit 104, and when the host CPU 90 has no data in the I / F control circuit 104, the host CPU 90 reads the data. At the time of access, the I / F control circuit 104 puts a WAIT on the host CPU 90 via the WAIT control circuit 101. In this case, therefore, the WAIT control circuit 101 sends the WAIT signal from the I / F control circuit 104. WAIT the host CPU 90 according to the instruction, and when ready to access, I / F control circuit 104
If there is a WAIT cancellation instruction from, the WAIT is canceled and access is permitted. The WAIT time in this case is as shown in FIG.
The time for resetting the DMA circuit 106 between data transfers, or as shown in FIG.
The time between the transfer and the DMA transfer, which is the internal CPU 10
3 is the time at which the transfer source, transfer destination, and data count of the next data are set in the DMA circuit 106. 5 and 6
4 shows a change of the WAIT signal in one DMA transfer, and one DMA transfer including the data transfer of data 1, data 2 ... Shown in FIG.

In this embodiment, the internal CPU 103 is
Since the data transfer source or transfer destination address and the number of transfer data in the next transfer are calculated and stored in the internal memory, only the time set in the DMA circuit 106 is taken into consideration and the calculation time is not taken into consideration. WAIT time can be shortened because it is good. Also, the WAIT time in this case may be measured and controlled by the measuring unit 141 of the WAIT control circuit 101 so that it does not become longer than a certain time.

For example, from the I / F control circuit 104 to the host CPU
If the data transfer to 90 is 4 Mbytes / sec, 204
The data transfer time for 8 bytes is 0.512 ms. On the other hand, the buffer from the CD-ROM data conversion circuit 105
Data transfer time of 2048 bytes to RAM102 is 1
The case where it takes a time of 3.333 ms is taken as an example. If the transfer from the I / F control circuit 104 to the host CPU 90 and the transfer from the CD-ROM data conversion circuit 105 to the buffer RAM 102 can be performed independently, if the WAIT time is not controlled, the host CPU 90 , 13.333 ms-0.
A WAIT time of 512 ms = 12.821 ms is generated. In case of 1Mbit DRAM, the maximum refresh interval is 8ms, so DR is
AM cannot be refreshed. According to this embodiment, as described above, the WAIT time is fixed and the host
Since WAIT is applied for each access of the CPU 90, 12.8
The WAIT time of 21 ms can be divided and instructed.
For example, when the WAIT time is set to 6.26 μs for each access of 1 byte, the CD-ROM data conversion circuit 1
In the data transfer of 2048 bytes from 05 to the buffer RAM 102, WAIT is instructed 2048 times. In this case, the total WAIT time in the data transfer of 2048 bytes is 6.26 μs × 2048 = 12.821 ms. As a result, the WAIT time can be divided and a long WAIT time is not taken, so that the DRAM can be refreshed in time.

The contents of the buffer RAM 102 are shown in FIG.
0 and as shown in FIG. 11 (a), there is a possibility of discontinuity due to cache control or the like. In this case, as shown in FIG. 6 and FIG. In the meantime, it takes time to reset the DMA circuit 106. From the host CPU 90 to the buffer RAM 102
Since the state inside is not known, the host CPU 90 tries to read continuous data by one data reproduction command. Therefore, in the CD-ROM drive device 120, the WAIT signal 110 is set to Low for each transfer unit (for example, for each sector) at the time of transfer in DMA transfer so that continuous data can be transferred from the host CPU 90. Then, the access of the host CPU 90 is delayed, and the read address is calculated in the internal CPU 103 during that time.

In this embodiment, the WAIT signal 110 is inserted and the bus right is DMAed in order to increase the time for calculating the read address in the internal CPU 103.
It passes from the circuit 106 to the internal CPU 103. Less than,
The data transfer method will be described together with the control method with reference to FIGS. 2 and 3 show a flow in the internal CPU 103 when transferring data from the CD-ROM drive device 120 to the host CPU 90. It is assumed that the data to be transferred is stored in the buffer RAM 102 before being transferred to the host CPU 90. Also,
In this embodiment, a WAIT cycle is set in the WAIT time setting unit 140 of the WAIT control circuit 101 each time transfer is started. If the WAIT time does not change, it can be done before the data transfer is started, so the WAIT time may be set only once at system startup.
The IT time setting unit 140 may be fixedly set in advance.

As shown in the processing in FIG. 2, the buffer RAM 1
In the data transfer from 02 to the I / F circuit 104, the internal CPU 103 first sets the WAIT time for the access from the host CPU 90 in the WAIT time setting unit 140 of the WAIT control circuit 106 (S1). Then the internal CPU
103 is a data transfer source address, in this case, a buffer
The address of the data start point in the RAM 102 is obtained, and the address of this data start point is set in the DMA circuit 106 (S
2). Next, the internal CPU 103 sets the address of the I / F circuit 104 in the DMA circuit 106 as a transfer destination address (S3), and obtains the number of data transfers that can be continuously sent at one time (S4). The data transfer source address, the transfer destination address, and the data transfer number are for one DMA transfer shown in FIGS. 5 and 6, and the data transfer number can be, for example, one sector. By determining whether or not the number of transfers set in S4 corresponds to all the data requested by the host CPU 90, it is determined whether or not there is data to be DMA-transferred next (S).
5). When the number of transfers corresponds to all the data requested by the host CPU 90, No is set and it is set that there is no data to be transferred to the DMA circuit 106 (data of the data to be transferred next, which is provided in the DMA circuit 106). Variable indicating quantity
NEXT_LENGTH is set to 0) (S8).

On the other hand, if the request from the host CPU 90 is not completed by the single transfer set in S2 to S4, the next transfer source address is further calculated and stored in the internal memory in the variable NEXT_SOURCE. Then, the next transfer data number is calculated and stored in the variable NEXT_LENGTH (S7). After the above processing, the DMA circuit 106 instructs the DMA circuit 106 to execute the interrupt processing by the interrupt signal 115 generated at the end of the transfer (S9), and D
The MA circuit 106 is activated to start data transfer (S1
0).

After the data transfer is started in the DMA circuit 106, when the bus right is handed to the internal CPU 103 as shown in FIG. 3, calculation for the next transfer (S
5 to S7 and S8) can be performed.
You may make it transfer to the process of S9 and S10 after the process of 4. In this case, it is sufficient that the data can be stored in the buffer RAM 102 before the next data transfer starts.

At the end of the first series of DMA transfers, as shown in FIG.
5, and notifies the internal CPU 103 of the DMA end interrupt. The internal CPU 103 secures the bus right in response to the interrupt signal and performs the processing shown in FIG. In FIG. 3, the internal CPU 103 clears the interrupt request (S
11), to prevent the interrupt from occurring again, DM
The A circuit 106 may be instructed not to permit interrupt processing. The variable NEXT_LENGTH is checked (S12), and if it is 0, there is no data to be transferred next, so data transfer end processing is performed (S21). As the transfer end processing, for example, no wait may be set for the WAIT control circuit 101.

If the variable NEXT_LENGTH is greater than 0 in S12, it is determined that there is data to be transferred, and the transfer source address previously calculated and stored in the variable NEXT_SOURCE is set in the DMA circuit 106 (S13), and the variable NEXT_LENG is set.
The number of transfer data stored in TH is set in the DMA circuit 106 (S14). After the above processing, the DMA circuit 106 is instructed to execute the interrupt processing by the interrupt signal 115 generated at the end of the transfer (S
15) Then, the DMA circuit 106 is restarted to start data transfer (S16). Then, after this transfer, it is inspected whether or not there is more data to be transferred (S1).
7). As a result of the inspection, when there is no data to be transferred, the variable NEXT_LENGTH is set to 0 through the No path (S2).
0). If there is data to be transferred, the next transfer source address is calculated and stored in the variable NEXT_SOURCE (S18), and the next transfer data number is calculated and stored in the variable NEXT_LENGTH (S19). This completes the interrupt processing.

In the above data transfer method, the WAIT period between data transfers shown in FIG. 5 corresponds to the processing period from S11 to S16 shown in FIG. The processing during this period is limited to the processing of checking the variable and transferring the value of the variable to the DMA circuit 106. In the processes S17 to S19 for calculating the address of the data to be transferred next, after the 1-byte data transfer by the DMA circuit 106, the bus right of the internal CPU 103 can be secured as shown in FIG. As a result, it can be surely executed until the next interrupt processing.

Although the data transfer from the CD-ROM drive device 120 to the host CPU 90 has been described in the present embodiment, conversely, data transfer from the host CPU 90 to the CD-ROM drive device 12 is performed.
Even in the data transfer to 0, the same effect can be obtained by the similar control. In this case, S6 shown in FIG.
The transfer destination address to be transferred next is calculated and stored in a variable, the contents of this variable are set in the DMA circuit 106 in S13 shown in FIG. 3, and the transfer destination address to be transferred next is calculated in S17. You can store it in a variable.

As described above, according to this embodiment, the transfer waiting time can be controlled. Also, by inserting a WAIT for a fixed time for each access from the host CPU,
By ensuring the processing time of the transfer control CPU during DMA transfer and calculating the next transfer address, the WAIT between transfers
The period can be minimized.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 7 shows the CD-ROM drive device 1 shown in FIG.
20 shows a configuration when the MPEG playback device 200 is added to 20. Under the control of the internal CPU 103, the MPEG reproducing apparatus 200 is supplied with the read data of the CD disk 108 to the buffer RAM 102 via the DMA circuit 106 and reproduces a video signal. Further, the DMA circuit 106 is the internal CPU 1
Under the control of 03, a buffer RAM is used in parallel to transfer data to the MPEG circuit 200 by using another channel.
Data may be transferred from 102 to the I / F circuit 104.

8 and 9 show the DMA circuit 106.
3 shows the state of the data bus 113 when data is transferred to both the MPEG playback device 200 and the I / F circuit 104. In FIG. 8, also in the present embodiment, as shown in FIG. 4 of the first embodiment, the WAIT of the WAIT time set for each access of the host CPU 90 is inserted.

In this embodiment, since data transfer to the MPEG playback device 200 by the DMA circuit 106 occurs every other time, MPEG playback is performed during the time when the internal CPU 103 was using the bus in the first embodiment. Data may be transferred to the device 200, and the internal CPU 103 may not be able to use the bus. Therefore, as shown in FIG. 9, during the period in which the data is transferred to the MPEG playback device 200 and the data is transferred to both the I / F circuit 104, the first control is performed by the WAIT control circuit 101.
The WAIT time longer than that in the embodiment of FIG.
The data read of No. 4 is sent first to secure the time for the internal CPU 103 to use the data bus. That is, by adjusting the WAIT time according to the situation of using the bus, the time during which the internal CPU 103 operates can be secured. In this case, in S1 of the flow chart shown in FIG. 2 described above, when the data is transferred to the MPEG reproducing apparatus 200, the WAIT time is set to be longer than when the data is not transferred to the MPEG reproducing apparatus 200. can do.

According to the second embodiment, the MPEG playback device 20
Even when there is data transfer to 0, the setting of the WAIT time can be set according to the system status so that the calculation time in the internal CPU 103 can be secured.

[0050]

According to the present invention, in the data transfer control device and the recording / reproducing device that control data transfer using the WAIT signal, the length of time during which the transfer is interrupted by the WAIT signal can be limited. Therefore, system operation stability can be improved. Further, according to the present invention, the length of the WAIT time generated for each data transfer is adjusted according to the internal state of the device performing the data transfer, and the data transfer rate can be secured without impairing the stability of the system.
Further, it is possible to realize a transfer rate that does not hinder the operation of the external recording device while limiting the access WAIT time that occurs in the host CPU.

[Brief description of drawings]

FIG. 1 is a CD using a data transfer control device according to this embodiment.
FIG. 3 is a block diagram of a ROM drive device.

FIG. 2 is a flowchart showing a part of a data transfer control procedure of the data transfer control device according to the present embodiment.

FIG. 3 is a flowchart showing a part of a data transfer control procedure of the data transfer control device according to the present embodiment.

FIG. 4 is a timing chart for explaining data transfer control by a WAIT signal in the present embodiment.

FIG. 5 is a timing chart for explaining data transfer control of the data transfer control device according to the present embodiment.

FIG. 6 is a timing diagram for explaining data transfer control of the data transfer control device according to the present embodiment.

FIG. 7 is an application of the data transfer control device according to the present embodiment.
It is a block diagram which shows the 2nd Example of a CD-ROM drive device.

FIG. 8 is a timing chart showing an operation of data transfer control in the second embodiment.

FIG. 9 is a timing chart showing an operation of data transfer control in the second embodiment.

FIG. 10 is an explanatory diagram illustrating a situation in which a discontinuous portion occurs in a buffer RAM.

FIG. 11 is an explanatory diagram illustrating that a long WAIT time occurs during data transfer due to a discontinuous portion of the buffer RAM.

FIG. 12 is a timing chart showing an operation of data transfer control according to a conventional example.

[Explanation of symbols]

90 ... Host CPU, 101 ... WAIT control circuit, 102 ... Buffer RAM, 103 ... CPU, 104 ... I / F circuit, 106 ... D
MA circuit, 110 ... WAIT signal, 111 ... Access signal, 1
12 ... I / F data bus, 113 ... Data bus, 114 ...
Control bus, 120 ... CD-ROM drive device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Matsunaga 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Imaging Information Systems (72) Inventor Hirofumi Tsujimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (72) Inventor Tamotsu Ito, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company, Hitachi, Ltd.

Claims (5)

[Claims] 1. A recording / reproducing apparatus for reading data from a recording apparatus for recording information in accordance with an access request from the upper apparatus, wherein the data is read from the recording apparatus, and a transfer for accepting an access of the upper apparatus for each specific data amount is performed. A control unit, a weight control unit for instructing a weight for suppressing the access for a predetermined time to the upper device for each access of the upper device, and the weight for the predetermined time. A recording / reproducing apparatus comprising: an instruction means for instructing a control unit in advance. 2. The transfer control unit according to claim 1, wherein the transfer controller is connected to the host device and temporarily holds data to be transferred to the host device; and data read from the recording device. In the buffer means for storing, the transfer between the recording device and the buffer means, and the transfer between the buffer means and the interface means, the transfer of data having consecutive addresses stored in the buffer means is regarded as one transfer. Transfer means for controlling, control means for instructing the transfer means of the transfer destination or transfer source address and the number of transfer data in the buffer means for each transfer, the interface means, the buffer means A bus connected to the transfer means and the control means, wherein the control means uses the bus. The use of the bus is controlled by a bus right that permits the bus right, and when the transfer is controlled by the transfer means, the bus right is given to the transfer means, and the transfer means transfers the specific data amount, and then the control means. To the interrupt means, the control means, when there is an interrupt from the transfer means,
A recording / reproducing apparatus characterized in that the control means secures the bus right and obtains the address of the transfer destination or the transfer source and the number of transfer data in the next transfer by the transfer means. 3. The recording medium according to claim 1, wherein the instructing means defines the predetermined time corresponding to each of a plurality of predetermined states of the recording / reproducing apparatus and responds to the state of the recording / reproducing apparatus. And instructing the predetermined time corresponding to the state, the weight control unit sets the predetermined time instructed by the instructing unit, and the weight instructing unit instructing the weight. And a measuring means for measuring the time from the start of the weight instruction by the weight instructing means until the elapse of a predetermined time set by the setting means, the weight instructing means comprising: A recording / reproducing apparatus, wherein the weight is released after a lapse of a predetermined time by the measuring means. 4. The output device according to claim 3, further comprising an output unit for outputting the data read from the storage device to the outside, the transfer unit further controlling transfer between the buffer unit and the output unit, The recording / reproducing apparatus, wherein the instruction means sets a plurality of predetermined states of the recording / reproducing apparatus to a state in which the data is output from the output unit and a state in which the data is not output. 5. A data transfer control method in a recording / reproducing apparatus for reading data from a recording apparatus for recording information in accordance with an access request from a host apparatus, the method comprising the step of reading data from the recording apparatus, and a specific amount of data. A step of accepting the access of the higher-level device to the read data; and, for each access of the higher-level device, instructing the higher-level device a weight for inhibiting the access for a predetermined time. And a data transfer control method.