JP2002278918A - Dma device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor whether transfer which a descriptor prescribes satisfies a temporal limit or not, to suppress the dispersion of data transfer speed, to delay the start of DMA when transfer is below minimum time and to interrupt transfer in the case of the abnormal delay of data transfer. SOLUTION: A DMA device is provided with one or more descriptors 610 and 620 showing the blocks of transfer information and including transfer source address information 612 and 622 and transfer byte number information 613 and 623 and a transfer control means 400 reading transfer information that information of the descriptors designates from the memories 630 and 640. Transfer time minimum value and maximum value are included in the descriptors. In the case of transfer with transfer time below the minimum value, the next information reading of the descriptor is delayed until time becomes the minimum value. When it exceeds the maximum value, a transfer processing is interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access (DMA) device. This apparatus is used, for example, for transferring image data in an image forming apparatus such as a printer, a digital copying machine, or a digital facsimile, or for transferring image data to an image storage apparatus.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No.
1 bus cycle transfer, 2 bus cycle transfer, burst transfer and cycle steal transfer are described. The burst transfer includes a single transfer mode, a repetitive transfer mode, and an array chain transfer mode. And 4 modes of link array transfer mode
Is explained.

In a conventional descriptor type controller (DMAC), the transfer start timing can be controlled by using an underflow of a counter, but the transfer end timing cannot be delayed. In addition, even if the transfer target block specified by the descriptor can be transferred continuously, it cannot be temporarily stopped and restarted when the block transfer is completed.

To cope with this, Japanese Patent Application Laid-Open No. 2000-298
Japanese Patent Application Laid-Open No. 640 discloses that the transfer control means adds interrupt occurrence timing information (timer variable) to each descriptor.
A method for solving the above-described problem is described in which an interrupt signal is generated at a timing designated by interrupt generation timing information held by the descriptor for each transfer of one unit based on information of one descriptor.

In the above method, the interval from the end of one unit transfer specified by the descriptor to the start of the next one unit transfer can be controlled by a designated timer variable. Although possible, it was not an absolute time specification of how long each unit should actually be transferred.

[0006]

In the actual DMA transfer, it is possible to control in which period the transfer specified by each descriptor should be completed, that is, in what period the transfer control of each unit should be completed. More flexible control is possible.

A timer variable controls the interval between the end of the DMA and the start of the DMA defined by the next descriptor.
If the DMA transfer fluctuates due to the bus status, etc.
A's absolute time cannot be guaranteed. For example, when a device such as a printer or a scanner exchanges data with the image processing controller by DMA, data starts to flow at regular intervals when the device starts operating. From the end of the above, not only the interval of the start of the DMA defined by the next descriptor can be controlled but also the data transfer speed expected by the device in normal operation can be controlled more flexibly. In addition, it is possible to detect an abnormal state deviating from the expected speed.

The first object of the present invention is to make it possible to monitor whether the transfer specified by the descriptor satisfies the time limit, and to suppress the variation of the data transfer speed as a second object. The third object is to delay the start of DMA when the time is less than the above, the fourth object is to stop an abnormal delay in data transfer, and the fifth object is to interrupt the transfer when the maximum time is exceeded. And

[0009]

(1) One or more descriptors each including transfer source address information and transfer byte number information of one transfer unit, each indicating a transfer unit division of transfer information; and these descriptors. A transfer control means for sequentially reading transfer source address information and transfer byte number information from the memory and reading transfer information from the memory in accordance with the information, the descriptor manages the time allotment of the transfer addressed thereto. A DMA device comprising time information.

For example, if the time information is a transfer time minimum value for each descriptor, if the transfer is completed within a time shorter than the transfer time minimum value, the next processing is delayed until the transfer time minimum value is reached. In addition, it is possible to guarantee that the processing of one DMA specified by the descriptor is longer than a certain minimum time, and it is possible to expect advantages such as simplification of processing of hardware and software depending on the DMA processing. Alternatively, for example, if the time information is the maximum transfer time of the descriptor unit, if the DMA processing exceeds the maximum transfer time, the transfer is interrupted, etc. The transfer process can be interrupted.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (2) One or more descriptors each including transfer source address information and transfer byte number information of one transfer unit, each indicating a transfer unit division of transfer information; and sequentially from these descriptors Transfer control means for reading transfer source address information and transfer byte number information and reading transfer information from a memory in accordance with the information, wherein the descriptor includes transfer time minimum value information. apparatus.

For example, if the transfer is completed within a time shorter than the minimum transfer time, the next processing is delayed until the minimum transfer time is reached, so that the processing of one DMA specified by the descriptor is longer than the minimum time. This can be expected to have advantages such as simplification of hardware / software processing dependent on DMA processing.

(3) The transfer control means according to (2), wherein when the transfer is completed within a time shorter than the minimum transfer time, the transfer control means delays the next processing until the transfer time is minimum.
A device.

According to this, the processing of one DMA specified by the descriptor becomes longer than the minimum time, and the processing of hardware and software depending on the DMA processing can be simplified.

(4) One or more descriptors each including transfer source address information and transfer byte number information of one transfer unit indicating a transfer unit classification of transfer information; and a transfer source address sequentially from these descriptors. Transfer control means for reading information and transfer byte number information and reading transfer information from a memory according to the information, wherein the descriptor includes transfer time maximum value information.

For example, if the DMA processing exceeds the maximum transfer time, the transfer process is interrupted or the like, so that an abnormality in the transfer process or the transfer system can be monitored and the transfer process can be stopped early.

(5) The DMA device according to (4), wherein the transfer control means interrupts the transfer if the transfer does not end after the maximum transfer time has elapsed.

A DMA device, wherein the descriptor includes transfer time maximum value information.

According to this, by monitoring whether or not the transfer time exceeds the maximum transfer time, if the transfer does not end after the maximum transfer time has elapsed, it is determined that the transfer processing or the transfer system is abnormal, and the transfer system is immediately determined to be abnormal. Transfer processing can be interrupted.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[0021]

FIG. 1 shows the configuration of an embodiment of the present invention. CP
U100 is a microprocessor. The ROM 200 is a read-only memory that stores a program executed by the CPU 100. The memory controller 300
A circuit that generates a control signal of the M600 and reads and writes data to and from the RAM 600 in response to requests from the CPU 100 and the DMA controller 400.

The DMA controller 400 is a main part of the DMA device according to one embodiment of the present invention. I / O device 5
00 is a device to which data is transferred, such as a hard disk. The RAM 600 is a readable and writable random access memory. Before performing the DMA, the CPU 100 prepares a descriptor in the RAM 600.

FIG. 2 shows an embodiment in which two descriptors 610 and 620 are generated on the RAM 600, and FIG. 3A shows the structure of one descriptor 610.
If two descriptors are generated as shown in FIG. 2, the start address of the second descriptor 620 is stored in the next descriptor pointer register 611 (one area of the memory: one register) of the first descriptor 610. ing.

The data of the transfer source address register 612 of the first descriptor 610 is stored in the buffer memory 630.
Indicates the start address of The buffer memory 630 stores data to be transferred. The transfer byte number register 613 of the first descriptor 610 stores the number of bytes to be transferred among the data stored in the buffer memory 630.

The least significant bit, bit N, of mode word register 614 of first descriptor 610
o. As shown in FIG. 3B, when the transfer indicated by the first descriptor 610 is completed, flag data CONT for determining whether or not to generate an interrupt exists in the data 0, as shown in FIG. When the DMA controller 40
0 generates an interrupt signal.

Similarly, the next descriptor pointer register 621 shown in the second descriptor 620
Contains the start address of the third descriptor, if any, but in the illustrated example, since the second descriptor 620 is the last descriptor, to inform the DMA controller 400 that it is the end, “0” is stored. The transfer source address register 622 of the second descriptor 620 indicates the start address of the buffer memory 640, and the buffer memory 640 stores data to be transferred. The transfer byte number register 623 of the second descriptor 620 stores the number of bytes to be transferred among the data stored in the buffer memory 640. Nothing is set in the mode word register 624 of the second descriptor 620.

In this embodiment, as shown in FIG. 3B, by providing an interrupt enable bit “CONT” in the descriptor 610 before the last descriptor, it is possible to generate an interrupt for each descriptor. I have to. Although the size of the descriptor is not limited to any word, there is no problem in the function, but here, it is assumed to be 4 words, and the increment address from the head address of the descriptor is shown as an offset in FIG.

The next descriptor address register 611 stores the address of the next descriptor 620 to be executed so that the descriptors 610 and 620 can be linked in a chain structure. The data of the transfer source address register 612 is such that the descriptor 610 is stored in the buffer memory 630 and stored in the I / O device 50.
The start address of the transfer data (630) secured on the RAM memory 600 is shown as the one to be transferred to 0. The data in the transfer byte number register 613 indicates the length (byte number) to be transferred.

The mode word register 614 stores a word for setting an operation mode for each descriptor, and details are shown in FIG. The mode word register 614 has a length of 32 bits in this embodiment. Bit No. which is the least significant bit Data C of 0
The ONT can take two states, "0" and "1", and this Bit data CONT functions as an interrupt enable bit. The interrupt enable bit indicates that generation of an interrupt is permitted when the transfer indicated by the descriptor whose bit is set to “1” is completed. 16th to 23rd of the mode word register 614
The bit is a minimum value timer variable, and the 24th to 31st bits are a maximum value timer variable. The minimum timer value represented by the minimum timer variable is transfer time minimum value information, and the maximum timer value represented by the maximum timer variable is transfer time maximum value information.

FIG. 4A shows the configuration of a DMAC (DMA controller) 400. The descriptor pointer register 401 is a register for storing the head address of the descriptor (610/620) stored on the RAM memory 600.

The control register 402 is a CPU
This register receives a DMA operation start instruction from 00. The address register 403 stores the transfer source address held by the descriptor, and the transfer counter 409 is a counter that counts the actual number of transfer bytes. The transfer byte number register 410 is a register for storing the transfer byte number indicated by the descriptor.

The DMA transfer control circuit 404 accesses the memory at the address indicated by the sum of the transfer source address of the address register 403 and the count value (the number of transferred bytes) of the transfer counter 409, and performs actual transfer. .
The mode register 406 is a register for storing the data of the mode word registers 614 and 624 of the descriptor. The data of the mode word register 614 is
This is shown in FIG.

The descriptor control circuit 405 is a circuit for reading the descriptors 610 and 620.
The data ("1" or "0") of the interrupt instruction bit CONT of the mode register 406 is supplied to the DMA transfer control circuit 404 via the interrupt enable signal line 407. This is a signal notifying whether or not to generate an interrupt when the transfer is completed.

When the transfer indicated by the descriptor is completed, the DMA transfer control circuit 404 (DMAC 400)
Provides a signal to notify the CPU 100 of an interrupt via the interrupt signal line 408.

The CPU 100 sets transfer data and a descriptor on the RAM 600, and
00 is written in the descriptor pointer register 401 of the first 00, and the bit EXEC shown in FIG.
Then, when "1" is written, the DMAC 400 starts the transfer operation in response to this.

FIG. 5 shows a transfer operation flow of the DMAC 400. The start (step 701) is when the CPU 100
EXEC of control register 402 of MAC 400
Starting by setting the bit to “1”, the DMAC400
Goes to descriptor reading (step 702). In the following, the word “step” is omitted in parentheses, and step No. Write only numbers.

That is, the descriptor on the memory is read. Specifically, the DMAC 400 reads the contents of the address (descriptor 610) indicated by the data of the descriptor pointer register 401 for four words, and sets the first word (next descriptor address) to the next descriptor shown in FIG. The pointer is stored in the pointer register 411, the second word (transfer source address) is stored in the address register 403, the third word (transfer byte number) is stored in the transfer byte number register 410, and the fourth word (mode) is stored. Word: CONT, minimum value timer variable, maximum value timer variable)
06 and the control register 402. FIG. 6 shows the transition of the control signal at that time.

Referring to FIG. 6, the CLK signal indicates a clock signal that is the basis of the operation of the system. TRZ_ST
The ART signal indicates that access to the memory has been started. The ADDRESS signal indicates a memory address. The DATA signal indicates a data signal output from the memory. The RDWR signal indicates whether access to the memory is read or write. The IADDR signal is DMAC400
Shows the address of the register inside the. The IRDWR signal indicates whether the access inside the DMAC is reading or writing. The IDATA signal indicates data inside the DMAC. I
The RDATA signal is the DMAC specified by the IADDR signal.
Is a signal indicating the contents of the internal register.

At the rising edge of the CLK signal shown in FIG.
The _START signal is asserted to indicate that access has been started, and at the same time, the ADDRESS signal becomes valid, and the RDWR signal becomes high, indicating that reading is to be performed. At the rising edge of the clock, the ADDRE
Upon receiving the SS signal, the memory outputs data as a DATA signal. At the same time, the DMAC outputs the address of the register to be fetched into the IADDR signal,
The signal indicates a write to the internal register. The data (DATA) in the memory is output as internal data (IDATA). At the rising edge of the clock, the internal data (IDATA) of the DMAC is taken into an internal register indicated by the IADDR signal, and the contents of the register are held in the IRDATA signal. The rising of the clock indicates an idle cycle without any data. The clock rise indicates the start of the next access. In this figure, one memory access is performed in four clocks. Thus, the data of the registers 611 to 614 of the first descriptor 610 are written to the registers 411, 403, 410, and 406 of the DMAC 400 (702).

After loading the contents of the descriptor into each of the internal registers, a timer circuit 412 is used to perform DMA for guaranteeing the maximum timer value represented by the maximum timer variable and the minimum timer value represented by the minimum timer variable in the mode register 406. And initializes the counter register 413, sets the maximum timer value and the minimum timer value in the counter register 413, and starts the timer circuit 412 (709). That is, the countdown (time measurement) of the clock pulse from the value of the counter register 413 is started.

Next, the DMAC 400 sets each register 41
DMA defined by 1,403,410,406 data
Transfer (703) is started, and one descriptor (first
It is checked whether the transfer of the block specified by the descriptor 610 has been completed (704). If the block transfer has not been completed, the address is updated for the next transfer (705). The transfer (703) is repeated until the transfer of the block is completed.

During this time, the timer circuit 412 is performing a count (time measurement) operation during the operation of the DMA, and when the time value exceeds the maximum timer value (711), a time-out interrupt is generated and the transfer is interrupted there ( 712).

When the transfer of the block is completed before the time of the maximum timer value elapses, the DMAC 400 checks whether the chain of the descriptor itself has been completed, that is, whether the entire transfer has been completed (706).

As described above, in the illustrated example, since the second descriptor 620 is the last descriptor, to inform the DMA controller 400 of the end,
If "0" is written in the next descriptor pointer 621, and the descriptor that has just been transferred is the last descriptor (second descriptor 620), the data is stored in the next descriptor pointer register 411 of the DMAC 400. Since "0" has been written, it is determined based on this data that the entire transfer has been completed (706).

However, if the transfer just completed is based on the data of the first descriptor 610, the next descriptor pointer register 411 stores the data of the next descriptor pointer 611 of the first descriptor 610 (the second descriptor 620). DMAC 400 has the next descriptor (6
Since (20) is valid, the value "1" of the bit CONT stored in the mode register 406, which was originally in the mode register 614, is read via the line 407 and is "1". Therefore, a continuation interrupt is generated (70
7). Thereafter, if the timer circuit 412 initialized and operating in the timer initialization (709) has counted the timer value equal to or more than the minimum timer value of the counter register, the process proceeds to reading of the next descriptor (702). If the count is not longer than the minimum timer value, the process waits until the count becomes equal to or longer than the minimum timer value, and then reads the next descriptor (70).
It moves to 2) (710).

The order of steps 707 and 710 may be reversed. That is, the DMAC 400 is:
The bit EXEC of the control register 402 is set to "0".
And the interrupt request line 408 to the CPU 100 is cleared.
(707). And the CPU 10
0 waits in response to this to set bit EXEC of control register 402 to "1". When it becomes "1", the data of the second descriptor 620 is read and the registers 411, 403, 410, 406,
Writing (702) and transfer (703) are performed in 402.

When the transfer based on the data of the second descriptor 620 is completed, the data of the next descriptor pointer register 411 is "0".
The DMAC 400 generates a completion interrupt signal (70
8) Complete all processing.

The continuation interrupt (707) is issued by the DMAC 400
Is valid when the CONT bit of the control register is “1” (first descriptor 610), but is “0”.
In the case of (second descriptor 620), no continuous interrupt occurs. The mode word (624) in the final descriptor (620) also has a bit corresponding to the CONT bit, but this bit is set to "0" and the CONT bit of the control register 402 becomes "0".
400 generates a completion interrupt signal without generating a continuous interrupt.

When the DMA processing of one descriptor is completed and the next descriptor processing is performed, the initialization of the timer (709) is performed after the reading of the descriptor (702) in this embodiment. Timer circuit 412
Generates a timeout interrupt (712) when it exceeds the maximum timer value (711). That is, the maximum timer value defines the maximum time until the next processing including the loading of the descriptor. When the processing of all blocks is completed (70
6) The timer circuit 412 is stopped because the timer circuit 412 does not need to generate an interrupt any more (713).

[0050]

For example, if the time information is a transfer time minimum value for each descriptor, if the transfer is completed within a time less than the transfer time minimum value, the next processing is delayed until the transfer time minimum value. As a result, it is possible to guarantee that the processing of one DMA specified by the descriptor is longer than a certain minimum time, and it is possible to expect advantages such as simplification of processing of hardware and software depending on the DMA processing. . Alternatively, for example, if the time information is the maximum transfer time of the descriptor unit, if the DMA processing exceeds the maximum transfer time, the transfer is interrupted, etc. The transfer process can be interrupted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DMA system according to an embodiment of the present invention.

FIG. 2 is a table schematically showing descriptors set on a RAM 600 shown in FIG.

FIG. 3A shows a first descriptor 61 shown in FIG.
FIG. 4B is a diagram schematically showing a word configuration of 0, and FIG. 4B is a diagram showing a data configuration of the mode register 614 shown in FIG.

FIG. 4A shows a DMA controller 40 shown in FIG.
0 is a block diagram showing the functional configuration of the control register 402, and FIG. 4B is a table showing the contents of data stored in the descriptor pointer register 401 shown in FIG. FIG.

FIG. 5 shows a DM of the DMA controller 400 shown in FIG.
This is a flowchart showing the outline of the A transfer control.

FIG. 6 shows an example in which the DMA controller 400 shown in FIG.
This is a time chart showing the generation timing of read / write data and control signals when reading data from M600.

Claims (5)

[Claims] 1. One or more descriptors each including transfer source address information and transfer byte number information of one transfer unit, each indicating a transfer unit division of transfer information; and transfer source address information sequentially from these descriptors. Transfer control means for reading transfer byte number information and reading transfer information from a memory in accordance with the information.
A device according to claim A, wherein the descriptor includes time information for managing an assigned time of a transfer addressed to the device. 2. One or more descriptors each including transfer source address information and transfer byte number information of one transfer unit, each indicating a transfer unit division of transfer information; and transfer source address information sequentially from these descriptors. Transfer control means for reading transfer byte number information and reading transfer information from a memory in accordance with the information.
A device according to claim A, wherein the descriptor includes minimum transfer time information. 3. The DMA device according to claim 2, wherein said transfer control means delays a next process until said transfer time is shorter than said transfer time minimum value. 4. One or more descriptors each including transfer source address information and transfer byte number information of one transfer unit, each indicating a transfer unit division of transfer information; and transfer source address information sequentially from these descriptors. Transfer control means for reading transfer byte number information and reading transfer information from a memory in accordance with the information.
A device according to claim A, wherein the descriptor includes transfer time maximum value information. 5. The DMA device according to claim 4, wherein said transfer control means interrupts the transfer if the transfer does not end after the maximum transfer time has elapsed.