JP4410978B2 - Data transfer apparatus and operation control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer device used in IEEE 1394 or the like using a storage device such as a FIFO for data transmission, and more particularly to a data transfer device forming a LINK device compliant with the OHCI (Open Host Controller Interface) standard.
[0002]
[Prior art]
Conventionally, in a data transfer device that uses a storage device such as a FIFO for data transmission and conforms to the IEEE 1394 standard, there is a problem that transfer performance deteriorates if the packet transmission start timing is late. Such a problem appears particularly prominently when a hard disk device (hereinafter referred to as an HDD device) is connected to a personal computer (hereinafter referred to as PC) having an interface conforming to the IEEE 1394 standard (hereinafter referred to as IEEE 1394 interface). When the data is transferred between them.
[0003]
In such a case, the PC and the HDD device use an asynchronous packet among isochronous packets and asynchronous packets defined by the IEEE 1394 standard. Also, a physical request packet prepared for performing high-speed data transfer only by hardware without any software among asynchronous packets is transmitted from the HDD device to the PC. Then, the IEEE 1394 interface device in the PC performs processing on the received physical request packet, and then transmits a physical response packet.
[0004]
The IEEE 1394 interface device of the PC and the HDD device are connected by a bus conforming to the IEEE 1394 standard (hereinafter referred to as the IEEE 1394 bus), and the IEEE 1394 interface device is connected to the CPU of the PC via the PCI bus. A data flow in such an IEEE 1394 interface device in the PC will be described. FIG. 15 is a diagram showing a schematic timing example in the data flow in the IEEE 1394 bus and the PCI bus.
[0005]
As shown in FIG. 15, in the period A, a physical read request packet is transmitted from the HDD device to the PC on the IEEE 1394 bus. Next, in period B, the IEEE 1394 interface device in the PC reads data from the memory unit in the PC via the PCI bus and chipset, completes the data reading from the memory unit, and sends a packet to the transmission FIFO. prepare. Next, in period C, a physical read response packet is transmitted from the PC to the HDD device on the IEEE 1394 bus.
[0006]
In such a state, the data transfer request from the HDD device to the PC is made by a physical read request packet, and since data is being transferred at high speed only by hardware without software, as shown in FIG. Even in a state where the data reading process in the B period is not completed, the first data of the transmission packet is prepared in the transmission FIFO, so a method for improving the processing capability by accelerating the start of the C period can be considered. .
[0007]
[Problems to be solved by the invention]
However, in the IEEE 1394 standard, once the packet transmission is started, the data transmission cannot be stopped. For this reason, in the method for improving the processing capability as described above, if the transmission start time is set too early, as shown in FIG. 17, the data reading on the PCI bus side is not in time, and the physical data being transmitted on the IEEE 1394 bus is not in time. There is a problem that the data in the response packet is interrupted, and the hatched portion in FIG. 17 becomes an incomplete data portion, resulting in an incomplete packet.
[0008]
Also, even when the transmission start time is not so advanced, various devices are connected to the PCI bus, and access to these devices shortens the PCI bus usage time allocated to the IEEE 1394 interface device. In some cases, the last data in the transmission packet could not be prepared. In such a case, according to the IEEE 1394 protocol, the HDD apparatus transmits the same physical request packet as described above, and reprocessing is started.
[0009]
The present invention has been made to solve the above-described problems, and can improve the processing performance by increasing the transmission packet transmission start timing, and suppress the generation of incomplete data error packets. Data transfer device that can And its operation control method The purpose is to obtain.
[0010]
[Means for Solving the Problems]
A data transfer device according to the present invention is a data transfer device that transfers data between an external system device and an internal system device.
A first interface circuit unit for interfacing with the internal system device;
A second interface circuit unit for interfacing with the external system device;
Data input from the internal system device via the first interface circuit unit is temporarily stored, and the stored data is stored via the second interface circuit unit in response to the input control signal. A data storage unit for transmission to be transmitted to the device;
The total number of write data stored in the transmission data storage unit is monitored. When the monitored total number of write data exceeds a predetermined value, the write data stored in the transmission data storage unit is sent to the second interface circuit unit. A control circuit unit for controlling the operation of the transmission data storage unit,
With
In the period before the total number of write data monitored reaches a predetermined value, the control circuit unit A signal indicating that data transfer is possible is input from the first interface circuit unit. A period during which a signal indicating that data transfer is impossible is input from the internal system apparatus is monitored, and the predetermined value is set so that the period corresponds to the count time of the write data. Increment When the total number of the write data monitored is less than the predetermined value and less than the amount of data requested to be transmitted from the external system device, the second interface circuit unit is connected to the transmission data storage unit. Data transmission to is prohibited.
[0011]
Specifically, the control circuit unit is While a signal indicating that data transfer is impossible is input from the internal system device A preset value is added to the predetermined value.
[0012]
In addition, the control circuit unit is A signal indicating that data transfer is possible is input from the internal system device. During this time, the addition of the preset value to the predetermined value may be stopped.
[0013]
On the other hand, when the control circuit unit is transmitting data from the transmission data storage unit to the second interface circuit unit, the data transmission from the internal system device is not in time and data transmission from the transmission data storage unit When the data transfer is performed again from the internal system device, if the total number of the monitored write data becomes the amount of data requested to be transmitted from the external system device, the transmission data storage unit Data transmission to the second interface circuit unit may be performed.
In addition, an operation control method for a data transfer device according to the present invention includes a first interface circuit unit that interfaces with an internal system device,
A second interface circuit unit for interfacing with an external system device;
Data input from the internal system device via the first interface circuit unit is temporarily stored, and the stored data is stored via the second interface circuit unit in response to the input control signal. In an operation control method of a data transfer device that includes a data storage unit for transmission to be transmitted to the device and performs data transfer between the external system device and the internal system device,
Monitor the total number of write data stored in the transmission data storage unit,
In the period before the total number of monitored write data reaches a predetermined value,
A signal indicating that data transfer is possible is input from the first interface circuit unit. Monitoring a period during which a signal indicating that data transfer is impossible is input from the internal system device;
The predetermined value is set so that the period corresponds to the count time of the write data. Increment Let
When the total number of monitored write data is less than the predetermined value and less than the amount of data requested for transmission from the external system device, the transmission data storage unit is connected to the second interface circuit unit. Data transmission is prohibited.
Specifically, while a signal indicating that data transfer is impossible is input from the internal system device, a preset value is added to the predetermined value.
The addition of the preset value to the predetermined value may be stopped while a signal indicating that data transfer is possible is input from the internal system device.
On the other hand, when performing data transmission from the transmission data storage unit to the second interface circuit unit, if data transmission from the internal system device is not in time and data transmission from the transmission data storage unit fails, When the data transfer is performed again from the internal system device, the second interface circuit is connected to the transmission data storage unit when the monitored total number of write data reaches the data amount requested to be transmitted from the external system device. Data transmission to the unit may be performed.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a block diagram showing an example of a data transfer apparatus according to the first embodiment of the present invention. FIG. 1 shows an example in which an HDD device conforming to the IEEE 1394 standard is connected to a PC conforming to the IEEE 1394 standard, and data is transferred between the PC and the HDD device. Also, the arrows between the blocks shown in FIG. 1 indicate only the data flow.
[0015]
In FIG. 1, a data transfer device 1 is provided in a PC 2 as an IEEE 1394 interface device, and is connected to an HDD device 4 conforming to the IEEE 1394 standard via an IEEE 1394 bus 3. Further, the data transfer apparatus 1 is connected to the chip set 6 via the PCI bus 5 in the PC 2, and the chip set 6 is connected to the CPU 7 and the memory unit 8. The chip set 6 interfaces the PCI bus 5 with the CPU 7 and the memory unit 8. The HDD device 4 constitutes an external system device, and the PCI bus 5, chip set 6, CPU 7 and memory unit 8 constitute an internal system device.
[0016]
On the other hand, the data transfer apparatus 1 includes a LINK / PHY circuit 11 in which a link (LINK) layer and a physical (PHY) layer conforming to the IEEE 1394 standard are formed, a reception FIFO 12, and a reception DMAC (Direct Memory Access Controller). 13, a transmission DMAC 14, a transmission FIFO 15, and a PCI interface control circuit 16 that controls transmission and reception of data between the PCI bus 5. The LINK / PHY circuit 11 is a second interface circuit unit, the PCI interface control circuit 16 is a first interface circuit unit, the transmission DMAC 14 is a control circuit unit, and the transmission FIFO 15 is a transmission data storage unit. Eggplant.
[0017]
The LINK / PHY circuit 11 temporarily stores the data input from the HDD device 4 via the IEEE 1394 bus 3 in the reception FIFO 12, and the reception DMAC 13 reads out the data stored in the reception FIFO 12 (hereinafter referred to as “the reception FIFO 12”). Data reading is referred to as read), and the data is output to the transmission DMAC 14 or the PCI interface control circuit 16 in accordance with the read data. The PCI interface control circuit 16 outputs the input data to the chip set 6 via the PCI bus 5. On the other hand, the transmission DMAC 14 temporarily stores the data input to the PCI interface control circuit 16 in the transmission FIFO 15, and the data stored in the transmission FIFO 15 is transferred to the IEEE 1394 bus 3 via the LINK / PHY circuit 11. Is output.
[0018]
When transferring data between the PC 2 and the HDD device 4, the asynchronous packet is used among the isochronous packet and the asynchronous packet defined in the IEEE1394 standard. Also, among the asynchronous packets, a physical request packet prepared for high-speed data transfer only by hardware without software is transmitted from the HDD device 4 to the PC 2. Then, the data transfer device 1 in the PC 2 performs processing on the received physical request packet, and then transmits a physical response packet to the HDD device 4.
[0019]
The data flow in the data transfer apparatus 1 in such a case will be described in more detail. First, a physical request packet is transmitted from the HDD device 4 to the PC 2 via the IEEE 1394 bus 3. The physical request packet is stored in the receiving FIFO 12 via the LINK / PHY circuit 11. Then, the reception DMAC 13 reads the physical request packet from the reception FIFO 12, and when it determines that the read packet is not a simple asynchronous packet but a physical packet, transfers the packet to the transmission DMAC.
[0020]
Next, the transmission DMAC 14 reads desired data from the memory unit 8 via the chip set 6 connected to the PCI bus 5 and stores it in the transmission FIFO 15 according to the contents of the input packet. When the predetermined data is read from the memory unit 8 via the PCI bus 5 and the physical response packet is prepared for the number of register values incorporated in the transmission DMAC 14 in the transmission FIFO 15, the transmission DMAC 14 The control signal indicating that the / PHY circuit 11 is ready for transmission is enabled, and the physical response packet is transmitted from the LINK / PHY circuit 11 to the HDD device 4 via the IEEE 1394 bus 3.
[0021]
On the other hand, when the internal data of the memory unit 8 is read using the PCI bus 5, the time required for data reading is momentarily depending on the availability of the PCI bus 5 and whether or not data is prepared in the memory unit 8. And change. The transmission DMAC 14 determines the change from a signal indicating the state of the PCI bus 5 and changes the value of a built-in register (not shown). For example, if the PCI bus 5 is not available and data cannot be read, the register value is increased. If the PCI bus 5 is available and data can be read smoothly, the register value is decreased.
[0022]
By doing so, the start time of the C period shown in FIG. 16 is automatically changed according to the data read status via the PCI bus 5, and the state shown in FIG. be able to. In addition to starting transmission of a physical response packet in response to a received physical request packet at an optimal time, it can also be used to start transmission of a simple asynchronous packet at an optimal time.
[0023]
Here, FIG. 2 is a diagram illustrating a schematic configuration example of a packet of the IEEE 1394 standard. As shown in FIG. 2, an IEEE 1394 packet includes a header part including information such as packet type and address, which is composed of 32 bits and 1 word, and data composed of 1 word and 32 bits and less than 2048 words. It is roughly divided into the data part that contains. Further, there is a packet having no data part depending on the type of packet.
[0024]
The transmission DMAC 14 uses data called a descriptor similar to a program for creating a transmission packet. FIG. 3 is a diagram showing a schematic configuration example of such a descriptor. As shown in FIG. 3, the descriptor is composed of a maximum of 8 words with 1 word of 32 bits and 4 words as one basic unit. In the descriptors Descriptor 0 to Descriptor 3, a control part containing a descriptor type, a memory address for creating a data portion, a next descriptor memory address, and the like is written in the transmission FIFO 15 in the descriptor Descriptors 4 to 7 (hereinafter referred to as “descriptor”). The data of the header part of the transmission packet is stored.
[0025]
Next, FIG. 4 is a block diagram showing a configuration example of the transmission DMAC 14. As shown in FIG. 4, the transmission DMAC 14 includes a descriptor 21 that is a program for creating a transmission packet or a register 21 that stores the physical read request packet as described above, and the register 21 includes 32 bits × 8 words. It consists of registers. The physical read request packet is input from the receiving DMAC 13 from the data bus REQD [31: 0], and the descriptor is read from the PCI master controller (not shown) in the PCI interface control circuit 16 by the read data bus MD [31: 0]. ] Is input.
[0026]
In addition, the transmission DMAC 14 includes a multiplexer (MUX) 22, and the multiplexer 22 transmits the header data in the transmission packet input from the register 21 or the transmission data input from the read data bus MD [31: 0]. One of the data in the data portion in the trusted packet is exclusively selected and output to the transmission FIFO 15 via the data bus FD [31: 0]. Further, the transmission DMAC 14 includes a timing control circuit unit 23 that creates all timing control signals in the transmission DMAC 14. A signal REQWRB indicating the data write period of the physical read request packet is input from the receiving DMAC 13 to the timing control circuit unit 23.
[0027]
The timing control circuit unit 23 sends the PCI master controller an address to the PCI master controller to the data bus MA [31: 0], and data indicating a data length value of the read request to the data bus ML [15: 0]. , A signal MREQ indicating the start of a read request and a signal MRDB indicating reading data are output. The signal MREQ is active at a high level, and the signal MRDB is active at a low level.
[0028]
The timing control circuit unit 23 receives a signal MEMP indicating that there is no read data in a FIFO (not shown) in the PCI master controller. The timing control circuit unit 23 is connected to an input / output data bus SD [31: 0] connected to a PCI slave controller (not shown) in the PCI interface control circuit 16, and a write request from the PCI slave controller. The signal SWRB is input, and writing to the start register 31 in the timing control circuit unit 23 is realized.
[0029]
The timing control circuit unit 23 receives data necessary for performing the timing control from the register 21 via the data bus DD # [31: 0] (# indicates four buses from 0 to 3). Is input. The timing control circuit unit 23 can prepare data in the signal FEOP indicating the final data of the write packet to the transmission FIFO 15, the write request signal FWRB to the transmission FIFO 15, and the transmission FIFO 15, and the LINK / PHY circuit 11 outputs a signal FREQB requesting transmission start.
[0030]
The signal FREQB is output from the comparator 32, and an output data bus DTC [from the data up counter 33 that counts the number of words in which data in the data portion of the transmission packet is written to the transmission FIFO 15 as input is input to the comparator 32. Data from 15: 0] and data from data bus DL [15: 0] for transmitting the requested number of bytes data from data bus DD # [31: 0] are respectively input.
[0031]
Further, the data output from the externally settable start register 31 via the output data bus STV [15: 0] is automatically supplied to the comparator 32 from the signals PIRDYB and PTRDYB by the arithmetic circuit 34 to the optimum value. The changed data is input via the data bus CSTV [15: 0]. The signal PIRDYB is a signal output from the PCI master controller indicating whether or not the PCI master controller is ready for data transfer. The signal PTRDYB indicates whether or not the memory unit 8 is ready for data transfer. It is a signal output from the chip set 6 shown.
[0032]
The output signal FREQB of the comparator 32 is (data from the data bus DTC [15: 0]) ≧ (data from the data bus DL [15: 0]) and / or (data from the data bus DTC [15: 0]) ) ≧ (data from the data bus CSTV [15: 0]), it is asserted at a low level and a transmission request is made to the transmission FIFO 15. The transmission DMAC 14 automatically changes the transmission start time of the packet according to the processing status of data read from the PCI bus 5 necessary for preparing the response packet.
[0033]
FIG. 5 is a block diagram showing an example of the internal configuration of the arithmetic circuit 34. As shown in FIG. 5, the arithmetic circuit 34 includes a 16-bit register 41, and data is input from a multiplexer (MUX) 42. The multiplexer 42 receives the data bus STV [15: 0] and the addition result output from the adder 43. The multiplexer 42 receives the data bus STV [15: 0] when the signal MREQ is at a high level. When the signal MREQ is at a low level, the output signal of the adder 43 is selected and output. The adder 43 adds the data output from the register 41 via the data bus CSTV [15: 0] and the data output from the multiplexer (MUX) 44 and outputs the result.
[0034]
The signal PIRDYB is input to the inverter 45, and the output signal of the inverter 45 and the output signal of the AND circuit 46 to which the signal PTRDYB is input are input as the select signal of the multiplexer 44. The multiplexer 44 selects and outputs a predetermined value “0004h” when the select signal is at a high level and outputs a predetermined value “0000h” when the select signal is at a low level.
[0035]
Next, FIG. 6 to FIG. 10 show timing examples until the transmission DMAC 14 writes a transmission packet to the transmission FIFO 15 and issues a packet read request to the LINK / PHY circuit 11. The operation of the data transfer apparatus 1 during packet transmission will be described in a little more detail with reference to FIGS.
When transmitting a packet, first, it is necessary to write either a descriptor or a physical read request packet to the register 21 as information for creating a transmission packet.
[0036]
FIG. 6 is a timing chart showing signals for writing the descriptor to the register 21.
In FIG. 6, at timing T2, a signal MREQ indicating a read request to the PCI master controller is asserted at a high level, and is simultaneously stored in a register (not shown) in the timing control circuit unit 23 of FIG. The memory address register value of the descriptor is output to the data bus MA [31: 0], and data “0020h” is output to the data bus ML [15: 0] in order to read 32 bytes of data.
[0037]
When the PCI master controller in the PCI interface control circuit 16 is able to read data from the PCI bus 5, the FIFO (not shown) in the PCI master controller is in an empty state where there is no data to be stored. Therefore, the signal MEMP becomes low level. When the signal MEMP becomes low level, the timing control circuit unit 23 sets the data read request signal MRDB to the PCI master controller to low level. Next, the descriptor data S0 to S7 sequentially read via the read data bus MD [31: 0] are stored in the register 21.
[0038]
Next, FIG. 7 is a timing chart showing the timing for writing the physical read request packet to the register 21.
As shown in FIG. 7, during the period of timings T6 to T9, the signal REQWRB becomes low level from the receiving DMAC 13, the physical read request packets P0 to P3 are read from the data bus REQD [31: 0], and are stored in the register 21. Written. In this way, either the descriptor or the physical read request packet is written to the register 21, and preparation for writing the transmission packet to the transmission FIFO 15 is completed.
[0039]
Next, FIG. 8 is a timing chart showing an example of timing for writing the header part of the transmission packet to the transmission FIFO 15.
FIG. 8 shows that the signal FWRB becomes a low level during the period of the timings T6 to T9 and data is written to the transmission FIFO 15. In this case, the transmission DMAC 14 sets the signal FWRB to a low level and outputs the header data already stored in the register 21 to the data bus FD [31: 0]. Further, since the final data of the packet at this time is not yet written, the signal FEOP remains at the low level. In this way, the transmission DMAC 14 causes the transmission FIFO 15 to write the header portion of the packet.
[0040]
Next, FIG. 9 and FIG. 10 are timings showing examples of timing when the transmission DMAC 14 writes the data part to the transmission FIFO 15 based on the data stored in the register 21 at the timing of FIG. 6 or FIG. It is a chart. The signals PFRMB, PIRDYB, PTRDYB, PSTOPB and the data bus PAD [31: 0] shown in FIGS. 9 and 10 are signals connected to the PCI bus 5. Further, in the terms “initiator” and “target” used in the PCI standard, only the data read from the PCI bus 5 is described here, so that the initiator is the data transfer device 1 and the target is the memory unit 8.
[0041]
9 and 10, a signal PFRMB is a signal indicating whether the bus cycle of the PCI bus 5 is being executed, and is output from the chip set 6. The signal PSTOPB is a signal asserted by the chipset 6 when the target requests the initiator to cancel the transaction currently being executed. The data bus PAD [31: 0] is an address on the PCI bus 5. And data input / output bus.
[0042]
In FIG. 9, at timing T1, the transmission DMAC 14 raises the signal MREQ to a high level and makes a read request to the PCI master controller. At the same time, the transmission DMAC 14 prepares the memory address data MSA on the data bus MA [31: 0], or the data “0030h” on the data bus ML [15: 0] when preparing data of “30h” bytes, for example. "Is output respectively. In response to this, the PCI master controller asserts the signal PFRMB at the low level from timing T2, and outputs the memory address data MSA for the memory unit 8 to the data bus PAD [31: 0].
[0043]
Next, the PCI master controller asserts the signal PIRDYB at a low level from the timing T3 to inform the chip set 6 that data reading is possible. The chip set 6 asserts the signal PTRDYB at the low level from timing T4 to indicate that data transmission is possible, and at the same time, sequentially outputs data to the data bus PAD [31: 0]. At timing T10, the signal PSTOPB is asserted at the low level by the chip set 6 to request to stop the data transfer, and the signal PTRDYB is deasserted at the high level by the chip set 6 from the timing T11. The PCI master controller deasserts the signal PFRMB at the timing T11 and the signal PIRDYB at the timing T12, and interrupts the data transfer.
[0044]
However, since the read request from the transmission DMAC 14 to the PCI master controller is “30h” bytes, the PCI master controller makes a read request by asserting the signal PFRMB again at the low level from timing T13, and at timing T13. The address “MSA + 1Ch” following the previous data read is output to the data bus PAD [31: 0].
[0045]
The chip set 6 asserts the signal PTRDYB at a low level at timing T15, and sequentially outputs data from the memory unit 8 to the data bus PAD [31: 0] at timings T15 to T19. Further, since the data read of the total “30h” bytes is completed at the timing T19, the PCI master controller deasserts the signal PFRMB to high level and notifies the chip set 6 of the end of the transaction. The signals PIRDYB and PTRDYB are respectively deasserted at a high level from the timing T20.
[0046]
For this reason, at time T5 to T11 and time T16 to T20, the signal MEMP input from the PCI master controller to the transmission DMAC 14 becomes low level. Therefore, the transmission DMAC 14 sets the signals MRDB and FWRB to the low level at timing T5, sequentially writes the data to the transmission FIFO 15, and sets the signal FEOP to the high level because it is the final data at timing T20. Data is written.
[0047]
The data from the data bus DTC [15: 0] indicating the number of bytes written to the transmission FIFO 15 is set to data “0h” at the data write start timing at timing T2, and then the data is stored in the transmission FIFO 15. Each time it is written, it is incremented by 4. When the data output from the start register 31 to the data bus STV [15: 0] is “14h”, the arithmetic circuit 34 transfers the data bus STV [15: 0] to the data bus CSTV [15: 0] at the timing T2. ] Data “14h” is output.
[0048]
When the signal PIRDYB is at the low level and the signal PTRDYB is at the high level and the timing indicates a period in which data is to be read but no data comes from the target side, that is, at the timings T3 and T14, the data "0004h" ”Is output, and the data on the data bus CSTV [15: 0] is incremented by 4 by the adder 43. At timing T11, since the comparison result of the comparator 32 in FIG. 4 changes, the signal FREQB becomes low level and is asserted at timing T12, and a packet read request is made to the LINK / PHY circuit 11.
[0049]
Although the timing example is the same as that in FIG. 9, the signal PIRDYB is at a low level and the signal PTRDYB is at a high level, and the timing indicating a period in which data is read but no data comes from the target side is longer than that in FIG. 9. An example of this is shown in FIG.
As shown in FIG. 10, there is a period in which the data does not come at timings T3, T4, T14, and T15. At these times, the data on the data bus CSTV [15: 0] is sequentially incremented by four. Further, since the comparison result of the comparator 32 of FIG. 4 changes at timing T20, the signal FREQB is asserted at a low level at timing T21, and a packet read request is made to the LINK / PHY circuit 11.
[0050]
As described above, the data transfer apparatus according to the first embodiment has a lower data transfer capability to the target PCI bus 5 in FIG. 10 than in FIG. 9, and in FIG. 9, the “18h” byte of the data portion. In FIG. 10, the transmission DMAC 14 makes a packet read request to the LINK / PHY circuit 11 when the data of “24h” byte is prepared. From this, it is possible to automatically change the transmission packet read request timing in accordance with the target state and transfer capability in the PCI bus 5 transaction.
[0051]
Second embodiment.
FIG. 11 is a diagram illustrating a configuration example of an arithmetic circuit of the data transfer device according to the second embodiment of the present invention. In the block diagram showing an example of the data transfer apparatus according to the second embodiment of the present invention, the transmission DMAC 14 in FIG. 1 is changed to the transmission DMAC 14a, and the data transfer apparatus 1 in FIG. 1 is changed to the data transfer apparatus 1a. Other than that is the same as FIG. The block diagram showing the configuration example of the transmission DMAC 14a is the same as FIG. 4 except that the timing control circuit unit 23a of FIG. In FIG. 11, the same components as those in FIG. 5 are denoted by the same reference numerals. The transmission DMAC 14a constitutes a control circuit unit.
[0052]
As shown in FIG. 11, the arithmetic circuit 34 a includes a 16-bit register 41, and data is input from the multiplexer 42. The multiplexer 42 receives data from the data bus STV [15: 0] and the addition result output from the adder 43. The multiplexer 42 selects the data from the data bus STV [15: 0] by the OR circuit 52 when the signal MREQ is at a high level or when the comparison result of the comparator 51 is at a high level. The data output from 43 is selected. The comparator 51 compares the data from the data bus STV [15: 0] with the data output from the adder 43, and the data from the data bus STV [15: 0] is output from the adder 43. If it is smaller than that, a high level signal is output, otherwise a low level signal is output.
[0053]
The adder 43 adds the data output from the register 41 via the data bus CSTV [15: 0] and the data output from the multiplexer 44 and outputs the result. The output signal of the NOR circuit 53 input to the input terminals corresponding to the signals PIRDYB and PTRDYB is input as the select signal of the multiplexer 44. The multiplexer 44 selects and outputs a predetermined value “FFFCh” when the select signal is at a high level, and selects a predetermined value “0004h” when the select signal is at a low level.
[0054]
In such a configuration, FIG. 12 is a timing chart showing an example of timing from when the transmission DMAC 14 a writes a transmission packet to the transmission FIFO 15 and issues a packet read request to the LINK / PHY circuit 11.
FIG. 12 is almost the same as the timing shown in FIG. 10 except that the data from the data bus STV [15: 0] is “1Ch” and the data bus CSTV [15 : The data from 0] is different. The data from the data bus CSTV [15: 0] is set to “1Ch” which is the value of the data bus STV [15: 0] at the timing T2, and then the data is actually transferred on the PCI bus 5. It is decremented by 4 at T5 to T10 and at timings T16 to T21, and is incremented by 4 at other timings when data transfer is not executed.
[0055]
However, at timing T9 to T11 and timing T22, the output of the comparator 51 becomes high level, so that the multiplexer 42 selects data from the data bus STV [15: 0], and the data bus CSTV [15: 0] from the register 41. The data output to the data “1Ch” from the data bus STV [15: 0] remains as it is. Since the comparison result of the comparator 32 of FIG. 4 changes at timing T20, the signal FREQB is asserted at a low level at timing T21, and a packet read request is output from the transmission DMAC 14a to the LINK / PHY circuit 11.
By doing so, the data transfer apparatus according to the second embodiment can obtain the same effects as those of the first embodiment.
[0056]
Third embodiment.
FIG. 13 is a diagram illustrating a configuration example of the transmission DMAC of the data transfer apparatus according to the third embodiment of the present invention. In the block diagram showing an example of the data transfer apparatus according to the third embodiment of the present invention, the transmission DMAC 14 in FIG. 1 is changed to the transmission DMAC 14b, and the data transfer apparatus 1 in FIG. 1 is changed to the data transfer apparatus 1b. Other than that is the same as FIG. In FIG. 13, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 4 are described. The transmission DMAC 14b forms a control circuit unit.
[0057]
13 differs from FIG. 4 in that a multiplexer (MUX) 61, a D-type flip-flop 62, an AND circuit 63, and an inverter 64 are added. Accordingly, the transmission DMAC 14 of FIG. 4 is replaced with the transmission DMAC 14b. It is in that.
In FIG. 13, the inverter 64 starts to transmit the data prepared in the transmission FIFO 15 from the LINK / PHY circuit 11 to the IEEE 1394 bus 3, but the data preparation in the transmission FIFO 15 is not in time and a transmission packet is received. A signal UNDERTM which becomes high level when a data error occurs is input from the transmission FIFO 15.
[0058]
The multiplexer 61 receives data from the data bus DL [15: 0] and data from the data bus CSTV [15: 0]. The multiplexer 61 compares either the data from the data bus DL [15: 0] or the data from the data bus CSTV [15: 0] according to the output signal from the output terminal QB of the D-type flip-flop 62. Output to 32 corresponding input terminals. The power supply voltage VDD is input to the D input terminal of the D flip-flop 62, and the output signal of the inverter 64 is input to the reset terminal RB. The output signal of the AND circuit 63 is input to the clock signal input terminal of the D-type flip-flop 62, and the signal output from the D-type flip-flop 62 and the signal FREQB correspond to each input terminal of the AND circuit 63. Have been entered.
[0059]
In such a configuration, FIG. 14 is a timing chart showing a timing example of each signal of FIG. In FIG. 14, the packet is written to the transmission FIFO 15 at timings T1 to T6 and timings T8 to T13. At timing T3, the signal FREQB is asserted at a low level, and packet transmission from the transmission FIFO 15 to the IEEE 1394 bus 3 is started via the LINK / PHY circuit 11, but data to the transmission FIFO 15 is transmitted at timing T5. The preparation is not in time and the signal UNDERTM goes high. Accordingly, the output terminal QB of the D-type flip-flop 62 rises to a high level at timing T5. Therefore, the multiplexer 61 selects data from the data bus DL [15: 0] and outputs the data to the corresponding input terminal of the comparator 32 via the data bus NSTV [15: 0].
[0060]
Therefore, the comparator 32 compares the data from the data bus DTC [15: 0] with the data from the data bus DL [15: 0]. For this reason, a transmission request for the next packet in which a data error has occurred is always made only when data is prepared in the transmission FIFO 15. However, once the packet is transmitted securely, the output terminal of the AND circuit 63 rises from the low level to the high level at timing T18, and the output terminal QB of the D-type flip-flop 62 becomes the low level.
[0061]
Therefore, the multiplexer 61 selects and outputs data from the data bus CSTV [15: 0], and the comparator 32 outputs the data bus DTC [15: 0], the data bus DL [15: 0], and the data bus CSTV. A signal FREQB indicating the result of comparison of each data from [15: 0] is output. Therefore, the timing for starting data transfer from the transmission FIFO 15 to the LINK / PHY circuit 11 is the timing at which the function of the arithmetic circuit 34 is activated.
[0062]
As described above, the data transfer apparatus according to the third embodiment can obtain the same effects as those of the first embodiment, and when a data error occurs during packet transmission, Since the next transmission packet can be transmitted reliably, the stability on the system can be improved.
[0063]
In each of the first to third embodiments, the signal having a B at the end of the code, the signal input terminal and the signal output terminal are active at a low level, and the code has a B at the end. No signal, signal input end, and signal output end indicate that they are active at a high level, respectively.
[0064]
【The invention's effect】
As is apparent from the above description, the data transfer device of the present invention. And its operation control method According to the above, in order to improve the processing capability of the data transfer device, even when the packet transmission timing is advanced, the transmission start timing is automatically changed according to the state of the internal system device for preparing the transmission data Therefore, it is possible to reduce the occurrence of transmission packets causing data errors, and to further improve the data transfer processing capability. In addition, if the transmission packet has a data error when the transmission start timing is advanced in order to improve the data transfer processing capability, when retransmitting the transmission packet having the data error, a process for increasing the transmission start timing is performed. By invalidating the data, reliable data transfer is possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a data transfer apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a schematic configuration of an IEEE 1394 standard packet.
FIG. 3 is a diagram illustrating a schematic configuration example of a descriptor.
4 is a block diagram showing a configuration example of a transmission DMAC 14 in FIG. 1. FIG.
5 is a block diagram showing an example of an internal configuration of an arithmetic circuit 34 in FIG. 4. FIG.
FIG. 6 is a timing chart showing signals for writing a descriptor to the register 21;
FIG. 7 is a timing chart showing timing for writing a physical read request packet to a register 21;
FIG. 8 is a timing chart showing an example of timing for writing a header part of a transmission packet to a transmission FIFO 15;
9 is a timing chart showing an example of the timing of each signal shown in FIGS. 4 and 5 when a data part is written in the transmission FIFO 15. FIG.
10 is a timing chart showing another timing example of each signal shown in FIG. 4 and FIG. 5 when a data part is written in the transmission FIFO 15. FIG.
FIG. 11 is a diagram illustrating a configuration example of an arithmetic circuit of a data transfer device according to a second embodiment of the present invention.
12 is a timing chart showing an example of the timing of each signal until a transmission packet is written in the transmission FIFO 15 and a packet read request is issued to the LINK / PHY circuit 11. FIG.
FIG. 13 is a diagram illustrating a configuration example of a transmission DMAC of a data transfer apparatus according to a third embodiment of the present invention.
14 is a timing chart showing an example timing of each signal in FIG. 13;
FIG. 15 is a diagram showing an example of a schematic timing in the data flow in the IEEE 1394 bus and the PCI bus.
FIG. 16 is a diagram showing another schematic timing example of the data flow in the IEEE 1394 bus and the PCI bus.
FIG. 17 is a diagram showing another schematic timing example of the data flow in the IEEE 1394 bus and the PCI bus.
[Explanation of symbols]
1, 1a, 1b Data transfer device
2 PC
3 IEEE1394 bus
4 HDD device
5 PCI bus
6 Chipset
7 CPU
8 Memory part
11 LINK / PHY circuit
12 Receive FIFO
13 DMAC for reception
14, 14b DMAC for transmission
15 FIFO for transmission
16 Interface control circuit
21,41 registers
22, 42, 44, 61 Multiplexer
23, 23b Timing control circuit section
31 Start register
32,51 comparator
33 Data up counter
34, 34a arithmetic circuit
43 Adder
45, 64 inverter
46, 63 AND circuit
52 OR circuit
53 NOR circuit
62 D-type flip-flop

Claims (8)

In a data transfer device that transfers data between an external system device and an internal system device,
A first interface circuit unit for interfacing with the internal system device;
A second interface circuit unit for interfacing with the external system device;
Data input from the internal system device via the first interface circuit unit is temporarily stored, and the stored data is stored via the second interface circuit unit in response to the input control signal. A data storage unit for transmission to be transmitted to the device;
The total number of write data stored in the transmission data storage unit is monitored. When the monitored total number of write data exceeds a predetermined value, the write data stored in the transmission data storage unit is sent to the second interface circuit unit. A control circuit unit for controlling the operation of the transmission data storage unit,
With
In the period before the total number of monitored write data reaches a predetermined value, the control circuit unit receives a signal indicating that data transfer is possible from the first interface circuit unit and can not transfer data. A period in which a signal indicating a state is input from the internal system device, the predetermined value is incremented so that the period corresponds to the count time of the write data, and the total number of the monitored write data is When the amount is less than the predetermined value and less than the amount of data requested by the external system device, the transmission data storage unit is prohibited from transmitting data to the second interface circuit unit. A data transfer device. The control circuit unit adds a preset value to the predetermined value while a signal indicating that data transfer is impossible is input from the internal system device. Item 4. The data transfer device according to Item 1. The control circuit unit stops adding the preset value to the predetermined value while a signal indicating that data transfer is possible is input from the internal system device. The data transfer device according to claim 2. When the control circuit unit is transmitting data from the transmission data storage unit to the second interface circuit unit, data transmission from the internal system device is not in time, and data transmission from the transmission data storage unit fails Then, when data transfer is performed again from the internal system device, if the total amount of the monitored write data reaches the data amount requested to be transmitted from the external system device, the second data is stored in the second data storage unit. 4. The data transfer apparatus according to claim 1, wherein the data transfer apparatus is configured to transmit data to the interface circuit unit. A first interface circuit unit for interfacing with an internal system device;
A second interface circuit unit for interfacing with an external system device;
Data input from the internal system device via the first interface circuit unit is temporarily stored, and the stored data is stored via the second interface circuit unit in response to the input control signal. In an operation control method of a data transfer device that includes a data storage unit for transmission to be transmitted to the device and performs data transfer between the external system device and the internal system device,
Monitor the total number of write data stored in the transmission data storage unit,
In the period before the total number of monitored write data reaches a predetermined value,
Monitoring a period in which a signal indicating that data transfer is possible is input from the first interface circuit unit and a signal indicating that data transfer is not possible is input from the internal system device;
The said period is incremented the predetermined value so as to correspond to the counting time of the write data,
When the total number of monitored write data is less than the predetermined value and less than the amount of data requested for transmission from the external system device, the transmission data storage unit is connected to the second interface circuit unit. An operation control method for a data transfer apparatus, wherein data transmission is prohibited.   6. The data transfer according to claim 5, wherein a preset value is added to the predetermined value while a signal indicating that data transfer is impossible is input from the internal system device. Device operation control method.   7. The addition of the preset value to the predetermined value is stopped while a signal indicating that data transfer is possible is input from the internal system device. Control method of the data transfer apparatus of the present invention. When transmitting data from the transmission data storage unit to the second interface circuit unit, if the data transmission from the internal system device is not in time and data transmission from the transmission data storage unit fails, the internal system When the data transfer is performed again from the device and the total number of the monitored write data reaches the amount of data requested to be transmitted from the external system device, the transmission data storage unit is sent to the second interface circuit unit. 8. The method for controlling operation of a data transfer apparatus according to claim 5, 6 or 7, wherein the data transmission is performed.

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