JPH08129362A - Image data line driving circuit for active matrix type liquid crystal - Google Patents

Abstract

PURPOSE: To decrease the number of 2<n> value switches while preventing the deterioration of picture quality in an active matrix type liquid crystal driving circuit. CONSTITUTION: A driving switch connected to a liquid crystal cell belonging to the respective display groups R, G, B of driving switch group 6R1 , 6G1 , 6B1 ,..., 6Rm , 6Gm , 6Bm is successively turned on for every display group (e.g. 6R1 -6Rm , 6G1 -6Gm , 6B1 -6Bm ). When a driving switch complied with some display group is turned on, a gradation voltage selecting circuit selects either of the relevant gradation voltages V1, V2,..., V2<n> based on a gradation instructing signal and outputs it to a liquid crystal cell through a driving switch being turned on. Consequently, the gradation voltage selecting circuit and the driving switch of the driving switch group give the instructed gradation to the liquid crystal cell for every display groups R, G, B cooperatively and successively selected and display the image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display, and more particularly to an image data driving circuit of an active matrix type liquid crystal display.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional example of an image data line driving circuit (hereinafter abbreviated as a driving circuit) of an active matrix type liquid crystal display device of this kind.
FIG. 7A is a circuit diagram showing the 2 ⁿ value switch used in FIG. 6, and FIG. 7B is a diagram showing an equivalent circuit of each switch of FIG. 7A. In this case, a total of 3 m output terminals S _{R1 to} S _R corresponding to the colors R, G, and B, respectively, are provided.
3 connected to _Bm via image data lines
It is intended to drive each of the m liquid crystal cells by giving 2 ⁿ gradations.

A chip selector 51 sequentially selects and drives a plurality of sets of drive circuits (only one set is shown in FIG. 6 for easy understanding). Shift register 52
Are selected by the chip selector 51 and sequentially drive the registers of the n × 3 m bit register 53. The n × 3 m-bit register 53 supplies each R,
The gradation data D _{R1 to} D _Rn , D _{G1 to} D _Gn , for the sets G and B
D _{B1 to} D _Bn are input and sequentially passed to the n × 3 m bit latch 54.

Each of R, G, B of the n × 3 m bit latch 54
Of the 2 ⁿ value switch 55 of the output circuit 55
Passed to _R1 , 55 _G1 , 55 _B1 , ..., 55 _Rm , 55 _Gm , 55 _Bm . 2 ⁿ value switches 55 _R1 , 55 _G1 , 55 _B1,.
55 _Rm, 55 _Gm, 55 _Bm, the voltage V0, based on the grayscale data passed V1, ~, V2 ⁿ selects one of the outputs to the output terminal S _R1 to S _Bm. That is, conventionally, in the case of gradation display of liquid crystal, as shown in FIG. 6, each 2 ⁿ value switch of the output circuit section is arranged so as to drive one image data line L _{R1 to} L _Bm .

[0005]

Each of the above-mentioned 2 ^n- value switches of the output circuit section for displaying the gradation of the liquid crystal is as follows.
Since each of them is arranged so as to drive one image data line, there is a problem that the chip size becomes large. For example, the number of pixels of a liquid crystal display device is usually 640 × 4
00, 1 frame 60 Hz, 1 horizontal period is 1 /
400 × 60 Hz = about 41.7 μsec. The load on the image data line of the active matrix liquid crystal is
Since R = 50 KΩ and C = 50 pF, the time constant τ of the image data line is about ½ × 50 KΩ × 50 pF.
= About 1.25 μsec. Even if the output impedance of the LCD driver is 10KΩ, τ = 40KΩ ×
50 pF × １ ／ × 50 KΩ × 50 pF = 1.75 μs
ec. In order to sufficiently charge and discharge the liquid crystal, a time of about 5τ (99.3%) is sufficient, and therefore a liquid crystal writing time of about 9 μsec is sufficient.
However, the 2 ⁿ value switches are arranged corresponding to one image data line.

In view of the above problems, the present invention can reduce the chip size by driving a plurality of (most preferably a multiple of 3) image data lines in a time division manner without deteriorating the image quality with one output circuit unit. It is an object to provide an image data line driving circuit.

[0007]

An image data line driving circuit according to the present invention includes a plurality of liquid crystal cells which are divided into a plurality of display groups and are driven by active elements to form an image in order to form an image. An image data line is provided at an output section of an active matrix type liquid crystal display device, based on a selection signal for sequentially selecting liquid crystal cells of each display group and a gradation instruction signal for instructing a gradation of each liquid crystal cell. And an image data line driving circuit for driving each liquid crystal cell to have a designated gray scale via the liquid crystal cell. One end of each of the driving switches connected to the liquid crystal cell belongs to each of the display groups. Each of which is selected to form a connection group, and the other end of each drive switch of the same connection group is connected to a common node of the connection group. Based on the selection signal, a liquid crystal cell belonging to a corresponding display group is selected from each connection group and connected to a common node, and a plurality of gradations for supplying a voltage corresponding to each gradation. A voltage supply line is connected to each grayscale voltage supply line and is also connected to a common node of each group of the drive switch group, and the corresponding grayscale voltage supply line is connected to a common node based on the grayscale instruction signal. And a plurality of gray scale voltage selection circuits connected to each.

When driving a liquid crystal cell via the plurality of image data lines, an initialization circuit for setting and initializing the image data lines to or near a liquid crystal common potential during a horizontal blanking period. And a write control circuit for controlling the write time and the write order of each image data line.

Further, each of the gradation voltage selection circuits includes a plurality of selection switches each having one end connected to any one of the gradation voltage supply lines and the other end connected to the common node. 2 ^n- value switches, one of the corresponding selection switches is turned on based on the selection signal, and the number of drive switches forming one connection group of the drive switch group is three. It is preferable that one of each is selected from those connected to the liquid crystal cells belonging to the display groups of the colors R, G, and B.

[0010]

The drive switches connected to the liquid crystal cells belonging to each display group of the drive switch group are sequentially turned on for each display group such as R, G, and B. When a drive switch corresponding to a certain display group is turned on, the gray scale voltage selection circuit selects a corresponding gray scale voltage based on the gray scale instruction signal and supplies the selected gray scale voltage to the liquid crystal cell via the turned on drive switch. Output. Therefore, the gray scale voltage selection circuit and the driving switches of the driving switch group cooperate to display the image by giving the specified gray scale to the liquid crystal cells of the display group sequentially selected.

[0011]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. FIG. 2 is a detailed diagram of an output circuit including the 2 ⁿ value switch and the drive switch in the embodiment of FIG.

This embodiment has a chip selector (not shown),
Through the shift register 2 and the INV circuit 7, gradation data D indicating gradations of colors R, G, and B (display groups may be any other number of groups) as display groups.
_{R1 to} D _Rn , D _{G1 to} D _Gn , and a data register 3 for inputting D _{B1 to} D _Rn , a latch 4 for receiving gradation data from the data register 3, and a gradation voltage V 1 based on the gradation data from the latch 4. V2, ~, and 2 ⁿ values switch circuit 5 to select one of V2 ^n, and a driving switch circuit 6, and an output timing control circuit 8 which controls the on-off timing of the switches.

2ⁿThe value switch circuit 5 has m 2ⁿValue switch
Chi 5₁, ~, 5_mConsisting of 2 eachⁿ Value switch 5₁, ~,
5_mEach include a plurality of switches. 2 eachⁿ Value switch
Switch 5 ₁, ~, 5_mOne end of each switch is connected to a gray scale voltage V1,
V2, V2ⁿAnd the other end is a common node
It is connected to the.

The driving switches 6 _R1 ,
Each of 6 _G1 , 6 _B1 , ..., 6 _Rm , 6 _Gm , 6 _Bm is a recombined number (in this embodiment, one is selected from R, G, and B of colors of three display groups, and a total of three). All drive switches are divided so as to form a connection group, one end of each drive switch belonging to the connection group is connected to a common node of the connection group, and the other end is connected to a liquid crystal cell to be driven to output terminals S _R1 , S respectively. _G1 , S _B1 , ~, S _Rm , S _Gm , S
It is connected via _Bm and the image data line. Also, the initialization switch SW _c1, ~, SW _cm has one end connected to a common node of each drive switch is connected, the other end is connected to the liquid crystal common voltage V _c which is used to initialize the liquid crystal cell I have. In the case of this embodiment, the drive switches 6 _{R 1 to} 6 _Bm are controlled by the output timing control circuit 8. At this time, even when a driver is used in a case where a terminal on the upper side of the panel as shown in FIG. 8 is used or a terminal in a lower side is used, control is performed so that the timing for driving each color is the same. .

The operation of the embodiment shown in FIGS. 1 and 2 will now be described with reference to FIG. 4 (R / L = H: when the upper terminal is used in FIG. 8). The time division timing is controlled by the timing signals SB1 and SB2. Initialization switch SW _c1, ~, SW _cm and driving switch _{6 R1, 6 G1, 6 B1} , ~, 6 Rm, 6 Gm, 6 Bm is the on totally liquid crystal cells are initialized. First driving switch 6 for the color R _R1 ~, 6 _Rm is turned on, the color G, the drive for the B switch 6 _G1, 6 _B1, ~, 6 _Gm, 6 _Bm is turned off, 2 ⁿ value switch 5 _1, -, 5 Each gray scale voltage is applied to each liquid crystal cell for displaying a pixel of color R from _m through drive switches 6 _R1 ,..., 6 _Rm . Next, the drive switches 6 _R1 ,..., 6 _Rm are turned off, and the color R image data line becomes high impedance and holds the applied gradation voltage.

The driving switch 6 _R1, ~, the 6 _Rm is turned off, the driving switch 6 _G1, ~, 6 _Gm is turned on, 2 ⁿ value switch 5 _1, - to display a pixel of the color G from 5 _m Each gradation voltage is applied to each liquid crystal cell via the drive switches _6G1 ,..., _6Gm . Next, drive switch 6 _G1 , ～,
6 _Gm is turned off, and the color G image data line becomes high impedance and holds the applied gradation voltage. The same operation is repeated for the drive switches 6 _B1 to 6 _Bm . That is, all the liquid crystal cells are driven by time division in the order of a display group of liquid crystal cells displaying color R, a display group of liquid crystal cells displaying color G, and a display group of liquid crystal cells displaying color B.

In the case of FIG. 5 (R / L = L: using the lower terminal of FIG. 8), the display order is the color G
, The display group of the liquid crystal cell that displays the color R, and the display group of the liquid crystal cell that displays the color B.

FIG. 3 is a block diagram of a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the 2 ⁿ value switch circuit 5 includes the 2 ⁿ value decoder 15 + the output amplifier 2
This is the configuration of FIG. Normally, a 2 ⁿ value switch has n = 3 to 4. However, if n is 5 or more, the area of the switch becomes large. Therefore, it is more advantageous to adopt a configuration of 2 ⁿ value decoder 15 + output amplifier 25. The operation is similar to that of the embodiment shown in FIG. In the above-described embodiment, there was no problem in the leakage of the image data line, and the load of the liquid crystal cell to be driven was small and there was no problem.

[0019]

The present invention as described in the foregoing, in the arranged image data line driving circuit to the output portion of the active matrix type liquid crystal display device for driving a liquid crystal cell to form a pixel in an active element, 2 ⁿ values By driving a plurality of image data lines in a time-division manner with a single gradation voltage selection circuit such as a switch, it is possible to reduce the number of gradation selection circuits and, consequently, to reduce the chip size of the circuit. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image data line driving circuit of the present invention.

FIG. 2 is a circuit diagram showing a 2 ^n- value switch circuit and a drive switch circuit of the output unit of FIG. 1;

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the embodiment of FIG.

FIG. 5 is a timing chart showing the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7A is a circuit diagram showing a 2 ⁿ value switch.
(B) is a circuit diagram showing each switch of the 2 ⁿ value switch.

FIG. 8 is a diagram showing a color filter array of an LCD panel.

[Explanation of symbols]

Second shift register 3 the data register 4 latches 5 2 ⁿ value switching circuit _{5 1, ~, 5 m 2} n value switch 6 driving switch circuit _{6 R1, 6 G1, 6 B1} , ~, 6 Rm, 6 Gm, 6 Bm drive switch 7 INV circuit 8 outputs a timing control circuit _{S R1, S G1, S B1} , ~, S Rm, S Gm, S Bm output terminal SW _c1, ~, SW _cm initialization switch

Claims (5)

[Claims] 1. An output unit of an active matrix type liquid crystal display device in which a plurality of liquid crystal cells, which are divided into a plurality of display groups and are driven by active elements, are arranged in a matrix to form an image, Based on the selection signal for sequentially selecting the liquid crystal cells of each display group and the gradation designating signal for designating the gradation of each liquid crystal cell, each liquid crystal cell is set to the designated gradation through the image data line. In the image data line driving circuit that is driven so as to form a connection group, one of the display switches belonging to each of the display groups is selected from the drive switches each having one end connected to the liquid crystal cell, and the same connection is formed. Connect the other ends of the drive switches of each group to the common node of the connection group, and belong to the corresponding display group based on the selection signal. Drive switches for selecting the liquid crystal cell from each connection group and connecting to a common node, a plurality of gradation voltage supply lines for supplying voltages corresponding to each gradation, and connection to each gradation voltage supply line And connected to a common node of each group of the drive switch group,
An image data line driving circuit, comprising: a plurality of gradation voltage selection circuits each connecting a corresponding gradation voltage supply line to a common node based on the gradation instruction signal. 2. An initialization circuit for setting an image data line at or near a liquid crystal common potential during a horizontal blanking period when driving a liquid crystal cell via the plurality of image data lines. 2. The image data line driving circuit according to claim 1, comprising: 3. The image data line driving circuit according to claim 1, further comprising a write control circuit that controls a writing time and a writing order of each image data line when driving the liquid crystal cell through the plurality of image data lines. . 4. Each of the gradation voltage selection circuits includes a plurality of selection switches each having one end connected to any one of the gradation voltage supply lines and the other end connected to the common node. 4. The image data line drive circuit according to claim 1, wherein the switch is a 2 ^n- valued switch, and any one of the selection switches is turned on based on the selection signal. 5. The number of drive switches forming one connection group of the drive switch group is three, each of which is selected from those connected to a liquid crystal cell belonging to a color R, G, B display group. 5. The image data line driving circuit according to claim 1, wherein the image data line driving circuit is selected one by one.