JPH0812882B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a standard cell type semiconductor integrated circuit, a plurality of cells corresponding to logic gates are prepared for the purpose of reducing the area of a wiring channel and improving the integration degree of the cells. In a standard cell type semiconductor integrated circuit in which the cells are arranged based on a logic circuit diagram and wiring between the cells is performed, the cells have a first power supply line and a second power supply line provided on the cells. An input / output terminal between the input and output terminals, and connecting the input / output terminals of the plurality of cells extending in a direction parallel to the first and second power supply lines to each other. Wiring formed of the same wiring layer as the power supply line, and the first and second wirings.
A wirable region in which a wire made of a wiring layer different from that of the first and second power supply lines, which connects the input / output terminals of the plurality of cells extending in the direction perpendicular to the power supply line, can be provided. Is configured to have.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit, and more particularly to a standard cell type semiconductor integrated circuit.

2. Description of the Related Art In recent years, the design of integrated circuits has become complicated and long due to the large scale of integrated circuits and the diversification of user needs. Design automation is advancing in response to such a situation, and the standard cell method is drawing attention as a method thereof.

In the standard cell method, cells (functional blocks) corresponding to logic gates are prepared, and cells are automatically wired based on the logic circuit diagram.

It is desired to improve the degree of integration even in such a standard cell system.

[Conventional technology]

In the conventional standard cell system, the cell has a rectangular shape as shown in FIG. 6 (A), and the input / output terminals 10a to 10c are provided on the peripheral portion of the cell 10.

The cells 10 are arranged in a line as shown in FIG. 6 (B), and the wiring between the cells is performed in the wiring channel 12 provided between the cell rows 11.

[Problems to be solved by the invention]

In the conventional standard cell method, the wiring in the cell 10 is prohibited, and even when connecting the input / output terminals between the adjacent cells, the wiring must be performed using the wiring channel 12, and the area occupied by the wiring channel 12 is large. Therefore, the degree of integration is low.

In addition, the wiring as shown in FIG.
In order to provide 13, the cell row 11 must be separated to provide the wiring channel 14, which causes a problem of low integration.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit that reduces the area of a wiring channel and improves the degree of integration of cells.

[Means for solving problems]

The semiconductor integrated circuit of the present invention is a standard cell type semiconductor integrated circuit in which a plurality of cells corresponding to logic gates are prepared, the cells are arranged based on a logic circuit diagram, and wiring between the cells is performed. Of the first power line (2
The plurality of cells (40 to 44) having an input / output terminal between the second power supply line (27) and the second power supply line (27) and extending in a direction parallel to the first and second power supply lines. Of the same wiring layer as the first and second power supply lines, which connect the input / output terminals to each other, and the plurality of cells extending in a direction perpendicular to the first and second power supply lines. Of the first and second power supply lines for connecting the input / output terminals to each other can be provided with a wirable region.

[Operation] In the circuit of the present invention, the input / output terminal of the cell is provided between the first power supply line (26) and the second power supply line (27), and is arranged in a direction parallel to the first and second power supply lines. The input / output terminals of the cells lined up in a line can be connected by a wire made of the same wiring layer as the power supply line, and the input / output terminals of the cells lined up in a direction perpendicular to the first and second power supply lines Since it is possible to connect the wiring composed of a wiring layer different from the power supply line, first, the cells adjacent to each other in the direction parallel to the power supply line are connected by the wiring composed of the same wiring layer as the power key line without intersecting the power supply line, Further, the input / output terminals in the cells adjacent to each other in the direction perpendicular to the power supply line are connected to each other by the wiring made of a wiring layer different from the power supply line, and the wiring channel region is completely unnecessary.

〔Example〕

1 (A) and 1 (B) respectively show a mask pattern and a symbol pattern of an embodiment of a NAND cell of the semiconductor integrated circuit of the present invention.

In FIG. 1 (A), 20 is a P-channel MOS formation portion, 21 is an N-channel MOS formation portion, and when a P-type substrate is used, the P-channel MOS formation portion 20 is an N-well and an N-type substrate. In the case of, the N channel MOS formation part 21 is P
Well.

P ⁺ type diffusion layers 22a, 22b, 22c and N ⁺ are provided in the MOS formation parts 20 and 21, respectively ^.
The type diffusion layers 23a, 23b, 23c are provided, and the gate electrodes 24, 25 made of polysilicon wiring shown in a satin pattern extend substantially in the Y direction. In the vicinity of the ends of the gate electrodes 24, 25, power supply lines 26, 27 for the power supplies V _CC , GND respectively by the first layer metal wiring, which are hatched in the lower right direction with an insulating layer interposed, extend in the X direction. . The power supply lines 26 and 27 are connected to the diffusion layers 22a, 22c and 23a by contact portions 26a, 26b and 27a, respectively. The first-layer metal wiring 28 is connected to the diffusion layers 22b and 23c at contact portions 28a and 28b, respectively.

Further, N ⁺ type diffusion layers 29 and P ⁺ type diffusion layers 30 are formed as contact formation portions of the substrate and the well at the ends of the MOS formation portions 20 and 21, respectively.
Each one is provided. The N ⁺ type diffusion layer 29 has a contact portion 26.
It is connected to the power supply 26 by c and the P ⁺ type diffusion layer 30 is connected to the power supply line 27 by the contact portions 27b and 27c to determine the potentials of the substrate and the well.

As a result, a NAND circuit is formed by two MOS transistors each of the MOS forming units 20 and 21. This NAND circuit uses the contact portions 24a and 25a shown in FIG. 1B as input terminals for the gate electrodes 24 and 25, and the contact portion 28c as output terminal. Fig. 1 (B)
The broken line indicated by indicates a route that can be wired.

Thus, the input terminal and the output terminal are provided in the cell, and the wirable region is provided in the cell.

FIGS. 2A and 2B show mask patterns and symbol patterns of one embodiment of OR and NAND cells of the circuit of the present invention.

In FIG. 2 (A), N ⁺ -type diffusion layer 32a~32d is formed on the P-channel MOS formation portion 30 are P ⁺ -type diffusion layer 33a~33d is formed on the N-channel MOS formation portion 31, The diffusion layers 32a and 32d, 33a are connected to the power supply lines 26, 27, respectively.

The gate electrodes 34, 35, 36 made of polysilicon wiring have contact portions 34a, 35a, 36a, respectively. Also, the first
The layer metal wiring 37 is connected to the diffusion layer 32 by the contact portions 37a and 37b.
The first layer metal wiring 38 is connected to
It is connected to the diffusion layers 33a and 33c by a and 38b.

As a result, the contact portion 34a shown in FIG.
An OR circuit having 35a as an input terminal and a NAND circuit having the contact portion 36a as one input terminal and the output of the OR circuit as the other input are configured, and the contact portion 37c serves as an output terminal of the NAND circuit. The broken line shown in FIG. 2 (B) indicates a route in which wiring is possible.

Also in this case, the input terminal and the output terminal are provided in the cell, and the wirable region is provided in the cell.

3 (A) and 3 (B) show mask patterns and symbol patterns of one embodiment of the cell array of the circuit of the present invention. In the figure, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted.

In the figure, 40, 41, 42 and 43 are inverter cells, and 44 is D
Mold flip-flop cell, 45 is a NAND cell, and 46 is a Noah cell. The P-channel MOS forming portions of the cells 40 to 46 are integrated to form a P-type portion 47, and the N-channel MOS forming portions are integrated to form an N-type portion 48.

The power supply line 26 is connected to each cell 40-by contact parts 26a-26r.
46 connected to the respective P ⁺ -type diffusion layers and the N ⁺ -diffusion layers as the contact formation portions, and the power supply line 27 is connected by the contact portions 27a to 27r to the N ⁺ -type diffusion layers and the contact formation portions of the respective cells 40 to 46. It is connected to the P ⁺ diffusion layer.

On the inverter cell 40, a second-layer metal wiring 50, which is hatched to the right, extends and is provided in the X direction. The second-layer metal wiring 50 is connected to the first-layer metal wiring 51 at the contact portion 50a. The gate electrode 52 of the cell 40 is formed by the contact portion 51a.
And is routed to the cell 41 and connected to the gate electrode 53 by the contact portion 51b. As a result, the cells 40 and 41 are respectively connected to the second-layer metal wiring by the cells 4 to be described later.
The incoming signal is supplied from 4.

First layer metal wiring 54 for extracting the output of the inverter cell 40
Is connected to the second layer metal wiring 55 by the contact portion 55a and is drawn out from the cell 40. Similarly inverter cell
The first layer metal wiring 56 of 41 is connected to the second layer metal wiring 57, and the output of the cell 41 is extracted.

The first-layer metal wiring 58 is connected to the cell 42 by the contact portion 58a.
The first-layer metal wiring 61, which is connected to the gate electrode 59 of the cell 42 and takes out the output of the cell 42, is connected to the second-layer metal wiring 62 and is drawn out. Similarly, the first layer metal wiring 63 is connected to the gate electrode 64 of the cell 43, and the first layer metal wiring 65 for taking out the output of the cell 43 is connected from the first layer metal wiring 60 to the gate electrode 66 of the cell 44. Cell 43 connected to the second layer metal wiring 67
Is more drawn.

The cell 44 includes a clocked inverter formed by the gate electrodes 66, 68a, 68b and its associated diffusion layer, a high resistance inverter formed by the gate electrode 69 and its associated diffusion layer, and a latch loop together with this inverter. A D-type flip-flop is formed by the formed gate electrode 70 and the inverter formed by the diffusion layer accompanying it.

The signal output from the cell 43 is supplied to the gate electrode 66 as a data input. The second layer metal wiring 72 is the first layer metal wiring
It is connected to the gate electrode 68a via 73, and the clock input CX is supplied from here. The second layer metal wiring 74 is connected to the gate 68b through the first layer metal wiring 75, and the clock input C is supplied from this. The Q output of the D-type flip-flop is taken out from the first layer metal wiring 76. The first-layer metal wiring 77 is connected to the first-layer metal wiring 76. The first-layer metal wiring 77 extends from the lower side in the Y direction to the left side in the X direction, and the second-layer metal wiring 77 is formed by the contact portion 50b. It is connected to the wiring 50.

In the cell 45, the second layer metal wiring 78,7 from which a signal comes in
9 are gate electrodes 2 via the first layer metal wiring 80, 81 respectively
First-layer metal wiring 28 connected to each of 4 and 25 to take output
The first-layer metal wiring 82 is connected to and drawn out in the X direction, and the second-layer metal wiring 83 is connected by the contact portion 83a.
And is drawn out in the Y direction.

Similarly, in the cell 46, the second-layer metal wirings 84, 85 to which a signal comes in are connected to the gate electrodes 88, 89 via the first-layer metal wirings 86, 87, respectively, and the first output is taken out. The first-layer metal wiring 91 is connected and drawn out to the layer-metal wiring 90, and the second-layer metal wiring 92 is connected and drawn out.

Here, a cross section along a straight line passing through the contact portions 28a and 83a of the NAND cell 45 is shown in FIG. Here, on the P-type substrate 93
An N well 94 is formed as the MOS formation portion 20, and 95 is an insulating layer.

In the symbol pattern of FIG. 3 (B), the contact portions 40a, 41a, 42a, 43a, 44a to 44c, 45a, 45b, 46a, 46b are the input terminals for the first layer metal wiring of each cell, and the contact portion 40b, 41b, 42b, 43b, 44d, 45c, 46c are output terminals for the first layer metal wiring of each cell.

Here, the first layer metal wiring 58, 60, 63, 77, which passes through each cell,
82 and 91 extend in the X direction and perform wiring between cells,
Second layer metal wiring 50,55,57,62,67,72,74,78,79,83 to 85,92
Each of them extends in the Y direction for wiring between cells.

Since wiring lines between cells are not required in this way, cells can be spread over each other as shown in FIG. In FIG. 5, cells 100 are arranged in a row to form cell rows 101 to 103, and no wiring channel is provided between the cell rows 101 to 103.

The cells 100 are wired in the X direction and the Y direction by the first layer metal wiring indicated by the broken line and the second metal wiring indicated by the alternate long and short dash line.

In this way, since the wiring channel is not required, the cell integration degree is improved by the amount of the wiring channel.

A wiring channel can be provided between the cell rows 101 to 103 as needed. Also in this case, the area of the wiring channel is greatly reduced as compared with the conventional case.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit of the present invention, the area of the wiring channel can be significantly reduced, the wiring channel can be eliminated and the cells can be spread, and the integration degree of the cells can be improved. The cells adjacent to each other are connected to each other by the wirings in the same wiring layer as the power lines without crossing the power lines, and the input / output terminals in the cells adjacent in the direction perpendicular to the power lines are different from the power layer. Since they are connected by the wiring, the wiring channel region is completely unnecessary, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a diagram showing a mask pattern and a symbol pattern of an embodiment of a NAND cell of a semiconductor integrated circuit of the present invention, FIG. 2 is a diagram showing a mask pattern and a symbol pattern of an OR and NAND cell of the circuit of the present invention, FIG. Is a diagram showing a mask pattern and a symbol pattern of an embodiment of a cell array of the circuit of the present invention, FIG. 4 is a partial sectional view of a NAND cell of FIG. 3, and FIG. 5 is a cell of an embodiment of the circuit of the present invention. FIG. 6 is a diagram showing the arrangement, and FIG. 6 is a diagram for explaining a conventional circuit. In the drawing, 20,30 is a P channel MOS forming portion, 21,31 is an N channel MOS forming portion, 24,25,34 to 36,52,53,59,64,66,68a, 68b, 69,70,88. , 89 are gate electrodes, 26, 27 are power lines, 28, 37, 38, 51, 58, 60, 61, 63, 65, 73, 75 to 77, 82, 90, 91 are first layer metal wiring, 40 To 46 are cells, 40a, 40b, 41a, 41b, 42a, 42b, 43a, 43b, 44a to 44d, 45a to 45c,
46a to 46c are contact portions, and 50, 55, 57, 62, 67, 72, 74, 78, 79, 83 to 85, 92 are second layer metal wirings.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 A

Claims (1)

[Claims] 1. A standard cell type semiconductor integrated circuit in which a plurality of cells corresponding to logic gates are prepared, the cells are arranged based on a logic circuit diagram, and wiring between the cells is performed, wherein the cells are First power line provided on the cell (26)
And a second power supply line (27) with an input / output terminal, and in front of the plurality of cells (40 to 44) extending in a direction parallel to the first and second power supply lines. Wiring in the same wiring layer as the first and second power supply lines for connecting the writing output terminals, and in front of the plurality of cells extending in a direction perpendicular to the first and second power supply lines A semiconductor integrated circuit having a wirable region in which the first output power line and the second power supply line for connecting the writing output terminals to each other can be provided.