JPS6453430A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6453430A
JPS6453430A JP20925887A JP20925887A JPS6453430A JP S6453430 A JPS6453430 A JP S6453430A JP 20925887 A JP20925887 A JP 20925887A JP 20925887 A JP20925887 A JP 20925887A JP S6453430 A JPS6453430 A JP S6453430A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
cell
wiring
wirings
metallic
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20925887A
Other versions
JPH0812882B2 (en )
Inventor
Koichi Konuma
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

PURPOSE:To reduce the areas of wiring channels and to improve the integration degree of cells in a standard cell system by a method wherein input/output terminals and a region where wiring is possible are provided in the interior of each cell. CONSTITUTION:Contact parts 40a, 41a, 42a, 43a, 44a-44c, 45a, 45b, 46a and 46b are input terminals of each cell to first layer metallic wirings and contact parts 40b, 41b, 42b, 43b, 44d, 45c and 46c are output terminals of each cell to the first layer metallic wirings. The first layer metallic wirings 58, 63, 77, 82 and 91, which pass through the interior of each cell, are extendedly provided in an X direction and are wired between the cells and second layer metallic wirings 50, 55, 57, 62, 67, 72, 74, 78, 79, 83-85 and 92 are extendedly provided in a Y direction and are wired between the cells. In such a way, wiring channels are not needed. Thereby, the integration degree of the cells is improved by a space equivalent to the wiring channels.
JP20925887A 1987-08-25 1987-08-25 The semiconductor integrated circuit Expired - Fee Related JPH0812882B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20925887A JPH0812882B2 (en) 1987-08-25 1987-08-25 The semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20925887A JPH0812882B2 (en) 1987-08-25 1987-08-25 The semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6453430A true true JPS6453430A (en) 1989-03-01
JPH0812882B2 JPH0812882B2 (en) 1996-02-07

Family

ID=16569974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20925887A Expired - Fee Related JPH0812882B2 (en) 1987-08-25 1987-08-25 The semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0812882B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405460A2 (en) * 1989-06-26 1991-01-02 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system
JPH0513575A (en) * 1991-07-08 1993-01-22 Nec Corp Integrated circuit wiring design
JPH0745709A (en) * 1993-07-30 1995-02-14 Nec Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60145642A (en) * 1984-01-09 1985-08-01 Toshiba Corp Semiconductor ic device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60145642A (en) * 1984-01-09 1985-08-01 Toshiba Corp Semiconductor ic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405460A2 (en) * 1989-06-26 1991-01-02 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system
JPH0329342A (en) * 1989-06-26 1991-02-07 Toshiba Corp Semiconductor device
US5111271A (en) * 1989-06-26 1992-05-05 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system
JPH0513575A (en) * 1991-07-08 1993-01-22 Nec Corp Integrated circuit wiring design
JPH0745709A (en) * 1993-07-30 1995-02-14 Nec Corp Semiconductor device

Also Published As

Publication number Publication date Type
JP2094805C (en) grant
JPH0812882B2 (en) 1996-02-07 grant

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees