JP2000124318A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of cells exclusively for fixing potentials and make high the density and the integration degree of an LSI by attaching potential fixing terminals to an arbitrary unit cell for an inverter. SOLUTION: Inverter cells 23 as unit cells, first NAND circuit cells, second NAND circuit cells and NOR circuit cells are automatically arranged in a direction X to form logic circuits on a semiconductor substrate. GND terminals and VDD terminals are previously assembled in empty spaces of the inverter cells 23. In such constitution, logic functions of GND circuits are incorporated in p-type well regions 32 of the inverter cells 23 and logic functions of VDD circuits are incorporated in n-type well regions 31 of the inverter cells 23. In other words, a conductive layer 48 connected to a conductive layer 40 through n-type source regions 35 acts on the p-type well regions 321 as terminals for fixing the GND potential, and a conductive layer 50 connected to a conductive layer 38 through p-type source regions 33 acts on the n-type well regions 31 as VDD terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device in which a plurality of unit cells are combined to form a specific logic circuit.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit device is developed, a logic design is performed, and after a circuit design, a layout design is performed. At the time of layout design, laying out individual components such as transistors and capacitors on a semiconductor substrate requires a great deal of labor and time, so a unit cell with a predetermined logic function is used as a standard cell library. Prepared and automatically arranged on a semiconductor substrate by combining a plurality of unit cells necessary to configure a target logic circuit by a computer,
Automatic wiring (hereinafter, referred to as automatic placement and wiring) between cells is performed. Note that the unit cell includes an inverter circuit, a NAND circuit, a NOR circuit, and the like, and is not uniform in size.

Hereinafter, as an example, a description will be given of an example in which a conventional semiconductor integrated circuit device constituting a logic circuit as shown in FIG. The logic circuit shown in the figure has a VDD potential (first logic level potential) 2
And the input terminal 7 are connected to the input side of the first NAND (NA
ND) circuit 4, an input terminal 8 connected to the input side, an inverter 3, and an output terminal 3B of the inverter 3 and a GND potential (second logic level) 1 connected to the input side.
The NAND circuit 5 includes a NOR circuit 6 having an output terminal 9 connected to an input terminal of an output terminal 4C of the first NAND circuit 4 and an output terminal 5C of the second NAND circuit 5.

The computer has a GND terminal corresponding to the GND potential 1, the VDD potential 2, the inverter 3, the first NAND circuit 4, the second NAND circuit 5, and the NOR circuit 6 which constitute the above-described logic circuit in advance. Cell 11, VDD
A terminal cell 12, an inverter cell 13, a first NAND circuit cell 14, a second NAND circuit cell 14B, and a NOR circuit cell 15 are registered as unit cells. Therefore, based on the instructions of the designer, the computer shown in FIG.
Of the cells 11 to 1 so as to constitute a logic circuit of
5 and select X on the semiconductor substrate as shown in FIG.
Automatic placement in the direction. Subsequently, as shown in FIG.
7, the layout design is completed and the semiconductor integrated circuit device is completed.

Here, among the plurality of cells, GN
The D terminal cell 11 has a terminal for fixing (clamping) the GND potential which is the first logic level in the logic circuit, and functions as a GND potential fixing cell. The VDD terminal cell 12 is connected to the second logic level VDD.
A terminal for fixing the D potential is provided, and functions as a VDD potential fixing cell. Both the GND potential fixing cell and the VDD potential fixing cell are often required for a logic circuit based on a binary system.

Next, a specific configuration of each unit cell of the GND terminal cell 11 to the NOR circuit cell 15 will be described.
As shown in FIG. 11, in the GND circuit cell 11, an N-type well region 101 and a P-type well region 102 are formed adjacent to each other in the Y direction, and an N-type diffusion region 103 is formed in the P-type well region 102. Is formed. Then, the N-type diffusion region 1
03 is a conductive layer 10 made of aluminum or the like through contact holes 104 and 105 along the Y direction.
6, 107 (1B) are provided, and one conductive layer 106 is provided.
Is connected to the GND wiring 100 (1A) at the lower end by extension, and the other conductive layer 107 is connected to the GND wiring 100 via the N-type diffusion region 103 and the conductive layer 106.
Functions as the ND terminal 1B. Also, the N-type well region 1
A VDD wiring 110 is provided at the upper end of the reference numeral 01.

As shown in FIG. 12, an N-type well region 111 and a P-type well region 112 are formed adjacent to each other in the Y direction.
Has a P-type diffusion region 113 formed therein. And P
The contact hole 11 along the Y direction is formed in the mold diffusion region 113.
Conductive layers 116 and 117 made of aluminum or the like are provided via
7 is extended and connected to the upper VDD wiring (2B) 110, the other conductive layer 116 is connected to the VDD wiring 110 via the P-type diffusion region 113 and the conductive layer 117, and
Functions as the DD terminal 2B. Also, the P-type well region 1
At the lower end of 12, a GND wiring 100 (2A) is provided.

As shown in FIG. 13, the inverter cell 13 has an N-type well region 121 and a P-type well region 1.
22 are formed adjacent to each other in the Y direction, and the N-type well region 121 has a P-type source region 123 and a drain region 12.
4 is formed, while an N-type source region 125 and a drain region 126 are formed in the P-type well region 122. A conductive layer 128 is provided in the P-type source region 123 via a contact hole 127 and is extended and connected to the VDD wiring 110. A conductive layer 130 is provided in the N-type source region 125 through a contact hole 129,
It is connected to the ND wiring 100. P-type drain region 1
24 and the N-type drain region 126 are provided with contact holes 132 and 133, respectively.
Conductive layer 134 between 2 and 133 (corresponding to output terminal 3B)
Are provided and connected. An intermediate position between the P-type source region 123 and the drain region 124 and the N-type source region 1
A gate electrode 135 is provided so as to straddle an intermediate position between the gate electrode 25 and the drain region 126. Conductive layers 136 and 137 are provided at the upper end of the N-type well region 121 and the lower end of the P-type well region 122, respectively, and a conductive layer 138 (corresponding to the input terminal 3A) is provided at the upper end of the P-type well region 122. Have been. Thereby, the N-type well region 1
A PMOS (Metal Oxide Semiconductor) transistor 140P is formed in 21, while an NMOS transistor 140N is formed in the P-type well region 122. Then, the PMOS transistors 140P and N
C (Compleme) by MOS type transistor 140N
ntary) A MOS type inverter is configured.

The first NAND circuit cell 14A and the second NAND circuit cell 14B have the same configuration. That is, the first and second NAND circuit cells 14A and 14B
As shown in FIGS. 14 and 15, an N-type well region 141 is formed.
A, 141B and P-type well regions 142A, 142B are formed adjacent to each other to form N-type well regions 141A, 141B.
B has P-type source regions 143A, 144A, 143B,
144B and drain regions 145A and 145B are formed. The P-type well regions 142A and 142B have N-type source regions 146A, 147A, 146B and
7B and drain regions 148A and 148B are formed.

[0010] P-type source regions 143A, 144A, 14
3B and 144B have contact holes 150A and 1B, respectively.
51A, 150B, and 151B via the conductive layer 152A,
153A, 152B, and 153B are provided, and all of them are extended and connected to the VDD wiring 110. Contact holes 155A are formed in the N-type source regions 146A and 146B.
Conductive layers 156A and 156B are provided via 155B, and both are connected to the GND wiring 100.

The P-type drain regions 145A and 145B and the N-type source regions 147A and 147B are provided with contact holes 158A, 159A, 158B and 159B, respectively, and the contact holes 158A, 159A and 158B,
A conductive layer 160A (corresponding to the output terminal 4C) and 160B (corresponding to the output terminal 5C) are provided and connected between the conductive layer 160A and the conductive layer 159B. P-type source regions 143A, 144A, 1
43B, 144B and drain regions 145A, 145B
And the N-type source regions 146A, 147A, 1
46B, 147B and drain regions 148A, 148B
Gate electrodes 161 so as to straddle the intermediate position of
A, 162A, 161B and 162B are provided.
Further, the upper ends of the N-type well regions 141A and 141B and P
Conductive layers 163A, 163B and 164A and 164B are provided at the lower ends of the mold well regions 142A and 142B, respectively, and conductive layers 165A (corresponding to the input terminal 4A) and 166A (input terminal) are provided at the upper ends of the P-type well regions 142A and 142B. 4B), 165B (corresponding to the output terminal 5A), and 166B (corresponding to the output terminal 5B). As a result, PMOS transistors are formed in the N-type well regions 141A and 141B, while NMOS transistors are formed in the P-type well regions 142A and 142B.

As shown in FIG. 16, the NOR circuit cell 16 has an N-type well region 171 and a P-type well region 172 formed adjacent to each other in the Y direction, and the N-type well region 171 has a P-type source region. Regions 173, 174 and drain region 17
5, the N-type source region 176, 177 and the drain region 178 are formed in the P-type well region 172. The contact hole 17 is formed in the P-type source region 173.
9, a conductive layer 180 is provided via the VDD wiring 11
It is extended to 0 and connected. N-type source region 176,
177 are provided with conductive layers 183 and 184 via contact holes 181 and 182, respectively, and both are connected to the GND wiring 100. P-type source region 174 and N
Contact holes 18 are formed in the respective drain regions 178.
6, 187 are provided, and each contact hole 186, 187 is provided.
A conductive layer 188 (corresponding to the output terminal 6C) is provided and connected between them.

An intermediate position between the P-type source regions 173 and 174 and the drain region 175 and N-type source regions 176 and
Gate electrodes 190 and 191 are provided to straddle the intermediate position of the drain region 77 and the drain region 178, respectively.
Conductive layers 192 and 193 are provided at the upper end of the N-type well region 171 and the lower end of the P-type well region 172, respectively, and the conductive layer 194 is provided at the upper end of the P-type well region 172.
(Corresponding to the input terminal 6A) and 195 (corresponding to the input terminal 6B). Thereby, the N-type well region 1
A PMOS type transistor is formed in
An NMOS transistor is formed in the mold well region 172.

As described above, the conventional semiconductor integrated circuit device is completed by automatically arranging the GND circuit cell 11 to the NOR circuit cell 15 which are unit cells adjacent to each other in the X direction. Here, the height dimension in the Y direction of the N-type well region and the P-type well region of each unit cell is set to be the same,
The width dimension in the X direction is arbitrarily set according to the function of each unit cell.

[0015]

By the way, in the conventional semiconductor integrated circuit device as described above, every time a logic circuit requiring a predetermined fixed potential is designed, a GND terminal cell or VDD which is a potential fixing cell is required. Since the terminal cells must be laid out on the semiconductor substrate, there is a problem that the area of the semiconductor substrate is occupied by that much, which is an obstacle to improving the degree of integration. That is, in designing the layout of the semiconductor integrated circuit device, the cells for the GND terminal and the cells for the VDD terminal are necessary cells. Therefore, each time a logic cell requiring a predetermined fixed potential is designed, it is placed on the semiconductor substrate adjacent to the cell. Must be laid out.
For example, when designing the layout of a semiconductor integrated circuit device requiring a plurality of logic circuits shown in FIG. 17, one GND terminal cell 11 and one VDD terminal cell 12 shown in FIGS. 11 and 12 are also required. Therefore, the area occupied on the semiconductor substrate by those overlapping cells increases.

In the prior art, when automatic placement and routing is performed using a computer, the VDD terminal and the GND terminal must be provided independently of the power supply wiring and the GND wiring. This is because when a computer executes automatic placement and routing, a predetermined terminal is connected to the other terminal by wiring. For this reason, the predetermined terminal cannot be directly connected to the power supply wiring or the GND wiring by automatic wiring. For this reason, in order to connect a predetermined terminal to a power supply or GND by automatic wiring, it is necessary to provide a VDD terminal or GND terminal independently of the power supply wiring or GND wiring.

The connection pattern must be verified using a computer to verify that the layout pattern automatically arranged and wired matches the designed circuit diagram. In this case, it is necessary to verify each terminal on the circuit diagram in correspondence with each terminal on the layout pattern. However, in general, the power supply wiring and the GND wiring are not recognized as terminals, and thus connection verification cannot be performed. For this reason, in order to verify the connection, it is necessary to set the power supply wiring and the GND wiring as a VDD terminal and a GND terminal independent of these wirings.

Further, when automatic wiring is performed by a computer, it is necessary to minimize the amount of data to be handled and to improve the processing speed of automatic wiring. For example, when a certain output terminal is connected to a certain input terminal, automatic wiring processing can be performed if there is information on these terminals.
However, when an input terminal is connected to a power supply wiring or a GND wiring, it is necessary to take in information on the power supply wiring and the GND wiring in addition to the predetermined terminals into the computer and perform automatic wiring. Since the power supply wiring and the GND wiring are not located at one point as in the case of the terminal but are present on the side of the logic circuit, the data amount is greatly increased. As a result,
There is a problem that the processing speed of the automatic wiring is reduced.

In order to solve this problem, the connection verification computer uses the position information of the VDD terminal or the GND terminal instead of using the wiring information of the power supply wiring and the GND wiring. The VDD terminal and the GND terminal have the same potential as the power supply wiring and the GND wiring, and are positioned as independent terminals. For this reason, the VDD terminal and GND
Terminals and predetermined input terminals can be connected with a minimum amount of information, and automatic placement and routing can be performed at high speed.

The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit device capable of suppressing an increase in the area occupied on a semiconductor substrate by a cell having a potential fixing terminal. It is intended to be.

[0021]

According to a first aspect of the present invention, there is provided a logic circuit in which a plurality of unit cells having a desired logic function are combined and arranged on a semiconductor substrate. A semiconductor integrated circuit device according to the present invention is characterized in that an arbitrary unit cell is provided with a potential fixing terminal.

According to a second aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein the arbitrary unit cell is an inverter cell.

According to a third aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein the arbitrary unit cell is a NAND circuit cell.

According to a fourth aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein the arbitrary unit cell is a NOR circuit cell.

According to a fifth aspect of the present invention, there is provided the semiconductor integrated circuit device according to any one of the first to fourth aspects, wherein the potential fixing terminal is a first or second logic level terminal. Features.

According to a sixth aspect of the present invention, there is provided the semiconductor integrated circuit device according to the fifth aspect, wherein the first or second logic level terminal is connected to a power supply wiring or a G line via a conductive semiconductor region.
It is characterized in that it is connected to an ND wiring.

According to a seventh aspect of the present invention, there is provided the semiconductor integrated circuit device according to any one of the first to fourth aspects, wherein the unit cell outputs the first and second logic levels. It is characterized by having a second potential fixing terminal.

The invention according to claim 8 relates to the semiconductor integrated circuit device according to claim 7, wherein the first and second potential fixing terminals are respectively connected to a power supply wiring and a GND wiring via a conductive type semiconductor region. It is characterized by having.

According to a ninth aspect of the present invention, in the first conductivity type well region, a second conductivity type semiconductor region is formed, and a potential fixing terminal connected to a predetermined potential wiring via the second conductivity type semiconductor region. Is provided.

According to a tenth aspect of the present invention, the first conductivity type well region and the second conductivity type well region are formed adjacent to each other in one direction, and the first conductivity type well region and the second conductivity type well region are formed in the first conductivity type well region and the second conductivity type well region. Are formed with a second conductivity type semiconductor region and a first conductivity type semiconductor region, respectively, and via a first logic level terminal or a first conductivity type semiconductor region connected to a power supply wiring via the second conductivity type semiconductor region. It is characterized in that it has a unit cell provided with at least one logic level terminal of the second logic level terminal connected to the GND wiring, or at least one set of the first logic level terminal and the second logic level terminal.

According to an eleventh aspect of the present invention, there is provided a unit cell in which a first conductivity type well region is formed and a potential fixing terminal connected to a predetermined potential wiring through the first conductivity type semiconductor region is provided. It is characterized by having.

According to a twelfth aspect of the present invention, the first conductivity type well region and the second conductivity type well region are formed adjacent to each other in one direction, and the first conductivity type well region and the second conductivity type well region are formed in the wells. Is a first logic level terminal or a second conductivity type well region semiconductor region in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are respectively formed, and which is connected to a power supply wiring via the first conductivity type semiconductor region. And a unit cell provided with at least one set of a first logic level terminal and a second logic level terminal of one of the second logic level terminals connected to the GND wiring through the first and second logic level terminals. I have.

[0033] The invention according to claim 13 is the invention according to claims 1 to 1
2. The semiconductor integrated circuit device according to any one of the items 2, wherein a wiring is connected from the potential fixing terminal provided in the unit cell to a predetermined terminal.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. First Embodiment FIG. 1 is a plan view showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a plan view showing a configuration of the semiconductor integrated circuit device before wiring is formed, and FIG. FIG. 4 is a plan view showing a unit cell constituting a main part of the semiconductor integrated circuit device, and FIG. 4 is a sectional view taken along the line AA of FIG. As shown in FIG. 1, the semiconductor integrated circuit device of this example has an inverter cell 23 as a unit cell and a first NAND circuit cell 14A as unit cells.
And second NAND circuit cell 14B, NOR circuit cell 15
Are automatically arranged in the X direction on the semiconductor substrate so as to constitute the logic circuit of FIG. Here, in the inverter cell 23, a GND terminal and a VDD terminal are previously incorporated in the empty space. Therefore, only by arranging the inverter cell 23 on the semiconductor substrate, GND
Without placing the terminal cell and the VDD terminal cell,
The logical functions of the GND terminal and the VDD terminal can be obtained.

The inverter cell 23 is frequently used as a unit cell in a general logic circuit, and has a relatively large space.
It is easy to incorporate the ND terminal and the VDD terminal. The first and second NAND circuit cells 14
A, 14B and the NOR circuit cell 15 have the same configurations as those shown in FIGS. 14, 15 and 16, respectively.

As shown in FIGS. 3 and 4, the inverter cell 23 has an N-type well region 31 and a P-type well region 32 formed on a P-type semiconductor substrate 30 adjacent to each other in the Y direction. A P-type source region 33 and a drain region 34 are formed in the P-type well region 31 while the P-type well region 3 is formed.
2, an N-type source region 35 and a drain region 36 are formed. A conductive layer 38 made of aluminum or the like is provided in the P-type source region 33 through a contact hole 37 opened in the interlayer insulating film 41, and is extended and connected to the VDD terminal 110. A conductive layer 40 made of aluminum or the like is provided in the N-type source region 35 through a contact hole 39, and is extended and connected to the GND terminal 100. Contact holes 42 and 43 are provided in the P-type drain region 34 and the N-type drain region 36, respectively.
A conductive layer 44 made of aluminum or the like is provided and connected between the contact holes 42 and 43. A gate electrode 45 made of polysilicon or the like is provided so as to extend between an intermediate position between the P-type source region 33 and the drain region 34 and an intermediate position between the N-type source region 35 and the drain region 36. 200 and 201 are gate oxide films.
Thus, a PMOS transistor 46P is formed in the N-type well region 31, while an NMOS transistor 46N is formed in the P-type well region 32. The PMOS transistor 46P and the NMOS transistor 46N form a CMOS inverter.

Here, a contact hole 47 is provided above the contact hole 39 in the N-type source region 35 of the P-type well region 32 along the Y direction.
Is provided with a conductive layer 48 (corresponding to the GND terminal 1B) made of aluminum or the like. Then, conductive layer 40 that is conductive through conductive layer 48 and N-type source region 35 is formed.
Are extended and connected to the GND wiring 100. Also,
A contact hole 49 is provided below the P-type source region 33 in the N-type well region 31 along the Y direction of the contact hole 37, and a conductive layer 50 made of aluminum or the like is provided in the contact hole 49. . The conductive layer 50 (corresponding to the VDD terminal 2 </ b> B) and the conductive layer 38 conducting through the P-type source region 33 are extended and connected to the VDD wiring 110.

With this configuration, the logic function of the GND circuit is incorporated in the P-type well region 32 of the inverter cell 23, while the logic function of the VDD circuit is incorporated in the N-type well region 31. That is, in the P-type well region 32, the conductive layer 48 connected to the conductive layer 40 through the N-type source region 35 is configured to function as a terminal for fixing the GND potential. In the N-type well region 31, a conductive layer 50 connected to the conductive layer 38 through the P-type source region 33 is configured to function as a terminal for fixing the VDD potential.

Wiring is formed in the inverter cell 23, the first NAND circuit cell 14A, the second NAND circuit cell 14B, and the circuit cell 15 arranged as shown in FIG. 2 as shown in FIG. You. In FIG. 1, a wiring 25 is connected to the GND terminal (conductive layer 48) of the GND circuit 1 (in FIG. 17) of the inverter cell 23 and the second NAND circuit cell 1
4B input terminal of second NAND circuit 5 (conductive layer 166B)
Is connected between. The wiring 26 is connected to the VDD terminal (conductive layer 50) of the VDD circuit 2 of the inverter cell 23,
The first NAND circuit cell 14A is connected between the input terminal (conductive layer 165A) of the first NAND circuit 4 and the first NAND circuit cell 14A. The wiring 27 is connected between the output terminal (conductive layer 133) of the inverter 3 of the inverter cell 23 and the input terminal 5A (corresponding to the conductive layer 165B) of the second NAND circuit 5 of the second NAND circuit cell 14B. Have been. The wiring 28 is connected to the output terminal 4C of the first NAND circuit 4 of the first NAND circuit cell 14A.
(Corresponding to the conductive layer 160A) and the input terminal 6A of the NOR circuit 6 of the NOR circuit cell 16 (corresponding to the conductive layer 194). The wiring 29 is connected to the output terminal 5C of the second NAND circuit 5 of the second NAND circuit cell 14B (corresponding to the conductive layer 160B) and the input terminal 6B of the NOR circuit 6 of the NOR circuit cell 15 (to the conductive layer 195). Equivalent).

As described above, according to the configuration of this example, the inverter cell 23 in which the GND terminal and the VDD terminal are incorporated in an empty space is prepared in advance, and the inverter cell 23 is automatically used at the time of layout design. A logic circuit having a GND terminal and a VDD terminal can be configured by merely arranging it without arranging a cell for a GND terminal and a cell for a VDD terminal on a semiconductor substrate. Therefore, an increase in the area occupied by the cell having the potential fixing terminal on the semiconductor substrate can be suppressed.

Second Embodiment FIG. 5 is a sectional view showing a unit cell constituting a main part of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 6 is a sectional view taken along the line BB of FIG. FIG. The configuration of the semiconductor integrated circuit device of this example is significantly different from the configuration of the first embodiment described above in that the GND terminal and the VDD terminal are incorporated in another area in the inverter cell. In the P-type well region 32 of the inverter cell 23, a pair of P-type diffusion regions 53 and 54 are provided.
Conductive layers 57 and 58 are provided in 3 and 54 via contact holes 55 and 56, respectively. The N-type well region 31 is provided with a pair of N-type diffusion regions 60 and 61, and the N-type diffusion regions 60 and 61 are provided with conductive layers 64 and 65 via contact holes 62 and 63, respectively. ing. That is, the conductive layer 57 and the conductive layer 58 are connected to the P-type well region 32 through the P-type well region 32, and the conductive layer 58 is configured to function as a terminal for fixing the GND potential. I have. In addition, conductive layer 64 and conductive layer 65 are connected to N-type well region 31 through this N-type well region 31, and conductive layer 64 is connected to VDD.
It is configured to function as a terminal for fixing a potential. Except for this, the configuration is substantially the same as that of the above-described first embodiment. Therefore, in FIG. 5, the same components as those in FIG. 3 are denoted by the same reference numerals and description thereof is omitted.

As described above, according to the structure of this embodiment, substantially the same effects as those described in the first embodiment can be obtained. In addition, according to this example, it is effective when applied to the case where the area of the GND region and the VDD cannot be secured due to the small area of the diffusion region.

Third Embodiment FIG. 7 is a sectional view showing a unit cell constituting a main part of a semiconductor integrated circuit device according to a third embodiment of the present invention, and FIG. 8 is a sectional view taken along the line CC of FIG. FIG. The configuration of the semiconductor integrated circuit device of this example is significantly different from the configuration of the first embodiment described above in that the GND terminal and the VDD terminal are incorporated in the NAND circuit cell. As shown in FIGS. 7 and 8, an N-type well region 71A and a P-type well region 72A are formed adjacent to each other, and a P-type source region is formed in the N-type well region 71A. 73
A, 74A and a drain region 75A are formed.
The N-type source region 76 is provided in the P-type well region 72A.
A, 77A and a drain region 78A are formed.

The P-type source regions 73A and 74A are provided with conductive layers 82A and 82A through contact holes 80A and 81A, respectively.
83A are provided, and all are extended and connected to the VDD wiring 110. A conductive layer 86A is provided in the N-type source region 76A via a contact hole 85A, and a GN
It is connected to the D wiring 100. P-type drain region 75
The contact 8 is connected to the A and N type source regions 77A, respectively.
7A and 88A are provided, and each contact hole 87A and 88A is provided.
A conductive layer 89A is provided and connected between A. P
Gate electrodes 90A and 91A are provided so as to straddle an intermediate position between the source regions 73A and 74A and the drain region 75A and an intermediate position between the N-type source regions 76A and 77A and the drain region 78A, respectively.

Here, a contact hole 92A is provided above the contact hole 85A of the N-type source region 76A in the P-type well region 72A along the Y direction, and the contact hole 92A has a conductive layer made of aluminum or the like. 93A
Is provided. The conductive layer 86A that is electrically connected to the conductive layer 93A through the N-type source region 76A is GND.
It is extended and connected to the wiring 100. Further, the contact hole 8 in the P-type source region 73A of the N-type well region 71A is formed.
A contact hole 94A is provided below the 0A in the Y direction, and a conductive layer 95A made of aluminum or the like is provided in the contact hole 94A. A conductive layer 82A that is conductive through the conductive layer 95A and the P-type source region 73A is extended and connected to the VDD wiring 110.

With this configuration, the first NAND circuit cell 2
The logic function of the GND circuit is incorporated in the P-type well region 72A of 4A, while the V-type
The logic function of the DD circuit is incorporated. That is, P
In the mold well region 72A, a conductive layer 93A connected to the conductive layer 86A through the N-type source region 76A is configured to function as a terminal for fixing the GND potential. The N-type well region 71A has a conductive layer 9 connected to the conductive layer 82A through the P-type source region 73A.
5A is configured to function as a terminal for fixing the VDD potential.

Like the inverter cell, the NAND circuit cell 24A is frequently used as a unit cell in a general logic circuit, and has a relatively large space. Therefore, it is easy to incorporate the functions of the GND circuit 1 and the VDD circuit 2 in advance by using the empty space. The inverter cell 1
3. Second NAND circuit cell 14B and NOR circuit cell 1
5 is the same as that shown in FIGS. 13, 15 and 16, respectively.

As described above, according to the structure of this embodiment, substantially the same effects as those described in the first embodiment can be obtained.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there may be changes in the design without departing from the gist of the present invention. Is also included in the present invention. For example, in the case where the logic functions of the GND circuit and the VDD circuit are incorporated in the NAND circuit cell, if a wiring is formed so as to constitute a desired logic circuit, the second NAND circuit cell may be used instead of the first NAND circuit cell. It may be incorporated in the.

As a unit cell incorporating the logic functions of the GND terminal and the VDD terminal, a NOR circuit cell can be used in addition to an inverter cell and a NAND circuit cell. The NOR circuit cell, like the inverter cell and the NAND circuit cell, is frequently used as a unit cell in a general logic circuit and has a relatively large space, so that it can be similarly applied. . Also, V
The unit cell incorporating the DD terminal and the GND terminal can be applied to all of the inverter cell, the NAND circuit cell, and the NOR circuit cell included in the logic circuit, and can be applied in combination. By increasing the types of unit cells in which the VDD terminal and the GND terminal are incorporated, it is possible to use the VDD terminal and the GND terminal in a relatively close place. Further, in each embodiment, the example in which the layout design of the semiconductor integrated circuit device forming the specific logic circuit is described. However, since the logic circuit can be configured in various contents depending on the application, purpose, etc. It can be applied to logic circuits.

[0051]

As described above, according to the configuration of the semiconductor integrated circuit device of the present invention, it is possible to abolish the dedicated cell only for fixing the potential, and accordingly, the effective logic cell can be disposed on the semiconductor substrate. , Which can contribute to high density and high integration of LSI. In addition, when a certain terminal is fixed to the GND potential or the VDD potential, the potential can be fixed to a potential close to the actually used potential because the GND wiring or the VDD wiring is passed through the diffusion region or the well region. Therefore, the error can be reduced when comparing with another output signal using a comparator or when using as an output signal to an analog circuit.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a configuration of the semiconductor integrated circuit device before wiring formation.

FIG. 3 is a plan view showing a unit cell constituting a main part of the semiconductor integrated circuit device.

FIG. 4 is a sectional view taken along the line AA in FIG. 3;

FIG. 5 is a plan view showing a unit cell constituting a main part of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a sectional view taken along the line BB of FIG. 5;

FIG. 7 is a plan view showing a unit cell constituting a main part of a semiconductor integrated circuit device according to a third embodiment of the present invention.

8 is a sectional view taken along the line CC of FIG. 7;

FIG. 9 is a plan view showing a configuration of a conventional semiconductor integrated circuit device.

FIG. 10 is a plan view showing a configuration of the semiconductor integrated circuit device before wiring formation.

FIG. 11 is a plan view showing an example of a unit cell constituting the semiconductor integrated circuit device.

FIG. 12 is a plan view showing an example of a unit cell constituting the semiconductor integrated circuit device.

FIG. 13 is a plan view showing an example of a unit cell constituting the semiconductor integrated circuit device.

FIG. 14 is a plan view showing an example of a unit cell constituting the semiconductor integrated circuit device.

FIG. 15 is a plan view showing an example of a unit cell constituting the semiconductor integrated circuit device.

FIG. 16 is a plan view showing an example of a unit cell constituting the semiconductor integrated circuit device.

FIG. 17 is an example of a logic circuit included in the semiconductor integrated circuit device.

[Explanation of symbols]

Reference Signs List 1 GND (ground) potential 2 VDD (power) potential 3 Inverter 4 First NAND (NAND) circuit 5 Second NAND circuit 6 NOR (NOR) circuit 7, 8 Input terminal 9 Output terminal 11 Cell for GND terminal 12 For VDD terminal Cells 13, 23 Inverter cells 14A, 24A First NAND circuit cell 15B Second NAND circuit cell 16 NOR circuit cell 25-29 Wiring 30 P-type semiconductor substrate 31, 71A N-type well region 32, 72A P-type well Regions 33, 73A, 74A P-type source region 34, 75A P-type drain region 35, 76A, 77A N-type source region 36, 78A N-type drain region 37, 39, 42, 43, 47, 49, 55, 56, 6
2, 63, 67, 68, 80A, 81A, 85A, 87
A, 88A Contact holes 38, 40, 44, 48, 50, 57, 58, 64, 6
5, 69, 82A, 83A, 86A, 89A Conductive layer 41 Interlayer insulating film 45, 90A, 91A Gate electrode 46N NMOS transistor 46P PMOS transistor 53, 54 P-type diffusion region 61 N-type diffusion region 100 GND wiring 110 VDD wiring

Claims (13)

[Claims] 1. A semiconductor integrated circuit device comprising a combination of a plurality of unit cells having a desired logic function and arranging them on a semiconductor substrate to constitute a logic circuit. A semiconductor integrated circuit device provided with a terminal for use. 2. The semiconductor integrated circuit device according to claim 1, wherein said arbitrary unit cell is an inverter cell. 3. The semiconductor integrated circuit device according to claim 1, wherein said arbitrary unit cell is a NAND circuit cell. 4. The semiconductor integrated circuit device according to claim 1, wherein said arbitrary unit cell is a NOR circuit cell. 5. The semiconductor integrated circuit device according to claim 1, wherein said potential fixing terminal is a first or second logic level terminal. 6. The semiconductor integrated circuit device according to claim 5, wherein the first or second logic level terminal is connected to a power supply wiring or a GND wiring via a conductive semiconductor region, respectively. 7. The device according to claim 1, wherein the unit cell includes the first and second potential fixing terminals for outputting first and second logic levels. Semiconductor integrated circuit device. 8. The semiconductor integrated circuit device according to claim 7, wherein said first and second potential fixing terminals are respectively connected to a power supply wiring and a GND wiring via a conductive semiconductor region. 9. A unit cell in which a second conductivity type semiconductor region is formed in a first conductivity type well region and a potential fixing terminal connected to a predetermined potential wiring via the second conductivity type semiconductor region is provided. A semiconductor integrated circuit device comprising: 10. A first conductivity type well region and a second conductivity type well region are formed adjacent to each other in one direction, and the first conductivity type well region and the second conductivity type well region are respectively provided with a second conductivity type well region. A semiconductor region and a first conductivity type semiconductor region are formed, and are connected to a first logic level terminal connected to a power supply wiring via the second conductivity type semiconductor region or to a GND wiring via the first conductivity type semiconductor region. A semiconductor integrated circuit device, comprising: a unit cell provided with at least one set of a second logic level terminal or at least one set of a first logic level terminal and a second logic level terminal. 11. A unit cell in which a first conductivity type well region is formed and a potential fixing terminal connected to a predetermined potential wiring through the first conductivity type semiconductor region is provided. Semiconductor integrated circuit device. 12. A first conductivity type well region and a second conductivity type well region are formed adjacent to each other in one direction, and the first conductivity type well region and the second conductivity type well region are respectively provided with a first conductivity type well. A semiconductor region and a second conductivity type semiconductor region are formed and connected to a first logic level terminal connected to a power supply wiring via the first conductivity type semiconductor region or to a GND wiring via a second conductivity type well region semiconductor region. One of the second logic level terminals, or the first
At least one logic level terminal and the second logic level terminal
A semiconductor integrated circuit device having a set of unit cells. 13. The semiconductor integrated circuit device according to claim 1, wherein a wiring is connected from the potential fixing terminal provided in the unit cell to a predetermined terminal. .