JPS60242638A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance freedom in the disigning process and improve the degree of integration by a method wherein a basic element assembly is constituted of complementary MSI transistors so that the location over unused transistors may be used as a wiring region. CONSTITUTION:A basic cell is constituted of two P channel-type MIS transistors TR1, TR2 and two N channel-type MIS transistors TR3, TR4. The transistors of the same channel share a source or drain. In addition, the transistors of the different channels share a gate. In a region 20 for such basic cells, functional circuits composed of said basic cells are arranged, such as a triple-input NAND circuit forming region 31, flip-flop circuit forming region 32, inverter forming region 33, double-input NOR circuit forming region 34, flip-flop circuit forming region 35, double-input NAND circuit forming region 36, triple-input NOR circuit forming region 37. These circuits are connected to each other as necessary, longitudinally as well as laterally, for the constitution of a large-scale integrated circuit of the master slice type.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an MIS type large-scale integrated circuit using a master slice method.

As large-scale integrated circuits become larger, there is a trend toward high-mix, low-volume production.Nowadays, in order to reduce manufacturing costs and shorten production times, master slicing (SAAT-A1) is becoming more and more popular.
The production of large-scale integrated circuits using the 4 cm ) method is attracting attention.

[Conventional technology]

The master slicing method involves creating a large number of "basic element sets" (usually basic circuits from multiple transistors and resistors) in a single semiconductor chip (chip), and wiring them according to the developed product. A large-scale integrated circuit having a desired electrical circuit operation is completed by creating a mask and connecting transistors and resistors.

According to the master slicing method, the basic element set consisting of transistors, resistors, etc. is formed in large quantities in advance, so when a request for product development arises, only the wiring mask needs to be made, which shortens the development period. be done. Further, since the basic element set can be commonly used in various large-scale integrated circuits, development costs are also reduced.

Large-scale integrated circuits using this master slice method are
Generally, basic elements such as transistors and resistors are assembled and placed in a desired area of a conductor chip in an orderly matrix format, but this standardization allows for automatic placement using a Shimiko computer.

Wiring treatment can be effectively employed.

[Problem that the invention seeks to solve]

A master slice type large-scale integrated circuit is also divided into a basic element set including elements such as transistors and a wiring part, but it is extremely rare to use all the arranged transistors.

Therefore, when there is an unused basic element set, if the area above can be used as a wiring area, wiring will be easier and the period for wiring design will be shortened.

The present invention has been made in view of the various circumstances described above,
Its purpose is to use complementary MMIS transistors to create a simple structure with a common area of small area, and to make it possible to use unused transistors as wiring areas on transistors that are created as a basic element set. It is an object of the present invention to provide a master slice type semiconductor integrated circuit device that can be used for standardization.

[Means for solving problems]

For that purpose, the semiconductor integrated circuit device of the present invention includes a plurality of basic element sets formed on a base semiconductor substrate, and each of the basic element sets includes a pair of conductivity type channel MIS transistors 9.
A resistor and a pair of opposite conductivity type channels NIB) are arranged in parallel, each conductivity type channel Mis)
Each pair of transistors has a shared source region or common drain region and a drain region or source region specific to each MIS transistor disposed on both sides thereof, and one of the channel MIS transistors and the opposite conductive region. One of the channel MIS transistors has its gate electrode constituted by a common electrode, and the other of the - conductivity type channel MIS transistors and the other of the opposite conductivity type channel MIS transistors have their gate electrodes constituted by the common electrode. , each common electrode has a terminal extraction portion for wiring connection at both ends thereof, and the terminal extraction portion protrudes to the side opposite to the shared source region or shared drain region and is aligned with the unique source region or drain region. The device is characterized by a mask-sliced semiconductor integrated circuit device. Embodiments will be described in detail below. [Embodiments] FIG. 1 shows a basic element set (hereinafter referred to as basic cell) used to construct a large-scale integrated circuit according to the present invention.

The basic cell has two P-channel registers TR1, TR2 and two N-channel registers TR1 and TR2.
) consists of transistors TR5 and TR4. Transistors with the same channel share either the source or the drain. In addition, two different
The transistor pairs in the set share a gate.

FIG. 2 shows a front view of an impurity-introduced region pattern and a gate electrode pattern that realize the circuit configuration of the basic cell shown in FIG. In the figure, 1 is, for example, polycrystalline (poly)silico 7 (
A first gate electrode wiring layer made of (Si), IA, 1
B, IC' is a terminal extraction part of the first gate, 2 is a second gate electrode wiring layer also made of polysilicon, 2
A, 2B, and 2C are terminal extraction portions of the second gate. Further, 5 and 4.5 are N+m regions, which serve as source and drain regions of an N-channel transistor.

Further, 6 and 7.8 are P+ regions, and the source and drain regions of the P channel transistor. Further, reference numeral 9 denotes an island-like P-type region (F-well) in which the N-channel/channel type transistor is formed, which is previously formed on a y-type silicon semiconductor substrate 1°. Here, these source regions and drain regions can be formed by a normal impurity introduction method, such as an ion implantation method or a solid phase-in-phase diffusion method from impurity-containing glass. Impurities are introduced into the gate electrode made of polysilicon at the same time as the source and drain regions are formed to impart conductivity.

In this way, the basic cell according to the present invention has three P+ type and N+ type regions arranged symmetrically around the center of the terminal extraction portions IE and 2Bf of the gate electrode, and covers each of the impurity-introduced regions. Two gate electrodes are arranged vertically symmetrically. In addition.

Terminal lead-out portions of each gate electrode are provided at both ends and the center, and a gap is provided between the upper and lower gate electrodes to allow the terminals to be taken out from the impurity-introduced regions 4 and 7. Note that FIG. 3 is a cross-sectional view taken along the line A-A' in FIG.
The figure is a cross-sectional view taken along the line B-E' in Figure 2.
In the figure, 11 is, for example, silicon dioxide 7 (St 02
) and a field insulating film made of silicon dioxide, similar to the 12-layer film.

The basic cells as described above are arranged in rows as so-called plays on - semiconductor chips.

Here, if the basic cells are arranged in the vertical direction, a horizontal wiring area is secured for each basic cell. Figure 5 shows the arrangement of basic cells on a semiconductor chip.
Tens to hundreds of basic cells 21 are arranged in the vertical direction in each basic cell arrangement region 20, and about 10 to 30 basic cells 21 are arranged in the vertical wiring vacant region 22 provided between each arrangement region 20. wiring is provided.

The array regions 20 may be arranged laterally on the semiconductor chip in the tens or more as required. Figure 6 shows the basic cell 21
This is a plan view showing an enlarged arrangement state of basic cell 2.
A horizontal empty region 23 for wiring is formed between 1 and 21, and a gap is provided in this portion to accommodate about 1 to 4 wires.

In this way, by providing the horizontal wiring vacant area 23 between each basic cell, horizontal wiring distribution can be achieved. Local concentration of wiring reduces the wiring efficiency, and distributing wiring throughout the large-scale integrated circuit is important for improving the wiring efficiency.

Furthermore, as mentioned above, since the gate electrode terminals of the basic cells are symmetrically drawn out into the vertical wiring vacant area 22,
Wiring is very easy and the degree of freedom in wiring can be increased. That is, even if the vertical wiring area 22 on one side becomes overcrowded, the vertical wiring process can be performed in the adjacent vertical wiring area using the terminals on the opposite side.

In order to realize such vertical wiring and horizontal wiring, two wiring layers in the vertical direction and horizontal direction are used as wiring layers. Here, if the wiring layer closer to the semiconductor substrate, that is, the lower layer, is the first layer, and the wiring layer that is farther away, that is, the upper layer, is the second layer, then the first layer is in the direction of arrow A in FIGS. 5 and 6, that is, the basic The second layer can be set parallel to the vertical direction in which the cells are arranged adjacent to each other, and the second layer can be set in the direction of arrow B, that is, the horizontal direction orthogonal to the first layer. The lower wiring layer is formed on a first insulating layer made of, for example, phosphorous silicate glass (PSA) that covers the polysilicon gate electrode, and the upper wiring layer is formed on an insulating layer also made of phosphorous silicate glass that covers the lower wiring layer. is formed. Furthermore, a phosphorus silicate glass layer for passivation is formed to cover the upper wiring layer.

Here, the first layer wiring is not only provided in the wiring vacant area 22, but also utilized on the basic cell array area 20, as shown in FIG. The wiring arranged on this basic cell is applied to the power supply line, and these are connected to the P+ type region 24 provided on the island region 9 of the wiring vacant region 23 between the basic cells and the Ng silicon semiconductor substrate. Upper N+ type region 2
Resistive (ohmic) contact is made at the point marked with 5x.

In the complementary 711M18 circuit, an unused long gate cannot be left unconnected and must be connected to the power supply line.

In order to process such empty input terminals, the horizontal wiring empty area 23 that exists in each basic cell described above is used.

In Figure 7, if terminal outlets A and B or A' and B' become empty terminals, terminal outlets A or A' are connected to N+
By connecting the mold area 25 using the first wiring layer and connecting the terminal outlet B or B' to the P+ area 24 using the first wiring layer, empty terminals can be formed. can be easily connected to either a YA power supply or a Vss power supply.

Such processing of empty terminals is carried out in the vertical wiring empty area 22.
This can be achieved by connection processing using the empty area on the first layer sandwiched between the wiring and the power supply line provided in the lateral direction, so that empty terminals can be connected regardless of the horizontal wiring layer on the second layer. The wiring area on the semiconductor chip can be used very effectively.

On the other hand, in the master slice method, the basic elements in the basic cell as described above are connected appropriately.
1. It must be possible to form various gate circuits, flip circuits, 70-tube circuits, etc.

By using the basic elements, ie, basic cells, used in the present invention, it is possible to form dozens of types of logic gates and clip/70-tube circuits by appropriately connecting only those basic cells.

Next, using the basic cell according to the present invention, a logical NAND circuit (
An example of configuring HAND) is shown below.

FIG. 8 is a logical symbol diagram of a HAND circuit, and FIG. 9 is a circuit diagram of a HAND circuit composed of complementary NIB semiconductor devices. FIG. 10 is a layout diagram of this more advanced NAND circuit constructed using basic cells according to the present invention. In Figure 10, the thick solid lines are the first-layer wiring, the thin solid lines are the second-layer wiring, and the bus x marks indicate that each wiring is in ohmic contact with the impurity-introduced region in the semiconductor substrate through the electrode window. The dots are marked, and the * marks are the connection points between the first layer wiring and the second layer wiring. The connection point is provided by a through hole (Y4g), not shown, provided in an interlayer insulating layer made of, for example, phosphorous silicate glass (FSG). What should be noted here is that in the ft-HAND circuit composed of the basic cell according to the present invention, the gap provided between the two gate electrodes 1 and 2 allows the
The point is that the output of the AND circuit can be led to the vertical wiring regions on both sides of the basic cell.

Further, FIG. 11 is a logic symbol diagram of a D9 flip-flop circuit, and FIG. 12 is a circuit diagram of a clip/70 tube circuit composed of complementary Mis semiconductor devices. FIG. 15 is a layout diagram of such a slip-frog circuit constructed using the basic cell according to the present invention. In Fig. 16, the thick solid line is the first layer wiring, the thin solid line is the second layer wiring, and the x mark is the point where the wiring layer is in ohmic contact with the impurity-introduced region in the semiconductor substrate through the electrode window. The marks and marks indicate points where the first layer wiring and the second layer wiring are connected through through holes. Also in the configuration of this D-type clip-flop circuit, the outputs Q, Q can be led out to the vertical wiring regions on both sides of the basic cell array, similarly to the above-mentioned HAND circuit.

In this way, it is possible to form a 7-rethop/70-tub circuit or a HAND circuit using one or more of the basic cells according to the present invention, since it is possible to embody most logic configurations by combining them. This shows that the basic cell according to the present invention satisfies the performance as a basic cell of the master slice system and is excellent.

Further, by adopting the basic cell arrangement method according to the present invention, functional circuits can be effectively embedded without creating gaps between basic cells as long as wiring is permitted. Furthermore, compared to conventional large-scale integrated circuits using the master slice method, the semiconductor chip surface area can be used more effectively, and the degree of integration of large-scale integrated circuits can be greatly improved.

FIG. 14 shows an example in which a functional circuit configured by a combination of the basic cells is arranged in the basic cell arrangement area 20. In the figure, 31 is a 5-man power HAND circuit formation area, 32 is a 7-rip HAND circuit formation area, and 32 is a 7-rip HAND circuit forming area. A flop circuit forming area, 66 an inverter forming area, 64 a two-man NOR circuit forming area,
35 is a clip/70g circuit forming area, 56 is a two-person HAND circuit forming area, and 67 is a three-person NOR circuit forming area. These circuits are appropriately connected using vertical wiring and horizontal wiring to construct a desired large-scale integrated circuit.

FIG. 15 is a schematic diagram of the surface of a large-scale circuit semiconductor device according to the present invention. In the figure, reference numeral 41 indicates an area where an interface circuit with the outside of the large-scale integrated circuit is formed and an area where input/output electrode pads are formed. .

That is, as shown in FIG. 16, an input/output (Ilo) macros 44 consisting of an element arrangement section 42 in which a plurality of transistors and resistors are arranged and an input/output electrode pad 46 is provided.

The fake macros has one circuit (3-state output put input back 1.6 state output put buffer 1. , or true input buffer 1, etc.).

Then, if necessary, a desired buffer 7 circuit is provided by wiring the I10 macros. Note that the input/output electrode pad 43
A general thin lead wire can be connected to each of the external circuits.

As described above, in each basic cell arrangement region 20, the power source VaS power line and the VDD power line are provided in the vertical direction, but these power lines are much longer than other wiring lines. Therefore, a voltage drop occurs due to the resistance of the wiring itself, and the power supply voltage applied to the basic cells may differ depending on the location. For this reason, in the present invention, for example, a voltage equalizing line 42' is provided in the horizontal direction for every 10 basic cells, and VsB of each part on the semiconductor chip is
Aim to equalize the voltages in each of the power supply line and the YDD power supply line. This voltage equalization line is formed in the empty area of the second wiring layer.

In addition, in the embodiment of the present invention, in φ, the basic cellular configuration MIPI ffi )? The gate electrode of the resistor is
The polysilicon gate is made of polycrystalline (poly)silicon, and conductivity is imparted to the polysilicon gate when the source region and drain region are formed.

When a MIS type transistor is constructed using such polysilicon as a gate electrode, it is difficult to increase the operation speed of the Mis type transistor because the polysilicon layer has a relatively high resistance.

Therefore, in an advanced embodiment of the present invention, when forming the wiring layer structure, a metal layer is formed on the polysilicon gate electrode on the same plane and parallel to the lateral wiring layer. , the metal layer and the polysilicon gate electrode,
The connection is made at the terminal lead-out portion of the polysilicon gate electrode, thereby substantially increasing the effective cross-sectional area of the polysilicon gate electrode and lowering the resistance of the polysilicon gate electrode.

The metal layer may have the same pattern shape as the polysilicon gate electrode located therebelow with an insulating film interposed therebetween, and may have a structure in which it is weighted with the polysilicon gate electrode. However, if the metal layer is in close proximity to horizontal wiring led out from regions 4, 7, etc., and there is a possibility that problems may occur in the manufacturing process or electrical characteristics, the metal layer is The terminal lead-out portions of the silicon gate electrodes are connected in a straight line.

In the same figure, 51.52 are metal layers, 55A, 53E
.

Reference numerals 55Q, 54A, 54E, and 54C are connecting holes provided on the terminal extraction portions of the gold scrap layer 51, 52 and the polysilicon gate electrode; The same numbers as those shown in FIGS. 7, 10, etc. are given. Note that in addition to this, the gate electrode can also be formed of a highly heat-resistant metal.

〔Effect of the invention〕

As explained in detail above, the large-scale integrated circuit according to the present invention has a structure of a basic cell serving as a basic unit cell, which is a complementary board.
Since the IE structure is very compact, a large number of basic cells can be accommodated within the arrangement area of the basic cell.

Furthermore, the degree of integration can be made much larger than that of conventional large-scale integrated circuits.

Furthermore, the wiring structure of the basic cell does not use a complicated wiring structure and consists only of gate electrode wiring, so it is extremely compact. Therefore, since it is not necessary to form a wiring layer dedicated to the basic cell on the basic cell, the basic cell can be used as a wiring area with or between other basic cells. Furthermore, since the top of an unused basic cell can also be used as a wiring area between other basic cells, the degree of freedom in design is extremely high.

[Brief explanation of the drawing]

The first factor is a circuit diagram of the common parts constituting the large-scale integrated circuit according to the present invention, Fig. 2 is a front view of the pattern of the common parts, and Fig. 3 is a cut along the line A-A' in Fig. 2. 4 is a sectional view taken along the line B-B' in FIG. 2, FIG. 5 is a plan view showing the arrangement of common parts on the chip, and FIGS. 6 and 7 are common parts. 8 is a logical symbol diagram of the HAND circuit, and FIG. 9 is an enlarged plan view of the HAND arrangement.
A circuit diagram of an AND circuit, FIG. 10 is a layout diagram of a HAND circuit using common parts, FIG. 11 is a logic symbol diagram of a D-type flip-flop circuit, and FIG. 12 is a circuit diagram of a flip-flop circuit. FIG. 13 is a layout diagram of a flip-flop circuit, and FIG. 14 is a layout diagram showing an example of arranging functional circuits in a common partial array area. 15 and 16 are overall schematic diagrams of a large-scale integrated circuit chip embodying the present invention, and FIG. 17 is a plan view showing another embodiment of the basic element assembly according to the present invention. In the figure, 1 is the first gate electrode wiring layer, IA, IJ, and IC are terminal outlets, 2 is the second gate electrode wiring layer, 2A, 2B, and 2C are terminal outlets, 5, 4.5 are / m region, 6.7.8 is a P+ type region, and 9 is a P type island region. 10 is a semiconductor substrate, 11 is a gate insulating film, 20 is a basic cell arrangement area, 21 is a basic element set (basic cell), 22 is an empty area for vertical wiring, 25 is an empty area for horizontal wiring, 24 is a P+ type region, 25 is an r-group region, 42' is an equalizing wire, and 51.52 is a metal layer. Patent Applicant Fujitsu Ltd. Agent Patent Attorney Tama Mushi Hisa Go Part 9 Figure 10 Figure 11 lo (y 0 0 Figure 131i!fl Figure 14 Figure 15

Claims (2)

[Claims] (1) A plurality of basic element sets are formed on a base semiconductor substrate, and the basic element sets include a pair of conductivity type channels (Mis).
A transistor and a pair of channels of opposite conductivity (Mis) are arranged in parallel, and each conductive channel MIEI
) Each pair of transistors has a shared source region or a shared drain region. Each MIS transistor has a drain region or a source region specific to each MIS transistor disposed on both sides thereof, and one of the negative conductivity type channel transistors and one of the opposite conductivity type channel MIS transistors have gate electrodes having a common electrode. and the gate electrode of the other of the transistors and the other of the opposite conductivity type channel MIS transistors is constituted by a common electrode, and each common electrode is connected by wiring to both ends thereof. A mask characterized in that it has a terminal extraction part for the purpose of the present invention, and the terminal extraction part protrudes to the side opposite to the shared source region or shared drain region and is aligned with the unique source region or drain region.
Slice type semiconductor integrated circuit device. (2) Each of the common electrodes is also provided with a terminal extraction portion for wiring connection at a substantially central portion thereof, and the terminal extraction portion protrudes to the side opposite to the shared source region or shared drain region and 2. The mask-slicing semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is aligned with the source region or drain region of the semiconductor integrated circuit device.