JPH08123968A - Plotting processor - Google Patents

Abstract

PURPOSE: To speed up processing and to reduce the overhead of register setting with simple circuit constitution. CONSTITUTION: A buffer register 16 as a 1st stage which receives instructions and parameters from a CPU 10 and an execution register 18 as a 2nd stage which receives instructions and parameters transferred from the 1st-stage buffer register and makes a processor 20 perform plotting processing are provided in series in front of the plotting processor 20. Further, a selecting circuit 30 which sets the value of the execution register 18 used for the current plotting processing in the execution register 18 so that the value will be used as it is for next plotting processing is provided between the 1st-stage buffer register 16 and 2nd-stage execution register 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drawing processing apparatus used for displaying graphics such as a personal computer or a workstation.

[0002]

2. Description of the Related Art In recent years, the processing capacity of processors and the OS
With the development of technology, a graphical user interface (GUI) that makes extensive use of bitmap processing has become popular. However, since the load is heavy for the CPU to perform all the processing necessary for drawing and a practical response speed cannot be obtained, dedicated hardware is often provided in the display portion to supplement the CPU processing.

This display-only hardware is called a graphics accelerator or drawing processing device,
It consists of dedicated hardware including a drawing processor. FIG. 7 shows a conventional drawing processing apparatus, which has only one register for receiving instructions and parameters of the CPU 100. The register is an instruction register 102-1, an X coordinate register 102-2 for storing command parameters,
Y coordinate register 102-3 and color value register (RG
B register) 102-4 and the like.

[0004]

However, in such a conventional drawing processing apparatus, once the CPU 10
2 sets an instruction and a parameter in the registers 102-1 to 102-4 and the drawing processing graphic engine 106 of the processing processor 104 starts a drawing operation with respect to the frame memory 108. -1 to 102-4 cannot be set.
Therefore, in the case of continuous processing such as character drawing and vector drawing, the time waiting for the processing end of the processing processor 104 cannot be ignored.

FIG. 8 shows a FI for storing instructions and parameters.
This is a conventional device using the FO110. In this case,
The waiting time for the processing processor 104 to complete the processing can be reduced. However, the control circuit of the FIFO 110 is complicated, and it takes a long time from when an instruction is received by the FIFO 110 to when the processing processor 104 finishes the processing. For this reason, if the drawing process is not organized, it takes time to interpret the command each time, and the response becomes worse.

Further, when the next drawing process is performed after the completion of one drawing process, if the drawing areas on the frame memory 108 overlap, it is necessary to wait until the FIFO 110 becomes empty, and the advantage of using the FIFO 110 is lost. Be seen. Figure 9
Is a conventional device in which registers are duplicated in parallel. That is, command registers 102-1, 114-1, X coordinate registers 102-1, 114-2, Y coordinate register 10
2-3 and 114-3 and the color value register 102-4,
114-4 is provided and multiplexers 116-1 to 116
-4 is used for switching.

Such duplication of the registers also simplifies the hardware, and one register has the CPU 100
While setting the command and parameter, the other register can be selected and the processing processor 104 can perform the drawing process, and the waiting time can be shortened. However, since the two register groups operate independently, continuity of processing is lost. When processing with the same parameters (values such as coordinates, color information, size, etc.) following the previous processing, such as continuous drawing of vectors, it is necessary to set all parameters again, even if they are the same parameters. Therefore, the overhead of register setting becomes large.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a drawing processing apparatus capable of accelerating processing and reducing register setting overhead with a simple circuit configuration. To do.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention is directed to a drawing processing apparatus 14 including a drawing processor 20 that performs a drawing processing operation based on a command and a parameter independently of a CPU 10 that creates a command and a parameter.

According to the present invention as the drawing processing device 14 as described above, as shown in FIG. 1A, the drawing processor 20 receives a command and a parameter 1 from the CPU 10 before the drawing processor 20.
The buffer register 16 in the second stage and the execution register 18 in the second stage, which receives instructions and parameters from the buffer register 16 in the first stage and causes the processor 20 to perform the drawing process, are provided in series. To do.

Further, according to the present invention, as shown in FIG.
Buffer register 16 in the second stage and execution register 1 in the second stage
During 8, the execution register 18 used for this drawing process
In order to use the value of 1 as it is in the next drawing process as it is, a selection circuit 30 for resetting the value in the execution register 18 is provided. When the registers 16 and 18 are duplicated in series, the drawing processor 20 draws based on the busy status indicating the storage state of the instruction and parameter of the buffer register 18 of the first stage and the value of the execution register 18 of the second stage. The run status indicating that the process is being executed is C
When the CPU 10 continuously sets instructions and parameters to notify the PU 10 to instruct drawing, each time the busy status from the drawing processor 20 is released, the instruction and status are stored in the buffer register 16 of the first stage. To set.

On the other hand, when the CPU 10 instructs the next drawing process after one drawing process is completed by setting one command and parameter, the run status is released from the drawing processor 20 and the first stage is waited for. The following instructions and parameters are set in the buffer register 16.

[0013]

According to the drawing processing apparatus of the present invention as described above, C
By duplicating the registers that receive instructions and parameter settings by the PU 10 in series, the drawing processor 2
By releasing the buffer register 16 of the first stage during the operation of 0, waste of waiting time is eliminated, and the set value is changed from the buffer register 16 of the first stage to the execution register 1 of the second stage.
By taking over to 8, the continuity of processing can be maintained. Moreover, since the registers are simply connected in series, the amount of hardware is small.

[0014]

FIG. 2 shows a first embodiment of the present invention. CPU1
0 generates the drawing data necessary for the drawing process and transfers it to the drawing processing device 14 of the present invention. One drawing data created by the CPU 10 is composed of a command and its parameter. Taking two-dimensional drawing as an example, basic drawing data is composed of command X coordinate values, Y coordinate values, and color values (for example, RGB values) of coordinate points. Of course, for three-dimensional data, the Z coordinate value is added to this. In order to generate such drawing data, the CPU 10 performs modeling conversion for shape transformation known as rendering processing, color calculation for coloring, field-of-view calculation for changing a viewing range, and area limitation. Clipping to do this, coordinate transformation to change the viewing direction, anti-aliasing to remove jagged edges, etc. Further, as high-quality processing, phon shading for expressing shades of color, α blending for expressing transparency, and radiosity and ray tracing for expressing shadows and reflections can be performed.

The drawing processing apparatus 14 of the present invention has a drawing processor 20. The drawing processor 20 is equipped with a drawing processing graphic engine 22 realized by program control. The processing result of the drawing processor 20 is developed in the frame memory 24 as, for example, a two-dimensional dot pattern. The drawing pattern of the frame memory 24 is read and displayed on the CRT 26.

In the present invention, a duplicated register is provided in series in front of the drawing processor 20. In this embodiment, in addition to the command from the CPU 10, three command parameters of the X coordinate, the Y coordinate and the color value are taken as an example, so that there are provided four systems of duplicated registers in series. That is, for the command system, the command buffer register 16-1 and the command execution register 18-1 are provided in series.

Regarding the X coordinate, an X coordinate buffer register 16-2 and an X coordinate execution register 18-2 are provided in series. For Y coordinate, Y coordinate buffer register 1
6-3 and a Y-coordinate execution register 18-3 are provided. For color values, the color value buffer register 16
-4 and the color value execution register 18-4 are provided in series.

First stage buffer registers 16-1 to 16
The CPU bus 12 from the CPU 10 is connected to -4. The commands and parameters can be stored in the buffer registers 16-1 to 16-4 by sequentially reading and transferring the commands and parameters in order from the list structure of one pixel data created by the CPU 10.

The drawing processor 20 monitors the storage states of the first-stage buffer registers 16-1 to 16-4, and the CPU 10 is stored in the buffer registers 16-1 to 16-4.
The CPU 10 is notified of the busy status via the CPU bus 12 in the state where the instruction and the parameter are stored. Further, the drawing processor 20 sends the run status via the CPU bus 12 based on the values of the execution registers 18-1 to 18-4 in the second stage while the drawing processing graphic engine 22 is executing the drawing processing. CPU
Notify 10.

For this reason, the CPU 10 checks the busy status from the drawing processor 20 in order to instruct drawing by continuously setting commands and parameters such as vector drawing or character drawing, and checks the busy status of the busy status. When released, the first-stage buffer registers 16-1 to 16-4
The following commands and parameters will be set when is empty.

On the other hand, in the case of performing drawing according to the instruction of the next drawing data after the drawing processing in the drawing processor 20 based on the values of the execution registers 18-1 to 18-4 is completed,
The CPU 10 checks the run status of the drawing processor 20, and when the run status is released, the CPU 10 recognizes the end of one drawing process in the drawing processor 20 and sets the next command and parameter to the first stage. The buffer registers 16-1 to 16-4 are set to enable the next drawing process.

Further, two bits are provided from each of the first-stage buffer registers 16-1 to 16-4 in the drawing processing device 14.
The transfer of commands and parameters to the execution registers 18-1 to 18-4 of the second stage is performed by the drawing processor 20 after the drawing processing based on the values currently stored in the execution registers 18-1 to 18-4 is completed. At the timing when the run status is released, the first stage buffer register 1
The values already set by the CPU are transferred to 6-1 to 16-4. The transfer from the register of the first stage to the register of the second stage is automatically performed by the hardware based on the detection of the run status release by the drawing processor 20.

FIG. 3A shows each of the first-stage buffer registers 16-1 to 16-4 in the drawing processing apparatus 14 of FIG.
Processing. First, in step S1, it is checked whether an instruction and a parameter have been set in the buffer registers 16-1 to 16-4 from the CPU 10. When the command and the parameters are set, the drawing processor 20 returns the busy status to the CPU 10 in step S2.

Then, in step S3, the drawing processor 2
The run status accompanying the execution of the drawing process by 0 is checked, and when the run status is released, the process proceeds to step S4, and the values set in the buffer registers 16-1 to 16-4 are set in the execution register of the second stage. 18-1 to 18-4. When the transfer is completed, in step S5, the CPU 10
Release the busy status for. Then, the process returns to step S1 again and waits for the next instruction and parameter setting from the CPU 10.

FIG. 3B shows the processing of the execution registers 18-1 to 18-4 in the second stage of FIG. First, step S1
01, the first-stage buffer registers 16-1 to 16-4
It is checked whether the instruction and the parameter are transferred from the execution register 18-1 to the execution register 18-4. Upon receiving the instruction and parameter transfer, in step S102,
The drawing processor 20 uses the execution registers 18-1 to 18-4.
The drawing process based on the contents of is executed.

With the execution of this drawing process, step S1
At 03, the run status to the CPU 10 is returned. In step S104, the completion of execution of the drawing process is monitored, and when the execution is completed, step S105
Then, the run status is released and the process returns to step S101 to wait for the transfer of the instruction and parameter to the next execution register 18-1 to 18-4.

FIG. 4 shows the CPU 10 in the embodiment of FIG.
Processing. First, in step S1, the CPU 10 performs continuous processing such as character drawing or vector drawing, or 1
It is discriminated whether it is a non-sequential process with one command and parameter. If it is a continuous process, the process proceeds to step S2, and waits for the drawing processor 20 to release the busy status.

That is, the first-stage buffer register 16-1
Wait for ~ 16-4 available. When the busy status is released, the process proceeds to step S4, where the instruction and the parameter are transferred to the buffer registers 16-1 to 16-4 in the first stage and set. If the drawing is not completed in step S5, the process returns to step S1 again, and the command and parameter setting for the next continuous process are repeated.

On the other hand, if the continuous processing is not performed in step S1, the drawing processor 20 waits for the end of the drawing processing currently being executed. The end of this drawing process is step S3.
Can be detected by checking the run status from the drawing processor 20. When it is determined in step S3 that the run status has been released, one processing end wait has been completed, and therefore the process proceeds to step S4, in which the buffer register 16-1 to the instruction and parameter for the next drawing process are stored.
16-4 and set.

In this case, even if it is desired to check the busy status, the busy status is canceled before the run status is canceled and the first-stage buffer register is in an empty state. FIG. 5 shows a second embodiment of the present invention. In the second embodiment, the drawing processing device 14
It is characterized in that a selection circuit is provided between the first-stage buffer register and the second-stage execution register, which are provided in step 1, so that the current drawing process value can be used as it is in the next drawing process.

That is, the selection circuit (multiplexer) 30- is provided between the buffer registers 16-1 to 16-4 in the first stage and the execution registers 18-1 to 18-4 in the second stage of each system of command and parameter. 1 to 30-4 are provided.
The selection circuits 30-1 to 30-4 have two inputs A and B, and further have a control input S. One input A,
The outputs of the first-stage buffer registers 16-1 to 16-4 are given.

To the other input B, the stored value as the execution result of the execution registers 18-1 to 18-4 at that time by the drawing processor 20 is fed back and input. For the control input S, the buffer register 16-1
Selection bits 32-1 for controlling specific bits of 16-4
Input as 32-4. This selection bit 32-1
When the bit 32-4 is turned off (bit 0), the selection circuit 30-1 selects the input A.

On the other hand, the selection bits 32-1 to 32-
When 4 is turned on (bit 1), input B is switched to selection. The selection bits 32-1 to 32-4 of the buffer registers 16-1 to 16-4 can be turned on and off by the CPU 10. Therefore, when the CPU 10 wants to transfer the values of the buffer registers 16-1 to 16-4 to the execution registers 18-1 to 18-4 as they are, the selection bits 32-1 to 32-4 are bit-off (bit 0).
Set to.

On the other hand, when it is desired to use the values of the execution registers 18-1 to 18-4 currently undergoing the drawing process as the values of the next drawing process, the buffer register 16 is used.
Instead of setting the instructions and parameters for -1 to 16-4, it is only necessary to bit-on (bit 1) the selection bits 32-1 to 32-4. Regarding the drawing process using the values of the execution registers 18-1 to 18-4, when the current value is used as it is in the next drawing process, vector continuous drawing is performed. In continuous vector drawing, the start point and end point of each vector are continuously set. Of course, each of the start point and the end point is one drawing data having a command and parameters of X coordinate, Y coordinate and color value.

The end point of a certain vector is the execution register 18-
When transferred to 1 to 18-4 and being processed by the drawing processor 20, the start point of the next continuous vector becomes the same as the end point value of the execution register 18-1 to 18-4 currently being executed. In such a case, the CPU 10 uses the buffer register 1
Instead of setting the instruction and parameter of the start point of the next vector in 6-1 to 16-4, the selection bit 32-1
Bits 32 to 32-4 are turned on (bit 1).

In response to the selection bits 32-1 to 32-4 being turned on, the selection circuits 30-1 to 30-4 indicate the previous vector fed back from the drawing processor 20 from the selected state of the input A so far. Switch to the selected state of input B, which is the end point value, and execute registers 18-1 to 18-
4 again, the command and parameter relating to the end point of the previous drawing process are set as the command and parameter of the current vector start point.

By using the information of the current end point in such vector drawing as it is as the start point information of the next vector drawing, the setting for the first-stage buffer registers 16-1 to 16-4 by the CPU 10 can be simplified. The overhead of register setting can be reduced. Figure 6
Is the CPU processing of FIG. Steps S1 to S4 are the same as in the first embodiment of FIG. In the second embodiment, in the case of continuous processing, the busy
If the release of the status is determined, the process proceeds to step S6,
Check whether the previous end point is the start point of this time. If the previous end point is the current start point, the process proceeds to step S7, and buffer registers 16-1 to 16-16 for selecting the previous processing result.
-4 selection bits 32-1 to 32-4 are set to bit-on.

Of course, the fact that the previous register value is reset and used as it is next time is not limited to continuous vector drawing, and can be similarly applied to appropriate drawing processing as necessary. In the second embodiment shown in FIG. 5, selection circuits 30-1 to 30-4 are provided for each system,
The selection control is performed by the buffer register 1 for the CPU 10.
Specific selection bits 32-1 to 32 of 6-1 to 16-4
However, the selection is not limited to such a hardware configuration, and selection may be made in combination with software, or selection may be made only by software.

Further, the register system is not limited to the four systems of the embodiment, and an appropriate number of systems is used according to the number of parameters.

[0040]

As described above, according to the present invention, since the registers are serially duplicated and provided in the preceding stage of the drawing processor, the instruction and the parameter for the next operation can be stored while the drawing processor is operating. It can be set by the upper CPU, and the drawing processing can be speeded up by omitting the processing end waiting time by the drawing processor.

Further, by performing the selection processing of inheriting the processing value of the previous execution register to the processing value of the next time, it is possible to reduce the number of times of register access by the CPU. Furthermore, since it suffices to connect two registers in series in the preceding stage of the processor, it can be realized with a small amount of hardware.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is a flowchart of register processing of FIG.

4 is a flowchart of the CPU processing of FIG.

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a flowchart of CPU processing in FIG.

FIG. 7 is a block diagram of a conventional device using one stage of a register.

FIG. 8 is a block diagram of a conventional device using a FIFO.

FIG. 9 is a block diagram of a conventional device in which registers are duplicated in parallel.

[Explanation of symbols]

 10: CPU 12: CPU bus 14: Drawing processing device 16: Buffer register (first stage) 16-1: Command buffer register 16-2: X coordinate buffer register 16-3: Y coordinate buffer register 16-4: Color Value buffer register 18: Execution register 18-1: Command execution register 18-2: X coordinate execution register 18-3: Y coordinate execution register 18-4: Color value execution register 20: Drawing processor 22: Drawing processing graphic engine 24: Frame memory 26: CRT

Claims (5)

[Claims] 1. A C for creating drawing commands and parameters.
In a rendering processing device including a rendering processor that independently performs a rendering processing operation based on the instruction and parameters with respect to a PU, a first stage that receives an instruction and a parameter from the CPU before the rendering processor A buffer register,
A drawing processing apparatus comprising a second-stage execution register, which receives the instruction and the parameter transferred from the first-stage buffer register and causes the drawing processor to perform a drawing process, in series. 2. The drawing processing apparatus according to claim 1, further comprising the value of the execution register used for the current drawing processing between the buffer register of the first stage and the execution register of the second stage. The drawing processing device is provided with a selection circuit for resetting the execution register so that the drawing processing can be used as it is. 3. The drawing processing device according to claim 1, wherein the drawing processor has a busy status indicating a storage state of an instruction and a parameter of the buffer register in the first stage and the drawing stage in the second stage. The run status indicating that the drawing process based on the value of the execution register is being executed
A drawing processing device characterized by notifying U. 4. The drawing processing apparatus according to claim 3, wherein when the CPU continuously sets an instruction and a parameter to instruct drawing, each time the busy status from the drawing processor is released, A drawing processing apparatus which sets an instruction and a status in the first-stage buffer register. 5. The drawing processing apparatus according to claim 3, wherein when the CPU draws one drawing process by setting one command and one parameter and then instructs the next drawing process, the drawing processor The drawing processing apparatus, wherein the next instruction and parameter are set in the buffer register at the first stage after the run status is canceled.