JP2992406B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus provided with an I / O device (image display device) for performing drawing processing and the like by computer graphics.

[0002]

2. Description of the Related Art Conventionally, when data is transferred from a CPU to an I / O device, the I / O device receives data transferred from the CPU prior to activation of data transfer. Whether or not the preparation is completed (hereinafter, the state where the preparation is completed is referred to as non-busy, and the state where the preparation is not completed is referred to as busy) is confirmed by the CPU. If the result of this check is that the I / O device is in the non-busy state, data transfer from the CPU to the I / O device is started. As a result of the confirmation, if the I / O device is in a busy state, data transfer from the CPU to the I / O device is not activated. Such a prior art is disclosed in, for example, JP-A-1-161942.

[0003]

According to the above prior art, it is determined whether or not the I / O device is in a busy state before starting to transfer data from the CPU to the I / O device. (Confirmation) by the CPU is required. Therefore, there is a problem that data transfer from the CPU to the I / O device cannot be performed at high speed.

[0004] For this reason, especially in an image display device which needs to draw a large amount of data at a high speed, the time required for drawing becomes long, which is a major bottleneck in improving performance.

An object of the present invention is to perform high-speed data transfer from a CPU to an I / O device, particularly an image display device.

[0006]

According to the present invention, a master module, a slave module, a master module and a slave module are connected, and at least data between the master module and the slave module is achieved. In an information processing apparatus having a bus for transferring an address and a busy signal, a transfer starting means for starting data transfer from a master module to a slave module, and data transferred from the master module after starting the data transfer. Is ready in the slave module (non-busy state) or not (busy state), and when the busy detection means detects that the slave module is in the busy state A busy signal notifying unit for notifying the master module of a busy signal; The star module may include a busy signal detecting means for detecting that a busy signal is notified, and a means for terminating a bus cycle and terminating the activated data transfer upon detecting a busy signal. it can.

Further, an information processing apparatus comprising a master module, a slave module, a bus connecting the master module and the slave module, and transferring at least data, address, and busy signal between the master module and the slave module. Transfer activation means for initiating data transfer from the master module to the slave module, and address confirmation detection means for detecting in the slave module that the transfer destination address to which the data is to be transferred is decided after the data transfer is activated. Address identification means for identifying whether or not the determined transfer destination address is an address for the slave module; and, when the transfer destination address is identified as an address for the slave module, Module And a busy detection unit for detecting whether the slave module is ready to receive data transferred from the slave module (non-busy state) or not (busy state). And a busy signal notifying unit for notifying the master module of a busy signal when detected.
A busy signal detecting means for detecting the notification of the busy signal, and a means for terminating the activated data transfer by terminating the bus cycle upon detecting the busy signal, may be provided.

Further, an information processing apparatus comprising a master module, a slave module, a bus connecting the master module and the slave module, and transferring at least data, address, and busy signal between the master module and the slave module. Transfer activation means for activating data transfer from the master module to the slave module, and access request determination for detecting that the access request signal from the master module to the slave module is determined after the data transfer is activated in the slave module. A detecting unit, a busy detecting unit for detecting whether the slave module is ready to receive data transferred from the master module (non-busy state) or not (busy state); and an access request signal is determined. Octopus There is detected, busy - busy detection unit -
A busy signal notifying unit for notifying the master module of a busy signal when the state is detected, wherein the master module detects that a busy signal has been notified; and Means may be provided for terminating the activated data transfer by terminating the bus cycle upon detecting the busy signal.

Further, the master module can be a CPU (central processing unit) and the slave module can be an I / O device (input / output device).

A master module, a slave module, a bus connecting the master module and the slave module, and transferring at least data, an address, and a busy signal between the master module and the slave module are provided. In a data transfer method for controlling data transfer between modules, the slave module is ready to receive data transferred from the master module after starting data transfer from the master module to the slave module (non-busy). State) or not (busy state), and if the busy state is detected by the busy detection unit, a busy signal is notified to the master module, and the busy signal is notified in the master module. Is detected, and Upon detection of, and terminate the bus cycle, it is also possible to abort the started data transfer.

[0011]

In an information processing apparatus provided with an I / O device (image display device) for performing drawing processing by computer graphics and the like and a CPU, the CPU is provided with an I / O device to increase the drawing speed. Before confirming the busy state, the transfer of data to be displayed is started. After this activation, if it is confirmed that the I / O device is in a busy state, the data transfer is terminated (the bus cycle is terminated).

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows an example of the configuration of hardware according to this embodiment.

FIG. 1 shows a case where the I / O device is, in particular, a drawing device.

The image display device shown in FIG.
Clock generator 2 (120 MHz) and main memory 3 attached to PU 1, drawing device 5 for executing drawing processing, frame memory 6 and CRT 7 attached to drawing device 5
It is composed of The CPU 1 and the drawing device 6 are connected by buses 81 and 83 and signal lines 82, 84 to 86 and 41.

The CPU 1 includes an instruction execution unit 12 for processing a drawing program, a cache memory 11 for storing a part of the drawing program, a main memory 3 for storing the drawing program, and a bus control for controlling a bus connected to the drawing device 5. A unit 13 is provided.

The bus control unit 13 controls an instruction execution unit bus control unit 131 that controls the bus of the instruction execution unit 12, a memory bus control unit 132 that controls the bus of the main memory 3, and controls a bus connected to the drawing device 5. I / O device bus control unit 13
3. It has a DMA control unit 134 that controls the DMA when transferring the contents of the cache memory 11 to the drawing apparatus 5.

The I / O bus control unit 133 includes a busy signal detecting unit 1331 which is means 5 of the present invention, and a bus cycle terminating unit 1332 which is means 6 of the present invention.

The 120 MHz clock generator 2 supplies a clock of 120 MHz to the instruction execution unit 12 and the instruction execution unit bus control unit 131 by using the clock signal line 21. Thus, the instruction execution unit 12, the cache memory 11, and the instruction execution unit bus control unit 131 operate at 120 MHz.

The 30 MHz clock generator 4 has an I / O
A device bus control unit 133, a memory bus control unit 132,
A clock of 30 MHz is supplied to the main memory 3 and the drawing device 5 using a clock signal line 41. I / O device bus control unit 133, memory bus control unit 132, main memory 3
The bus controller 51 of the drawing device 5 is operated at 30 MHz.

The drawing apparatus 5 includes a drawing processing section 52 and a bus control section 51. The drawing processing section 52 performs a process of writing drawing data in the frame memory 6 in order to display an image on the CRT 7 in accordance with an instruction of a drawing program executed by the CPU 1. The bus control unit 51 receives a drawing instruction from the CPU 1 via a bus.

The bus control unit 51 includes an address signal determination detection unit 513 as the means 2 of the present invention, an address signal identification unit 512 for the drawing apparatus as the means 3, and a drawing processing unit business detection unit 511 as the means 1. Is provided. Busy signal line 8
Reference numeral 6 denotes means 4 of the present invention, which connects the drawing processing unit busy detection unit 511 and the busy signal detection unit 1331. This signal line 86 informs the CPU 1 of the state of the drawing processing unit detected by the drawing processing unit busy detection unit 511.

Next, the operation of each section in the image display device having the above-described configuration will be described. In the present invention, since 2 million continuous line segments (folded lines) are drawn in one second, this case will be considered.

FIG. 2 shows a CRT in the present image display device.
7 shows an example of the display screen of FIG. The display screen of FIG. 2 is a screen when a drawing program for drawing two million continuous lines 71 per second as described above is executed.

FIG. 3 shows a flowchart of the above program. This drawing program has 20 continuous
Since 100,000 line segments are drawn, the coordinates of the vertices, which are the connection points of the line segments, must be calculated at 2,000,001 per second. Here, for simplicity, it is assumed that the coordinates of two million vertices are calculated per second. In this case, the calculation of the coordinates per vertex must be made within 500 ns. In the flowchart of FIG. 3, the processing of the drawing program (steps 121 to 128) is roughly divided into three parts. That is, Steps 121 to 124 are processed in processing A (1206), Step 125
Is processing B (1207), and steps 126 to 128 are processing C (1208). Thus, drawing program 3
When divided, process A + process B + process C = 500 ns as shown at 120.

Hereinafter, processing A, A in the flowchart of FIG.
The processing in each of the steps B and C will be described.

In process A (1206), the instruction execution unit 12
First calculates the coordinates of one vertex. That is, CRT7
Consider the coordinate axes on the screen, and calculate the coordinates for one vertex. This calculation determines where one vertex should be drawn on the CRT 7 (step 121).

The coordinate calculation described above is specifically performed in FIG.
This is a matrix operation as shown in FIG. Of the coordinates (X, Y, Z) of one vertex, X and Y are coordinates for drawing on the CRT 7, but Z is used to determine which line is the upper side when the lines overlap each other. Used for
x, y, and z are coordinates given by the user, and parameters for converting the coordinates to coordinates on the CRT 7 are m11 to m3.
3. In these x, y, z and m11 to m33, 1
X, Y, and Z are obtained by performing 21 matrix operations.

The instruction execution unit 12 must transfer the values of X, Y, and Z, which are the operation results in step 121, to the drawing device 5. By the way, the instruction execution unit 12 is 120M
Hz, while the drawing device 5 operates at 30 MHz. Therefore, the speed of the arithmetic processing in the instruction execution unit 12 is high, and the speed of the transfer processing to the drawing device 5 is low. Therefore, every time the instruction execution unit 12 calculates the coordinates of one vertex, the efficiency of instruction processing is reduced if the calculation result is transferred to the drawing device 5. Therefore, the calculation result is 120M
The data is temporarily stored in the cache memory 11 operating at the Hz (step 122).

Next, for the vertices having the coordinates calculated in the process 121, it is calculated (color calculation) how many colors should be displayed on the CRT 7 (step 123). This color calculation is
The light intensity at each vertex is calculated by the formula shown in FIG.

FIG. 11B explains what angles A and B appear in FIG. 11A.

Here, the triangular mesh in FIG. 11B will be described. In order to draw an object on the screen of the display device, it is easiest to construct it by connecting several small surfaces. By making this small surface a triangle, the amount of information can be minimized. A combination of these triangles is called a triangle mesh. Actually, the positions of three vertices are calculated, and these vertices are connected by a line segment to display one triangle.

The calculation of the light intensity at each vertex shown in FIG. 11A is performed by calculating the R (red), G
The calculation is performed for each component of (green) and B (blue). The calculation result in step 123 must be transferred to the drawing device 5 in the same manner as the coordinate calculation result in step 121. However, for the same reason as when transferring the coordinate calculation results,
Temporarily store in the cache memory 11 (step 1
24).

Next, in process B (1207), an inquiry is made as to whether or not the drawing apparatus 5 is ready to receive data. If the data is ready to be received, the operation result transfer (DMA) from the cache memory 11 to the drawing device 5 is started (step 125).

The specific operation of each unit at this time will be described below.

The process of step 125 (start of transfer) in FIG. 3 is specifically, as shown at 125 in FIG.
The processing is performed by executing an instruction of “loading a transfer destination address in the drawing apparatus 5 to transfer data from the CPU 1 to the instruction execution unit 12”. When the data transfer is activated in this way, the I / O device bus control unit 133
Outputs the transfer destination address in the drawing apparatus 5 to the address signal line 81 in FIG. An output state of the address to the signal line 81 is shown at 81 in FIG.

Referring now to FIG.

In FIG. 5, reference numeral 41 denotes a signal line 41 of FIG.
2 shows the waveform of the 30 MHz clock signal output from FIG. In 41 of FIG. 5, the period from the rise of the 30 MHz clock signal to the next rise is referred to as one cycle. 30
One cycle of the MHz clock signal is about 33 ns.

Reference numeral 81 denotes a waveform of an address signal output to the signal line 81 in FIG. The address signal 81 is
15n from rising of 30MHz clock signal line 41
After S, the signal is output to the signal line 81.

Reference numeral 82 denotes A output to the signal line 82 in FIG.
3 shows a waveform of an S (address strobe) signal. A
The S signal 82 is set to the low level when 13 nS has elapsed after the output of the signal 81.

Reference numeral 85 denotes W output to the signal line 85 in FIG.
3 shows the waveform of the / R signal. The signal 85 is the AS signal 8
2 is simultaneously written (low level). The W / R signal 85 is written so that the calculation result can be transferred immediately when the drawing apparatus 5 is not busy.

The above processing (output of signal 81, low level of signal 82 and signal 85) is performed in one cycle from the first rising of clock signal 41. This cycle is called a first cycle.

The next cycle is called a second cycle. When the bus control unit 51 of FIG. 1 detects the rising of the second cycle, the address signal determination detection unit 513 outputs the AS signal 82
Is enabled (low level). Upon detecting this, the detection unit 513 sets the address signal line 81
Is confirmed (high level) to the address identification unit 512. Address identification unit 5 receiving this report
Reference numeral 12 identifies that the address signal line 81 indicates a transfer destination address in the drawing apparatus. Then, the transfer destination address is reported to the drawing processing unit busy detection unit 511. Upon receiving this report, the drawing processor busy detector 511 detects the state of the drawing processor (busy, non-busy) at this time. As a result, the detection unit 511 makes the busy signal line 86 valid (low level) if it is busy, and makes the busy signal line invalid (high level) if it is not busy. that's all,
From the time when the bus control unit 51 detects the rise of the second cycle to the time when the busy detection unit 511 reflects the state of the transfer destination address on the busy signal line 86 is executed at 28 nS as shown in FIG. .

The next one cycle is called a third cycle.
I / O device bus control unit 133 that has detected the third cycle
Detects the state of the busy signal line 86 at this time by the busy signal line detecting unit 1331.

As a result of this detection, the transfer destination address becomes
If not, it instructs the DMA control unit 134 to transfer the calculation result from the cache memory 11 to the drawing device 5. At the same time, it reports to the instruction execution unit bus control unit 131 that the drawing apparatus is not busy. DM who received instructions
The A execution unit starts transferring the operation result from the cache memory 11 to the drawing device 5. Instruction execution unit Bus control unit 131
Passes “1” to the instruction execution unit 12 in the sense that the calculation result has been transferred from the cache memory 11 to the drawing device 5. The instruction execution unit 12 stores “1” in the transfer enable / disable register 121 in the execution unit 12.

As a result of the above detection, the transfer destination address becomes
, The bus cycle end unit 1332
Report that At the same time, it reports to the instruction execution unit bus control unit 131 that it is busy. The bus cycle termination unit 1332 that has received the report invalidates (high level) the AS signal and the W / R signal at 15 nS from the rise of the third cycle in order to terminate the bus. At the same time, the instruction execution unit bus control unit 131 passes “0” to the instruction execution unit 12 in the sense that the calculation result could not be transferred from the cache memory 11 to the drawing device 5. Instruction execution unit 12
Stores this “0” in the transfer enable / disable register 121.

As described above, after the transfer destination address is determined, until the busy is reported to the instruction execution unit 12, the processing is completed in three cycles.

FIG. 6 shows signal timings in the above three cycles. In FIG. 6, reference numeral 802 denotes a timing according to the present invention. Reference numeral 801 denotes the timing according to the conventional technique. As can be seen from FIG. 6, the timing (802) of the present invention is more effective than the conventional timing (801).
One cycle faster at 30MHz bus cycle,
The status is transmitted to the instruction execution unit 12. This is 8
As shown in FIG. 05, the instruction cycle (1
20 MHz), which is four cycles faster. In time, it is about 33 nS faster.

FIG. 7B shows how much processing the instruction execution unit 12 can execute at about 33 ns.

FIG. 7A shows how the instruction execution section 12 operates.

The instruction execution unit 12 receives a clock signal from the clock generator 2 via a signal line 21 and
It operates with a MHz clock. The inside of the instruction execution unit 12 is composed of three instruction execution units. These three units are called unit 1 (1201), unit 2 (1202), and unit 3 (1203). These three units respectively operate in parallel. That is, the instruction execution unit 12
Instructions 1 to 3 (111) in 1 are fetched at a time. For example, instruction 1 is unit 1 (1201), instruction 2 is unit 2 (1202), and instruction 3 is unit 3 (1201).
Within (1203), about 8.3n per cycle (1204)
Execute in S. Similarly, in the next cycle, the instructions 4 to 6 (112) in the cache memory 11 are sequentially executed. In the next cycle, the instructions 7 to 9 (113) are sequentially executed. In the fourth cycle, the instructions 10 to 12 (114) are sequentially executed. take in. Then, three instructions are executed in each cycle. Thus, 4
In the cycle, processing of a total of 12 instructions is executed. That is,
At 33 ns, which is faster according to the present invention, the instruction execution unit 12 can execute processing of an extra 12 instructions.

The instruction execution unit 1 that receives the business status information of the drawing device 5 from the instruction execution unit bus control unit 131
2 loads the business status into a register of the instruction execution unit 12. As described above, the processing B (12
07), and then the process C (1208) is executed.

[0053] In process C (1208), first, the drawing apparatus 5 confirms whether a busy chromatography (Step 12
6). The processing in step 126 is specifically described in FIG.
This is shown at 126 in (b) . That is, the instruction execution unit 12
The value stored in the transfer enable / disable register 121 is “0”
Or "1". The result of this check, if "0" (drawing apparatus 5 is not able to transfer is computed a busy chromatography), again the process B (120
Return to 7). If it is “1”, the process proceeds to step 127. In step 127, it is determined whether there is no vertex to be drawn thereafter. If there is no vertex to be drawn, the drawing program ends. If there are more vertices to be drawn, the process proceeds to step 128, where preparations are made for the coordinate calculation and color calculation of the vertices to be drawn next.

In this way, processing for one vertex (processing A
A series of operations from (1206) to process C (1208) are executed, but the rendering processing apparatus calculates the coordinates and colors of two million vertices per second, so that the process for one vertex (process A)
(1206) to Process C (1208)) need to be executed at 500 nS. That is, as shown in FIG. 8, (A + B +
The processing time (120) of C) is 500 ns. Here, the processing time of B (1207) takes about 133 ns in the conventional status lead (1204), and the processing time of the present invention.
In the task (1205), it is about 100 ns. Therefore, the instruction execution unit 12 executes processing other than the status read ((A
+ C) (1208)) is about 367 ns in the conventional status lead (1204), which is 1
When converted to the number of clocks of 20 MHz, it becomes about 44 cycles, and in the status lead (1205) of the present invention, about 4 cycles are obtained.
At 00nS, it takes about 48 cycles. When this is converted into the number of instructions that can be executed by the instruction execution unit 12, about 132 instructions can be obtained by the conventional status read (12041) as shown in FIG.
In the status lead (12051) of the present invention, about 144 instructions are required.

As described above, according to the present invention, a program conventionally required to be composed of 132 instructions can be composed of 144 instructions in which the number of instructions is increased by 9% (12 instructions), and the drawing performance is improved. be able to.

The present invention is effective even when a single CPU is connected to a plurality of drawing devices (I / O devices) as shown in FIG.

In FIG. 10, the internal configuration of the CPU 1 is as follows.
It may be the same as FIG. The internal configuration of the drawing device 5 may be the same as that of FIG. 1 except for the address identification unit. The address identification unit of each drawing apparatus 5 is different from that of FIG. 1 in that it stores different addresses for identifying addresses addressed to the own apparatus.

[0058]

According to the present invention, data transfer from a CPU to an I / O device, particularly an image display device, can be performed at high speed. Therefore, the drawing process can be performed at high speed. For this reason, it is possible to further increase the speed of software for performing data transfer, and to improve the processing speed and ease of software creation for software that transfers a large amount of data in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hardware configuration example of the present invention.

FIG. 2 is a diagram illustrating a display screen of a processing result drawn by a drawing apparatus.

FIG. 3 is a flowchart illustrating processing executed by an instruction execution unit to cause a drawing apparatus to draw.

FIG. 4 is a diagram showing specific processing executed by an instruction execution unit.

FIG. 5 is a diagram showing a timing at which an instruction execution unit recognizes a drawing device business status.

FIG. 6 is a diagram illustrating a difference between timings for recognizing a drawing apparatus business status according to the related art and the present invention.

FIG. 7 is a diagram showing the operation of an instruction execution unit.

FIG. 8 is a diagram illustrating a difference between a time for recognizing a drawing status of a drawing apparatus according to the related art and the present invention, and a difference of a time that can be spent for processing other than recognizing the business status.

FIG. 9 is a diagram showing a difference in the number of instructions that can be spent on processing other than recognizing a drawing device business status according to the related art and the present invention.

FIG. 10 is another block diagram showing a hardware configuration example of the present invention.

FIG. 11 is an explanatory diagram of color calculation of a vertex.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Clock generator 3 Main memory 4 Clock generator 5 Drawing device 51 Bus control device 511 Drawing processing unit busy detection unit 512 Address identification unit to drawing device 513 Address signal determination detection unit 52 Drawing processing unit 6 Frame memory 7 CRT 81-86 Signal line 11 Cache memory 12 Instruction execution unit 121 Transfer enable / disable register 13 Bus control unit 131 Instruction execution unit bus control unit 132 Memory bus control unit 133 I / O device bus control unit 1331 Busy signal detection unit 1332 Bus Cycle end unit 134 DMA control unit

Claims (2)

(57) [Claims] A master module having an instruction execution unit for executing an instruction , a slave module, a connection between the master module and the slave module, and at least data between the master module and the slave module. , address, in an information processing apparatus having a bus for transferring busy over signal, a transfer starting means for starting the data transfer from the master module to the slave module, after the data transfer has been started, in the slave module Address determination means for detecting that the transfer destination address to which the data is to be transferred is determined; address identification means for identifying whether the determined transfer destination address is an address for the slave module; By the identification means, the transfer destination address is If it is identified as an address for blanking module,
Ready to receive data transferred from the master module, said state is made in the slave module (Nonbiji over state) or not <br/> busy over detector for detecting a (busy over state) or the busy chromatography If it is detected to be busy over state detector, busy for notifying busy over signal to the master module
A chromatography signaling means, to the master module, and busy over signal detecting means for detecting that said busy over signal is notified, upon detecting said busy over signal, to terminate the bus cycle, the is activated means for aborting the data transfer was, de from the master module to the slave module
Means for detecting whether or not the data transfer has been performed, and referring to the instruction execution unit, according to the stored value.
As the information for starting the next process, the detected
Also stores information indicating the status of data transfer.
The information processing apparatus characterized by comprising: means for. 2. The information processing apparatus according to claim 1, wherein the slave module is configured to detect an address determination of the address determination unit, identify an address of the address identification unit, and determine whether the busy detection unit is in a non-busy state. State) and each process of notifying the master module of a busy signal to the master module when the busy state is detected, based on the clock supplied to the slave module. After that, the information processing apparatus is executed until the second cycle ends.