JPH0635848A - Information processor - Google Patents

Abstract

PURPOSE:To transfer the data at a high speed to an I/O device and, to an image display device in particular, from a CPU. CONSTITUTION:A busy detecting part 511 starts a drawing device 5 through a CPU 1 for transfer of data and detects a non-busy state where the device 5 is ready to receive the data or a busy state. When an address decision detecting part 513 detects that a transferee address is decided for the data sent from the CPU 1, an address identifying part 512 decides whether the decided address is set to the device 5 or not. If so and also a busy state is detected by the part 511, the part 511 informs the CPU 1 of a busy signal. Then, the CPU 1 detects a fact that the busy signal is informed from a busy signal detecting part 1331. The CPU 1 detects the busy signal and discontinues the transfer of data or closes a bus cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having an I / O device (image display device) for performing drawing processing by computer graphics.

[0002]

2. Description of the Related Art Conventionally, when data transfer from a CPU to an I / O device is carried out, the I / O device receives data transferred from the CPU before starting data transfer. It is confirmed by the CPU whether or not it is ready (hereinafter, a ready state is referred to as a non-busy state and a non-ready state is referred to as a busy state). As a result of this confirmation, when the I / O device is in the non-busy state, the data transfer from the CPU to the I / O device is activated. As a result of the confirmation, when the I / O device is in the busy state, the data transfer from the CPU to the I / O device is not activated. As such a conventional technique, there is, for example, JP-A-1-161942.

[0003]

According to the above-mentioned prior art, whether or not the I / O device is in the busy state before the activation for transferring the data from the CPU to the I / O device is performed. Is required to be confirmed by the CPU. For this reason, there is a problem that data transfer from the CPU to the I / O device cannot be performed at high speed.

For this reason, particularly in an image display device that needs to draw a large amount of data at high speed, the time required for drawing becomes long, which is a major obstacle in improving the performance.

It is an object of the present invention to perform high-speed data transfer from a CPU to an I / O device, especially an image display device.

[0006]

To achieve the above object, according to the present invention, a master module, a slave module, a master module and a slave module are connected to each other, and at least data between the master module and the slave module, In an information processing device having an address and a bus for transferring a busy signal, a transfer starting means for starting data transfer from a master module to a slave module, and data transferred from the master module after starting this data transfer. When the slave module is ready to receive (busy state) or not (busy state), the busy detecting means detects whether the slave module is ready (non-busy state) or not (busy state). To the master module, a busy signal notifying means for notifying the master module of the busy signal The star module may include a busy signal detecting means for detecting that the busy signal has been notified, and a means for ending the bus cycle and aborting the activated data transfer when the busy signal is detected. it can.

Further, in an information processing apparatus including a master module, a slave module, a bus connecting the master module and the slave module and transferring at least data, address, and busy signal between the master module and the slave module. A transfer activation means for activating data transfer from the master module to the slave module; and an address confirmation detection means for detecting that the transfer destination address to which the data should be transferred has been determined in the slave module after the data transfer is activated. , An address identifying means for identifying whether or not the confirmed transfer destination address is an address for the slave module itself, and a master when the transfer destination address is identified by the identifying means for the slave module. Mod When the slave module is ready to receive data transferred from the device (non-busy state) or not (busy state), the busy detection unit detects that the data is in a busy state. When detected, the master module is provided with a busy signal notifying means for notifying the master module of the busy signal,
It is also possible to provide a busy signal detecting means for detecting that the busy signal has been notified, and a means for ending the bus cycle and canceling the activated data transfer when the busy signal is detected.

Further, in an information processing apparatus comprising a master module, a slave module, a bus connecting the master module and the slave module and transferring at least data, address and busy signal between the master module and the slave module. , A transfer activation means for activating data transfer from the master module to the slave module, and an access request confirmation for detecting that the access request signal from the master module to the slave module has been confirmed after the data transfer is activated in the slave module. An access request signal is determined by a detection unit, a busy detection unit that detects whether the slave module is ready to receive data transferred from the master module (non-busy state) or not (busy state). Shitako There is detected, busy - busy detection unit -
When it is detected to be in a state, it comprises a busy signal notifying means for notifying the master module of a busy signal, and in the master module, a busy signal detecting means for detecting that the busy signal has been notified, Means for terminating the bus cycle and aborting the initiated data transfer upon detection of the busy signal may also be provided.

Further, the master module may be a CPU (central processing unit) and the slave module may be an I / O device (input / output device).

Further, the master module, the slave module, and the bus for connecting the master module and the slave module and transferring at least data, address, and busy signal between the master module and the slave module are provided. In the data transfer method for controlling data transfer between modules, after activating the data transfer from the master module to the slave module, the slave module is ready to receive the data transferred from the master module (non-visible). Status) or not (busy status) is detected, and when the busy detection unit detects that the busy status is present, the master module is notified of the busy signal, and the master module is notified of the busy signal. Is detected, and the Upon detection of, and terminate the bus cycle, it is also possible to abort the started data transfer.

[0011]

In an information processing apparatus having an I / O device (image display device) for performing drawing processing by computer graphics and a CPU, the CPU is an I / O device for increasing the drawing speed. The transfer of data to be displayed is activated before the busy state is confirmed. After this start-up, when the I / O device is confirmed to be in the busy state, the data transfer is terminated (the bus cycle is terminated).

[0012]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows an example of the hardware configuration according to this embodiment.

FIG. 1 shows a case where the I / O device is a drawing device in particular.

The image display apparatus shown in FIG. 1 includes a CPU 1 and a C
A clock generator 2 (120 MHz) and a main memory 3 attached to PU1, a drawing device 5 for executing drawing processing, a frame memory 6 and a CRT 7 attached to this drawing device 5.
It consists of The CPU 1 and the drawing device 6 are connected by buses 81, 83 and signal lines 82, 84 to 86, 41.

The CPU 1 has a command execution unit 12 for processing a drawing program, a cache memory 11 for storing a part of the drawing program, a main memory 3 for storing the drawing program, and a bus control for controlling a bus connected to the drawing device 5. The unit 13 is provided.

The bus control unit 13 controls the instruction execution unit bus control unit 131 that controls the bus of the instruction execution unit 12, the memory bus control unit 132 that controls the bus of the main memory 3, and the control of the bus connected to the drawing device 5. I / O device bus control unit 13
3. A DMA control unit 134 for controlling the DMA when transferring the contents of the cache memory 11 to the drawing device 5 is provided.

The I / O bus control section 133 comprises a busy signal detection section 1331 which is the means 5 of the present invention and a bus cycle termination section 1332 which is the means 6 of the present invention.

The 120 MHz clock generator 2 supplies a 120 MHz clock to the instruction execution section 12 and the instruction execution section bus control section 131 using the clock signal line 21. As a result, the instruction execution unit 12, the cache memory 11, and the instruction execution unit bus control unit 131 operate at 120 MHz.

The 30 MHz clock generator 4 is an I / O
A device bus controller 133, a memory bus controller 132,
A 30 MHz clock is supplied to the main memory 3 and the drawing device 5 by using the clock signal line 41. I / O device bus control unit 133, memory bus control unit 132, and main memory 3
Then, the bus control unit 51 of the drawing apparatus 5 is operated at 30 MHz.

The drawing device 5 comprises a drawing processing section 52 and a bus control section 51. The drawing processing unit 52 writes the drawing data in the frame memory 6 in order to display an image on the CRT 7 according to an instruction of the drawing program executed by the CPU 1. The bus control unit 51 receives a drawing instruction from the CPU 1 via the bus.

The bus control section 51 is an address signal confirmation detection section 513 which is the means 2 of the present invention, an address signal identifying section 512 for the drawing device which is the means 3 and a drawing processing section busy detection section 511 which is the means 1. Equipped with. Busy signal line 8
Reference numeral 6 is the means 4 of the present invention, which connects the drawing processing unit busy detection unit 511 and the busy signal detection unit 1331. This signal line 86 informs the CPU 1 of the state of the drawing processing unit detected by the drawing processing unit busy detection unit 511.

Next, the operation of each section in the image display device having the above-mentioned structure will be described. In the present invention, since it is considered to draw 2 million continuous line segments (broken lines) per second, this case will be considered.

FIG. 2 shows a CRT in this image display device.
7 shows an example of the display screen of No. 7. The display screen of FIG. 2 is a screen when the drawing program for drawing 2 million continuous lines 71 in 1 second is executed as described above.

FIG. 3 shows a flow chart of the above program. This drawing program runs 20 times continuously for 1 second.
Since 20,000 line segments are drawn, the coordinates of the vertices, which are the connection points of each line segment, must be calculated in 2,000 times per second. Here, for simplicity, let us consider calculating the coordinates of 2 million vertices per second. In this case, the calculation of the coordinates per vertex must be within 500 nS. In the flowchart of FIG. 3, the process of the drawing program (steps 121 to 128) is roughly divided into three. That is, Steps 121 to 124 are processed A (1206), Step 125
Is a process B (1207), and steps 126 to 128 are a process C (1208). In this way, the drawing program 3
When divided, process A + process B + process C = 500 nS must be set as indicated by 120.

Hereinafter, the process A of the flowchart of FIG.
The processing in each step of B and C will be described.

In the process A (1206), the instruction execution unit 12
First calculates the coordinates of one vertex. That is, CRT7
Considering the coordinate axes on the screen, the coordinates for one vertex are calculated. This calculation determines where one vertex should be drawn on the CRT 7 (step 121).

The above-mentioned coordinate calculation is specifically shown in FIG.
Matrix operation as indicated by reference numeral 121. Of the coordinates (X, Y, Z) of one vertex, X and Y are the coordinates for drawing on the CRT 7, but Z is for distinguishing which line is on the upper side when the lines overlap. Used for.
x, y, and z are the coordinates given by the user, and the parameters for converting them to the CRT7 coordinates are m11 to m3.
It is 3. In these x, y, z and m11 to m33, 1
By performing the matrix operation 21, X, Y and Z are obtained.

The instruction executing section 12 must transfer the X, Y, and Z values, which are the calculation results in step 121, to the drawing device 5. By the way, the instruction execution unit 12 is 120M
Hz, while the drawing device 5 is operating at 30 MHz. Therefore, the operation processing speed in the instruction execution unit 12 is high, and the transfer processing speed to the drawing device 5 is low. Therefore, if the calculation result is transferred to the drawing device 5 every time the coordinate of one vertex is calculated in the command execution unit 12, the efficiency of the command processing becomes poor. So the calculation result is 120M
It is temporarily stored in the cache memory 11 operating at Hz (step 122).

Next, what color should be displayed on the CRT 7 for the vertex having the coordinates calculated in the processing 121 is calculated (color calculation) (step 123). This color calculation is
The intensity of light at each vertex is calculated by the formula shown in FIG.

FIG. 11B explains what kind of corners A and B appear in FIG. 11A.

Here, the triangular mesh in FIG. 11B will be described. The easiest way to draw an object on the screen of a display device is to connect several small surfaces together. By making this small surface a triangle, the amount of information can be minimized. A combination of these triangles is called a triangle mesh. Actually, the positions of three vertices are calculated, and these vertices are connected by line segments to display one triangle.

Calculation of the light intensity of each vertex shown in FIG. 11A is performed by calculating R (red) and G of the vertex as shown in FIG. 11C.
It is calculated for each component of (green) and B (blue). The calculation result in step 123 must be transferred to the drawing device 5 as well as the coordinate calculation result in step 121. However, for the same reason as when transferring the coordinate calculation result,
Temporarily store in the cache memory 11 (step 1
24).

Next, in process B (1207), the drawing apparatus 5 inquires whether or not it is ready to receive data. If the data is ready to be received, the operation result transfer (DMA) from the cache memory 11 to the drawing device 5 is activated (step 125).

The specific operation of each unit at this time will be described below.

Specifically, the process of step 125 (start of transfer) in FIG. 3 is performed as shown by 125 in FIG. 4 (b).
Processing is performed by executing an instruction "load data from the CPU 1 and transfer destination address in the drawing device 5 to the instruction executing unit 12". In this way, when the data transfer is activated, the I / O device bus control unit 133
Outputs the transfer destination address in the drawing device 5 to the address signal line 81 in FIG. The output of the address to the signal line 81 is shown at 81 in FIG.

Here, FIG. 5 will be described.

In FIG. 5, 41 is the signal line 41 of FIG.
3 shows the waveform of the 30 MHz clock signal output to. In 41 of FIG. 5, the period from the rise of the 30 MHz clock signal to the next rise is called one cycle. Thirty
One cycle of the MHz clock signal is about 33 ns.

Reference numeral 81 indicates the waveform of the address signal output to the signal line 81 in FIG. The address signal 81 is
15n from the rising edge of the 30MHz clock signal line 41
After S, it is output to the signal line 81.

Reference numeral 82 denotes A output to the signal line 82 in FIG.
The waveform of the S (address strobe) signal is shown. A
The S signal 82 is set to the low level when 13 nS has elapsed from the output of the signal 81.

Reference numeral 85 denotes W output to the signal line 85 in FIG.
The waveform of the / R signal is shown. Signal 85 is AS signal 8
At the same time as the output of 2, the write (low level) is made. The W / R signal 85 is written so that the calculation result can be immediately transferred when the drawing device 5 is not busy.

The above processing (outputting signal 81 and setting signals 82 and 85 to low level) is performed in one cycle from the first rise of clock signal 41. This cycle is called the first cycle.

The next cycle is called the second cycle. When the bus controller 51 of FIG. 1 detects the rising edge of the second cycle, the address signal confirmation detector 513 causes the AS signal 82 to be detected.
Detects that is enabled (low level). Upon detecting this, the detection unit 513 causes the address signal line 81
Is confirmed (high level) to the address identification unit 512. Address identification unit 5 that received this report
Reference numeral 12 identifies that the address signal line 81 indicates the transfer destination address in the drawing device. Then, the transfer destination address is reported to the drawing processing unit busy detection unit 511. Upon receiving this report, the drawing processing unit busy detection unit 511 detects the state (busy, non-busy) of the drawing processing unit at this time. As a result, the detection unit 511 validates the busy signal line 86 (low level) if it is busy, and invalidates the busy signal line (high level) if it is not busy. that's all,
After the bus controller 51 detects the rising edge of the second cycle, the busy detector 511 reflects the state of the transfer destination address on the busy signal line 86 in 28 nS as shown in FIG. .

The next one cycle is called the third cycle.
I / O device bus controller 133 that detected the third cycle
Detects the state of the busy signal line 86 at this time by the busy signal line detection unit 1331.

As a result of this detection, the transfer destination address is busy.
If not, the DMA control unit 134 is instructed to transfer the calculation result from the cache memory 11 to the drawing device 5. At the same time, it reports to the instruction execution unit bus control unit 131 that the drawing device is not busy. DM receiving instructions
The A execution unit starts the transfer of the calculation result from the cache memory 11 to the drawing device 5. Instruction execution unit Bus control unit 131
Passes "1" to the instruction execution unit 12 in the sense that the operation result can be transferred from the cache memory 11 to the drawing device 5. The instruction execution unit 12 stores this “1” in the transfer availability register 121 in the execution unit 12.

As a result of the above detection, the transfer destination address is busy.
If it is, the bus cycle end portion 1332 is busy.
Report that. At the same time, it also reports to the instruction execution unit bus control unit 131 that it is busy. Upon receiving the report, the bus cycle termination unit 1332 invalidates (high level) the AS signal and the W / R signal at 15 nS from the rising edge of the third cycle in order to terminate the bus. At the same time, the instruction execution unit bus control unit 131 passes “0” to the instruction execution unit 12 in the sense that the calculation result could not be transferred from the cache memory 11 to the drawing device 5. Instruction execution unit 12
Stores this “0” in the transfer availability register 121.

As described above, after the transfer destination address is determined, until the busy is reported to the instruction execution unit 12, the process is completed in 3 cycles.

FIG. 6 shows the timing of signals in the above three cycles. In FIG. 6, reference numeral 802 indicates the timing according to the present invention. Reference numeral 801 indicates the timing according to the conventional technique. As can be seen from FIG. 6, the timing (802) of the present invention is better than the conventional timing (801).
Bus cycle 30MHz, 1 cycle faster, busy
The status is transmitted to the instruction execution unit 12. This is 8
As shown by 05, the instruction cycle (1
20MHz), 4 cycles faster. In time, it is about 33 nS faster.

FIG. 7B shows how much processing can be executed by the instruction executing section 12 in about 33 nS.

FIG. 7A shows how the instruction executing section 12 operates.

The instruction executing section 12 receives the clock signal from the clock generator 2 through the signal line 21, and outputs the clock signal 120.
Operates with a MHz clock. The inside of the instruction execution unit 12 is composed of three instruction execution units. The three units are referred to as a unit 1 (1201), a unit 2 (1202), and a unit 3 (1203). Each of these three units operates in parallel. In other words, the instruction execution unit 12 uses the cache memory 1
Instructions 1 to 3 (111) in 1 are fetched at once. Then, for example, instruction 1 is unit 1 (1201), instruction 2 is unit 2 (1202), and instruction 3 is unit 3
Within (1203), one cycle (1204) is about 8.3n
Execute with S. Similarly, in the next cycle, instruction 4 to instruction 6 (112) in the cache memory 11, instruction 7 to instruction 9 (113) in the next cycle, and instruction 10 to instruction 12 (114) in the fourth cycle are sequentially performed. take in. Then, three instructions are executed in each one cycle. In this way, 4
In the cycle, a total of 12 instructions are processed. That is,
The instruction execution unit 12 can execute the processing of 12 extra instructions in 33 ns, which is faster due to the present invention.

Instruction Execution Unit Instruction Execution Unit 1 which has received the bus status information of the drawing device 5 from the bus control unit 131.
2 loads the busy status into a register included in the instruction execution unit 12. As described above, the process B (12
07) is ended, and then the process C (1208) is executed.

In the process C (1208), first, it is confirmed whether or not the drawing device 5 is busy (step 12).
6). The process in step 126 is specifically shown in FIG.
It is shown at 126 in (c). That is, the instruction execution unit 12
Value stored in the transfer permission / prohibition register 121 is “0”
Or "1" is checked. If the result of this check is "0" (the drawing device 5 was busy and could not transfer the calculation result), the process B (120
Return to 7). If it is “1”, the process proceeds to step 127. In step 127, it is determined whether or not there is a vertex to be drawn thereafter. If there is no vertex to be drawn, the drawing program is ended. If there are more vertices to be drawn, the procedure proceeds to step 128, where preparations are made for the coordinate calculation and color calculation of the next vertex to be drawn.

In this way, processing for one vertex (processing A
Although a series of operations from (1206) to processing C (1208) is executed, since the drawing processing apparatus calculates the coordinates and color of 2 million vertices per second, processing for one vertex (processing A
It is necessary to execute (1206) to process C (1208) at 500 nS. That is, as shown in FIG. 8, (A + B +
The processing time (120) of C) becomes 500 nS. Here, the processing time of B (1207) is about 133 nS in the conventional status read (1204), which is the case of the present invention.
Tasread (1205) is about 100 nS. Therefore, the instruction execution unit 12 executes a process other than the status read ((A
+ C) processing (1208) takes about 367 nS in the conventional status read (1204), which is 1
Converted to a clock frequency of 20 MHz, it takes about 44 cycles, which is about 4 in the status read (1205) of the present invention.
At 00 nS, it takes about 48 cycles. Converting this into the number of instructions that can be executed by the instruction executing section 12, as shown in FIG. 9, about 132 instructions in the conventional status read (12041),
The status read (12051) of the present invention has about 144 instructions.

As described above, according to the present invention, it is possible to compose a program, which conventionally has to be composed of 132 instructions, by 144 instructions with the number of instructions increased by 9% (12 instructions), thereby improving the drawing performance. be able to.

The present invention is also effective when a plurality of drawing devices (I / O devices) are connected to one CPU as shown in FIG.

In FIG. 10, the internal configuration of the CPU 1 is
It may be similar to FIG. The internal configuration of the drawing device 5 may be the same as that of FIG. 1 except for the address identification section. The address identification unit of each drawing device 5 is different from that of FIG. 1 in that it holds different addresses for identifying the addresses addressed to each device.

[0058]

According to the present invention, data can be transferred from the CPU to an I / O device, especially an image display device at high speed. Therefore, the drawing process can be performed at high speed. Therefore, it is possible to further increase the speed of software that transfers data, and it is possible to improve the processing speed and the ease of software creation for software that transfers a large amount of data in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration example of the present invention.

FIG. 2 is a diagram showing a display screen of a processing result drawn by a drawing device.

FIG. 3 is a flowchart showing a process executed by an instruction executing unit to cause a drawing device to draw.

FIG. 4 is a diagram showing a specific process executed by an instruction execution unit.

FIG. 5 is a diagram showing a timing at which an instruction execution unit recognizes a drawing device busy status.

FIG. 6 is a diagram showing a difference in timing for recognizing a drawing device busy status according to the related art and the present invention.

FIG. 7 is a diagram showing an operation of an instruction execution unit.

FIG. 8 is a diagram showing a difference in the time for recognizing the drawing device busy status of the present invention and the present invention, and a difference in time spent for processing other than recognizing the busy status.

FIG. 9 is a diagram showing a difference in the number of instructions that can be spent for processing other than recognizing the drawing device busy status of the related art and the present invention.

FIG. 10 is another block diagram showing a hardware configuration example of the present invention.

FIG. 11 is an explanatory diagram of color calculation of a vertex.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Clock generator 3 Main memory 4 Clock generator 5 Drawing device 51 Bus control device 511 Drawing processing part Busy-detection part 512 Address identification part to drawing device 513 Address signal confirmation detection part 52 Drawing processing part 6 Frame memory 7 CRT 81-86 signal line 11 cache memory 12 instruction execution unit 121 transfer enable / disable register 13 bus control unit 131 instruction execution unit bus control unit 132 memory bus control unit 133 I / O device bus control unit 1331 busy signal detection unit 1332 bus Cycle termination unit 134 DMA control unit

Claims (5)

[Claims] 1. A master module, a slave module, and a bus for connecting the master module and the slave module and transferring at least data, address, and busy signal between the master module and the slave module. In the information processing device, transfer activation means for activating data transfer from the master module to the slave module, and preparation for receiving data transferred from the master module after activation of the data transfer are completed in the slave module. An active state (non-busy state) or not (busy state), and a busy signal to the master module when the busy detection means detects a busy state. A busy signal notifying means for notifying, and the master module And a means for detecting that the busy signal has been notified, and a means for ending the bus cycle and aborting the activated data transfer when the busy signal is detected. An information processing device characterized by the above. 2. A master module, a slave module, and a bus for connecting the master module and the slave module and transferring at least data, address, and busy signal between the master module and the slave module. In the information processing device, a transfer activation unit that activates data transfer from the master module to the slave module; and, after the data transfer is activated, a transfer destination address to which the data is to be transferred is determined in the slave module. An address confirmation detecting means for detecting, an address identifying means for identifying whether or not the determined transfer destination address is an address for the self slave module, and the identifying means for determining that the transfer destination address is an address for the slave module. is there If it is identified,
A busy detection unit that detects whether the slave module is ready to receive data transferred from the master module (non-busy state) or not (busy state), and a busy detection unit A busy signal notifying means for notifying the master module of a busy signal when it is detected to be in a state, and the master module having a busy signal for detecting that the busy signal is notified. An information processing apparatus comprising: a detection unit; and a unit that terminates a bus cycle when the busy signal is detected and terminates the activated data transfer. 3. A master module, a slave module, and a bus for connecting the master module and the slave module and transferring at least data, address, and busy signal between the master module and the slave module. In the information processing device, a transfer activation unit that activates data transfer from the master module to the slave module; and, in the slave module, an access request signal from the master module to the slave module after the data transfer is activated. Access request confirmation detecting means for detecting confirmation and confirmation of whether or not the slave module is ready to receive data transferred from the master module (non-busy state) or not (busy state). Business A detection unit, wherein it is detected that the access request signal is confirmed, the busy - when it is detected that the state, - busy detection unit
And a busy signal notifying unit for notifying the master module of the busy signal, wherein, in the master module, a busy signal detecting unit for detecting that the busy signal is notified, and a busy signal detecting unit for detecting the busy signal. Then, the information processing apparatus comprising: a unit that terminates the bus cycle and terminates the activated data transfer. 4. The information processing apparatus as claimed in claim 1, wherein the master module is a CPU (central processing unit) and the slave module is an I / O device (input / output device). . 5. A master module, a slave module, and a bus that connects the master module and the slave module and transfers at least data, address, and busy signals between the master module and the slave module, In the data transfer method for controlling data transfer between the master module and the slave module, the slave that is ready to receive data transferred from the master module after activating data transfer from the master module to the slave module It detects whether the module is in a non-busy state or not (busy state), and notifies the master module of a busy signal when the busy detector detects that the busy state is present. In the master module, A data transfer method, comprising: detecting that a busy signal has been notified, terminating a bus cycle when detecting the busy signal, and terminating the activated data transfer.