JPH02245982A - Picture processor - Google Patents

Abstract

PURPOSE:To shorten the transfer time of picture data, and to speed up a picture processing by coupling a command parameter memory and a picture memory to different buses with an interposed picture processor. CONSTITUTION:A command parameter memory 2, which stores data to be processed by a picture processor 3, and a picture memory 4, which stores the picture data from the picture processor 3, are provided. Further the picture processor 3 and the command parameter memory 2, and the picture processor 3 and the picture memory 4 are respectively coupled by respectively different buses 7a and 7b. Consequently while the picture processor 3 executes the processing for the picture memory 4, a command to be next processed can be latched to the picture processor 3 from the memory of the command parameter. Thus the data transfer time can be shortened, and the picture processing can be sped up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for processing various input images in a manner suited to its processing purpose, and particularly relates to an image processing device that processes various input images in accordance with its processing purpose.
This invention relates to improvements in data access between a command/parameter memory and an image processing processor.

In recent years, there has been an increasing demand for image processing apparatuses that input target images using image input devices such as television cameras and perform inspection and recognition. This is to automate the conventional visual inspection and recognition process to improve productivity in factories and the like.

Furthermore, image processing devices are widely used in various fields such as image conversion, measurement pattern recognition, and simulation image generation.

[Conventional technology]

Currently, devices that display graphics and the like on CRTs tend to have higher resolution and higher speed year by year. Therefore, if the main CPU were to perform graphic drawing processing, it would take too much time, leading to a decrease in system performance. Therefore, a device that specializes in graphic display and drawing processing was considered, and the main C
A system has begun to be adopted in which the PU only issues commands and parameters, and a specialized processor performs image processing.

However, in such a system, each time the image processing processor performs processing, the CPU sends a message to the image processing processor.
Since commands and parameters must be issued, there is a drawback that CPU efficiency is reduced.

Another method is a method in which the image processing processor itself takes in commands and parameters through DMA transfer and performs image processing. FIG. 4 shows an example of the configuration of an image processing device. The image processing apparatus includes an image processing processor 101, an image memory 102 in which image data to be processed is stored, and a command memory 102 that stores commands and parameters for processing by the image processing processor 101.
Parameter memory 103 and image processing processor 101
The CPU 10 writes and reads the internal registers of
4, a bus 105 that connects these, and a CPU 104 that outputs images from the image memory.

Next, the operation during image data transfer will be explained. The image processing processor 103 is stored in the command/parameter memory 103.
Commands and parameters for processing are stored, and the image processing processor 103 uses this command/parameter memory 103 to execute drawing commands (for example,
BITBLT, surface drawing, line drawing, etc.), control commands (e.g., conditional branching, etc.), or parameters (e.g.,
(end point, start point, etc. of line drawing) and performs condition judgment on the image memory. The image data stored in the image memory 102 is output to the CRT.

[Problem to be solved by the invention]

The problem with the conventional image processing apparatus described above is that the image memory 102, command/parameter memory 103, and image processing processor 101 are accessed through one bus 105, so the image processing processor 101 takes in the command parameters. At the time, the image processing processor 101
When access between the image memory 102 and the image memory 102 is not possible and the image processing processor 101 is performing image processing,
This will make it impossible to import commands and parameters, resulting in a decrease in processing efficiency.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image processing device that accesses the image memory and the command/parameter memory using different buses to shorten the image data transfer time, thereby achieving speedup. .

[Means to solve the problem]

In order to achieve the above object, the present invention provides an image processing processor (3) that converts input image data into a predetermined data format.
, a command/parameter memory (2) for storing data processed by the image processing processor (3), an image memory (4) for storing image data from the image processing processor (3), and the image processing processor; In an image processing device equipped with a bus (7) that connects a command/parameter memory and an image memory, the image processor and command/parameter memory and the image processor and image memory are connected to different buses (7a, 7b), respectively. Combine and compose.

[Effect]

According to the present invention having the above configuration, since the command/parameter and the image memory are accessed through different buses (7a, 7b), the image processing processor can access the image while the image processing processor is processing the image memory. The next command to be processed can be latched into the processor from the command/parameter memory. Therefore, it is possible to shorten data transfer time and speed up image processing.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

Referring to FIG. 1, an image processing device 1 according to the present invention includes:
It has a command/parameter memory 2.

The command parameter memory 2 is a memory that stores commands and parameters for the image processing processor 3 to perform processing, and the image processing processor 3 receives drawing commands (for example, BITBLT, area drawing , line drawing, etc.), control commands (for example, conditional branching, etc.), or parameters (for example, end point, start point of line drawing, etc.), and draw on the image memory 4 or make conditional judgments. The image memory 4 is CR
This is a memory for storing figures and the like to be displayed on T5, and is accessed by the image processing processor 3.

The CPU 6 writes to and reads from the internal registers of the image processing processor 3.

These CPU 6, command/parameter memory 2, image memory 4, and CRT 5 are connected to buses 7a and 7b, respectively, and the command/parameter memory 2 and image memory 4 are different from each other with the image processing processor 3 in between. They are coupled to buses 7a and 7b, respectively.

FIG. 2 shows an internal configuration diagram of the image processing processor 3. The bus interface 8 is the image processing processor 3
This is an interface circuit that outputs external address data to an internal address and data bus, and is mainly composed of latches and buffers. The command register 9 is a register for latching commands taken in from outside the image processor. The drawing unit 10 receives a command (for example, BITBL) latched in a command register.
This is a unit for executing (T, area drawing, line drawing, etc.). Graphic interface 11 is image memory 4
This is a block that interfaces with the image processing processor 3. For example, in the case of a line drawing command, when writing graphic data sent from the drawing unit 10 to the image memory 4, it reads the graphic data from the image memory 4 and performs drawing. Processing such as sending the data to the unit 10 is performed.

According to the image processing apparatus 1 configured in this manner, the first command to be executed from the command/parameter memory is latched into the command register 9 via the bus interface 8. In response to the latched command, the drawing unit 10 starts processing the graphic interface 11, and the graphic interface 11 starts processing the image memory 4. During this processing, the next command to be executed is latched into the command register 9. Immediately after the processing of the first command is completed, execution of the command latched in the command register 9 is started.

Next, FIG. 3 is a comparison diagram of the processing time between the conventional case where the image memory 102 and the command/parameter memory 103 are accessed through one bus, and the case where they are accessed using different buses according to the present invention.

TOI is the access time of the conventional command/parameter memory 103, TO2 is the access time of the conventional image memory 102, TNl is the access time of the command/parameter memory of the present invention, and TN2 is the access time of the image memory of the present invention. represents time. Since the image memory 4 and the command/parameter memory 2 are accessed through different buses in this way, while the image memory 4 is being processed, the next processing from the command/parameter memory 2 is stored in the command register 9. Commands can be latched. That is, in FIG. 3, access times T and T2 of TN2
During this time, the command/parameter memory is accessed. As a result, the conventional command/parameter memory access time and the image memory access time TOI,
TO2 does not overlap and the total access time is T
The time is the sum of ol and TO2, but according to the present invention,
The access time is shortened by T and T2, and image processing speed can be increased by that amount.

〔Effect of the invention〕

As described above, according to the present invention, since the image memory and the command/parameter memory are accessed through different buses, the image processing device command The next command to be processed can be latched into the register from the command parameter memory.

This makes it possible to shorten the image data transfer time and speed up image processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an internal configuration diagram of an image processing processor, FIG. 3 is an explanatory diagram showing a comparison of processing time between the conventional method and the present invention, and FIG. 4 is a conventional example. 1 is a block diagram of the technology's image processing processor; FIG. 101... Image processing processor 102... Image memory 103... Command/parameter memory 104...
- CPU 1... Image processing device 2... Command/parameter memory 3... Image processing processor 4... Image memory 5... CRT 6... CPU 7a, 7b... Bus 8...・Bus interface 9...Command register 10...Drawing unit 11...Graphic interface Conventional technology image processing Bromo, Sunoflow, Riwhistle 4 Figure

Claims (1)

[Claims] An image processing processor (3) that converts input image data into a predetermined data format; a command/parameter memory (2) that stores data processed by the image processing processor (3); An image processing apparatus comprising an image memory (4) for storing image data, and a bus (7) connecting the image processing processor (3), command/parameter memory (2), and image memory (4). An image processing device characterized in that a parameter memory (2) and an image memory (4) are accessed through different buses (7a, 7b).