JPH08114659A - Semiconductor magnetoelectric transducer - Google Patents

Abstract

PURPOSE: To provide a Hall IC which can accurately measure the magnetic flux density by compensating the change, when the Hall voltage output from the element varys with temperature. CONSTITUTION: The semiconductor magnetoelectric transducer comprises a Hall element 1 for outputting a differential voltage corresponding to the intensity of an applied magnetic field, Differential amplifiers 2-6 for amplifying the output voltages of the element 1, amplifiers 7-11 for outputting currents corresponding to the intensity of the magnetic field applied based on the outputs of the amplifiers 2-6, and a resistor 12 formed near the element 1 on a semiconductor substrate having the Hall element 1 formed on it to generate a voltage corresponding to the intensity of the field applied upon reception of the output currents of the amplifiers 7-11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor magnetoelectric conversion device for measuring the strength of a magnetic field with a Hall element, and more particularly to improving the temperature dependence of its output characteristics.

[0002]

2. Description of the Related Art A Hall element is an element that outputs a voltage proportional to the strength of an applied magnetic field and is used as a magnetic flux density-voltage conversion element. The Hall element and the signal processing circuit are formed on the same semiconductor substrate, and a Hall IC integrated into one chip is used as a semiconductor magnetoelectric conversion device. This type of Hall IC is generally composed of a Hall element, an amplifier circuit that amplifies the output of the Hall element, and an output circuit that processes a signal output from the amplifier circuit.

FIG. 9 shows a block diagram of this type of Hall IC. In the figure, 1 is a Hall element that outputs a voltage proportional to the strength of the applied magnetic field. Hall element 1
Are input terminals 1a, 1 which are terminals for supplying power from the outside.
b, output terminals 1c and 1d for outputting a voltage signal proportional to the strength of the magnetic field are provided. Reference numeral 21 is an amplifier circuit that receives the output from the output terminals 1c and 1d and amplifies it, and 23 is an output circuit that processes the output of the amplifier circuit 21. The output of this Hall IC is output to the output terminal 24. The internal power supply (VCC) of the IC is connected to the input terminal 1a of the hall element 1, and the input terminal 1b is grounded.

Next, the operation will be described. Hall element 1
The output voltage appearing between the output terminals 1c and 1d of
The "Hall voltage" is generally expressed by the following equation as is well known. Where _{V H = K H · (I} H · B / d) · f H, V H: Hall voltage, K _H: Hall coefficient, I _H: Hall element drive current, B: magnetic flux density, d: the Hall element Thickness, f _H : A coefficient depending on the shape of the Hall element.

The amplifier circuit 21 amplifies this Hall voltage with a predetermined gain and outputs it to the output circuit 23. This output voltage is proportional to the strength of the applied magnetic field. Output circuit 2
3 performs a predetermined process on the output of the amplifier circuit 21 so that a predetermined output required for this Hall IC can be obtained. This output is output to the outside of the IC via the output terminal 24.

[0006]

In the conventional Hall IC, as shown in FIG. 9, the Hall element is set to a constant voltage (VC).
Let's find the formula of the Hall voltage when driving in C). Here, since I _H = V / R _IN , (V is an applied voltage, R _IN is an input resistance of the Hall element 1), V _H = K _H · (V / R _IN ) · (B / d) · f _H. By the way, it is known that the input resistance R _IN of the Hall element has temperature dependence. Therefore, when the Hall element is driven at a constant voltage, R _{IN in} the above equation changes greatly, so that the Hall voltage V _H also has temperature dependency. That is, even when the magnetic flux density B is constant, the Hall voltage changes greatly depending on the temperature.

The absolute value of the input resistance R _IN of the Hall element 1 tends to vary greatly depending on the manufactured IC. This also causes the absolute value of the Hall voltage to vary greatly. Due to these causes, the magnitude of the Hall voltage corresponding to the magnetic flux density B varies, so that it is difficult to measure the correct magnetic flux density B.

The present invention has been made in order to solve the above problems, and accurately measures the magnetic flux density B even if the Hall voltage with respect to the magnetic flux density B changes for each IC or due to temperature. It is an object of the present invention to provide a semiconductor magneto-electric conversion device that can do the above.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor magneto-electric conversion device having a Hall element for outputting a voltage corresponding to the strength of an applied magnetic field and a differential amplifier for amplifying an output voltage of the Hall element. An amplifier for outputting a current corresponding to the strength of a magnetic field applied based on the output of the differential amplifier; and the amplifier formed on the semiconductor substrate on which the hall element is formed in the vicinity of the hall element. And a resistor for generating a voltage corresponding to the strength of the applied magnetic field in response to the output current of.

According to a second aspect of the present invention, there is provided a semiconductor magneto-electric conversion device in which the amplifier has a first collector-grounded amplifier circuit having the first output of the differential amplifier as an input and a second collector of the differential amplifier.
A second collector-grounded amplifier circuit that receives the output of the input, and an operational amplifier that receives the output of the first collector-grounded amplifier circuit and the output of the second collector-grounded amplifier circuit,
A first transistor that operates based on the output of the operational amplifier, divides a current from the first grounded collector amplifier circuit, and outputs the first transistor; and operates based on the output of the operational amplifier.
A second transistor for shunting and outputting a current from the second common-collector amplifier circuit, wherein the output of the amplifier is the sum of the output of the first transistor and the output of the second transistor Is.

According to another aspect of the semiconductor magnetoelectric conversion device of the present invention, the amplifier is operated based on an output of the differential amplifier and an operational amplifier that receives the output of the differential amplifier, and an output terminal of the differential amplifier is operated. It is composed of a transistor that splits and outputs a current from one side.

According to a fourth aspect of the present invention, there is provided a semiconductor magneto-electric conversion device in which the resistor has characteristics similar to those of the Hall element.
It is formed by a structure similar to that of the Hall element.

[0013]

According to the present invention, the Hall element outputs a voltage corresponding to the strength of the applied magnetic field, the differential amplifier amplifies the output voltage of the Hall element, and the amplifier is the differential amplifier. Outputting a current corresponding to the strength of the magnetic field applied based on the output, the resistor formed in proximity to the Hall element on the semiconductor substrate on which the Hall element is formed,
It receives the output current of the amplifier and generates a voltage corresponding to the strength of the applied magnetic field.

According to a second aspect of the present invention, the first collector-grounded amplifier circuit and the second collector-grounded amplifier circuit receive the output of the differential amplifier and output a predetermined voltage, and the operational amplifier outputs the first voltage. The first transistor and the second transistor, which operate based on the outputs of the common-collector grounded amplifier circuit and the second common-grounded amplifier circuit, and operate based on the output of the operational amplifier, are the first common-grounded amplifier circuit and the second transistor. The current is shunted from the grounded-collector amplifier circuit of No. 2 and used as the output of the above amplifier.

In the invention of claim 3, the operational amplifier operates based on the output of the differential amplifier, and the transistor operating based on the output of the operational amplifier divides a current from one of the output terminals of the differential amplifier. And the output of the above amplifier.

In the invention of claim 4, the resistor formed by a structure similar to the structure of the hall element cancels the fluctuation of the characteristics of the hall element so that the characteristics are similar to those of the hall element. .

[0017]

【Example】

Example 1. An embodiment of the Hall IC according to the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a Hall element provided on a semiconductor substrate using an epitaxial layer. The Hall element 1 includes input terminals 1a and 1b which are terminals for supplying a power supply (VCC) from the outside, and output terminals 1c and 1d which output a voltage signal proportional to the strength of a magnetic field.
Reference numerals 2 and 3 denote base diffusion resistors (R2, R3) whose one ends are connected to a power supply (VCC), and reference numerals 4 and 5 have bases connected to the output terminals 1c and 1d of the Hall element 1, and collectors connected to the resistors R2 and R3, respectively. NPN type transistor (Q4, Q
5) and 6 are constant current sources, one end of which is connected to the emitters of the NPN transistors 4 and 5 and the other end of which is grounded. These R2, R3, Q4, Q5 and the constant current source 6 form a differential amplifier circuit. This differential amplifier circuit amplifies the Hall voltage V _H generated between the output terminals 1c and 1d of the Hall element.

Reference numerals 7 and 8 denote buffer circuits for amplifying the output signals appearing at the collectors of the NPN transistors 4 and 5, respectively, 9 denotes a base diffusion resistor (R9) provided at the output of the buffer circuit 7, and 10 denotes a + input as a base. An operational amplifier (op amp) whose negative input is connected to the diffusion resistor 9 and whose negative input is connected to the output of the buffer circuit 8.
Of the NPN transistor (Q11), 12 whose collector is connected to the base diffusion resistor 9 and whose one end is connected to the emitter of the NPN transistor 11 and whose other end is grounded, the same epitaxial layer as the Hall element. Is a resistor formed by using (hereinafter, referred to as "epi resistor"). The epi resistor 12 has input terminals 12a and 12b. Reference numeral 13 is an output terminal of the amplification circuit of this Hall IC.

Here, the epi resistance 12 has the same size and the same structure as the Hall element 1, and is configured so that the absolute value of the input resistance and its temperature characteristic are close to each other. FIG. 2 shows an example of the configuration and arrangement of the Hall element 1 and the epi resistance 12 as described above. As shown in the figure, the Hall element 1 and the epi resistor 12 are formed separately on a semiconductor substrate (not shown) via a separation film 21. Here, the gap between the Hall element 1 and the epi resistance 12 is very narrow. The input terminals 1a and 1b of the hall element 1 are provided so as to face each other. The same applies to the input terminals 12a and 12b of the epi resistor 12. In addition, when the input terminals 1a and 1b face each other,
The facing directions of the input terminals 12a and 12b are the same.
By adopting such a configuration, the currents flowing through the Hall element 1 and the epi resistance 12 are in the same direction, and therefore, the directions in which they flow with respect to the crystal axis of the semiconductor are also in the same direction. Therefore, these physical characteristics are very similar. Therefore, the absolute values of these input resistances and their temperature characteristics are similar to each other. Even if the directions of the currents flowing in the Hall element 1 and the epi resistance 12 are different, these temperature characteristics are close to each other.

Next, the operation will be described. In the circuit configuration as shown in FIG. 1, when a magnetic field is applied to the Hall element 1,
A Hall voltage V _H proportional to the magnetic field is generated between the output terminals 1c and 1d of the Hall element 1. _{V H = K H · (I} H · B / d) · f H = K H · (V / R IN) · (B / d) · f H where, V _H: Hall voltage, K _H: Hall coefficient , I _H : Hall element drive current, B: magnetic flux density, d: hall element thickness, f _H : coefficient depending on the shape of the hall element, V: applied voltage, R _IN : input resistance of the hall element 1.

Due to the Hall voltage V _H , a difference occurs in the collector currents I ₂ and I ₃ flowing through the NPN transistors 2 and ₃ . That is, when a magnetic field is applied so that the potential of the output terminal 1c among the output terminals 1c and 1d of the Hall element 1 becomes high, the collector current I ₂ becomes larger than the collector current I ₃ . Therefore, the voltage drop in the resistor 2 becomes larger than the voltage drop in the resistor 3, so that the input voltage of the buffer circuit 7 becomes higher than the input voltage of the buffer circuit 8.
Therefore, the output voltage of the buffer circuit 8 becomes lower than the output voltage of the buffer circuit 7. However, since the potentials of the two input terminals of the operational amplifier 10 can be regarded as the same potential, the base diffusion resistor 9 between the buffer circuit 7 and the + side input terminal of the operational amplifier 10 has the output voltage of the buffer circuits 7 and 8. The current I ₀ corresponding to the difference between the two flows in the direction of flowing into the collector of the NPN transistor 11.

Since the input voltage of the + input terminal of the operational amplifier 10 is larger than the input voltage of the − input terminal, the output of the operational amplifier 10 has a + potential. Therefore, the NPN transistor 11 is turned on, and the current I ₀ flows into the epi resistance 12 via the NPN transistor 11. The voltage generated by the current I ₀ flowing into the epi resistance 12 in this way becomes the output voltage of the amplifier circuit of the Hall IC.

Here, the current I ₀ is proportional to the Hall voltage V _H. When this proportional coefficient is α, I ₀ = αV _H = α · K _H · (V / R _IN ) · (B / d) · f _H. Further, when the output voltage appearing at the output terminal 13 and _{V 0 V 0 = I 0 R} E = α · K H · (R E / R IN) · V · (B / d) · f H wherein, R _E : Epi resistance.

By the way, since the Hall element 1 and the epi resistance 12 of these Hall ICs are arranged as shown in FIG. 2, the input resistance R _IN of the Hall element 1 and the input resistance R _E of the epi resistance 12 are the same absolute value. It has a value and its temperature coefficient is the same. Therefore, in the above equation, (R _E / R _IN )
Is constant regardless of the Hall IC and operating temperature. As can be seen from this, the variation in the input resistance value of the Hall element and the temperature change are canceled by the input resistance of the epi resistance, and the voltage appearing at the output terminal 13 is not affected by the temperature. Similarly, variations in absolute value of the input resistance of the Hall element, which occur for each Hall IC, are offset.

As described above, according to the first embodiment, since the variation in the input resistance value of the Hall element and the temperature change are canceled by the input resistance of the epi resistance having the same characteristic, the output voltage of the Hall IC is reduced. In the above, variations in the input resistance of the Hall element and variations in the resistance value caused by temperature changes are extremely small, and the magnetic flux density can be accurately measured.

The arrangement of the Hall element and the epi resistance is as follows.
The arrangement shown in FIGS. 3 to 6 is not limited to the arrangement shown in FIG.

FIG. 3 shows an arrangement in which two Hall elements 1 and two epi resistors 12 are close to each other. The arrangement of FIG. 3 is provided with two sets of the Hall element 1 and the epi resistance 12 of the arrangement shown in FIG. However, the arrangement of the Hall element 1-1 and the epi resistance 12-1 of one set is exactly the same as that of FIG. 2, but the arrangement of the Hall element 1-2 and the epi resistance 12-2 of the other set is equal to that of the current. The difference is that the flowing direction of I differs from that in the case of FIG. 2 by 90 °. These Hall elements 1-1 and 1-2 are connected in parallel with each other and used as the Hall element 1 in the circuit of FIG. The epi resistors 12-1 and 12-2 are connected in series and used as the epi resistors in the circuit of FIG. Epi resistors 12-1 and 12-2
Depending on the output range of the amplifier circuit, only one of them may be used. By connecting the two Hall elements in parallel in this manner, the effect that the offset voltage of the Hall elements is compensated and becomes smaller is further added.

FIG. 4 shows an example in which two sets of Hall elements 1 and epi resistors 12 are provided as in the case of FIG. This is different from the arrangement of FIG. 3 in that the positions of the pair of Hall elements 1-2 and the epi resistance 12-2 are different from each other.

FIG. 5 shows two sets of Hall element 1 and epi resistance 1.
2 is an example of a case where 2 are arranged radially around a certain point on the semiconductor substrate. As can be seen from the figure, Hall element 1
And the current in the epi resistance 12 flows toward the center point on the semiconductor substrate. In addition, the hall element 1 and the epi resistance 1
Contrary to the above case, the current in 2 may flow radially from the center point on the semiconductor substrate.

FIG. 6 shows four Hall elements 1-1 to 1-4.
Are arranged so as to surround one epi resistor 12. These four Hall elements 1-1 to 1-4 are arranged radially around a point on the semiconductor substrate, like the two Hall elements and the two epi resistors shown in FIG. These Hall elements 1-1 to 1-4 are connected in parallel with each other and used as one Hall element. Further, an epi resistor 12 is arranged in the central portion. Even if the number of the epi resistors 12 is one, the effect of temperature compensation can be obtained. In addition, epi resistance 1
2 may be further arranged around the Hall element 1 and those epi resistors connected in series may be used as the epi resistor 12.

In the Hall IC of the first embodiment, as shown in FIG.
~ Any arrangement can be adopted from the arrangements shown in Fig. 6. This also applies to Examples 2 and 3 described below.

Example 2. In the first embodiment, the voltage signal is transmitted using the two buffer circuits 7 and 8 and converted into the current by the resistor 9. It is conceivable to use a transistor grounded collector circuit (emitter follower) as the buffer circuit. However, if this is simply applied to the circuit of the first embodiment, the collector currents of the transistors of the respective buffer circuits are different, and thus the base-emitter voltage (V _BE ) is different. Therefore, an error occurs in the transmission of the Hall voltage.

Therefore, when the emitter follower is used, the circuit configuration shown in FIG. 2 may be used. In the figure, 16 is a PNP transistor that receives the output of the NPN transistor 4, and 17 is a PNP transistor that receives the output of the NPN transistor 5. Reference numerals 6b and 6c are current sources connected to the emitters of the NPN type transistors 17 and 16, respectively. Each of the PNP type transistors 17 and 18 is an emitter follower, and the output of each of the PNP type transistors 17 and 18 is connected to the operational amplifier 10 via a resistor.
Is input to the-input terminal and the + input terminal of. Reference numeral 18 denotes a base diffusion resistance (R
16) and 19 are NPN transistors whose output current from the PNP transistor 16 is input to the collector.

The NPN transistor 19 has a base and an emitter connected in parallel with the NPN transistor 11. The sum of the currents output by the transistors 11 and 19 is supplied to the epi resistance 12 to output the output voltage V _0.
Is obtained. The other Hall elements 1 and the like are the same as those shown in the first embodiment.

Next, the operation will be described. Hall element 1
The operation from to the transistors 4 and 5 is the same as that of the first embodiment. Receiving the output of the differential amplifier, an emitter follower by NPN-type transistors 16 and 17 outputs a voltage corresponding to the Hall voltage V _H. Example 1
Similarly to the case of, the current I _0a flows from the emitter of the transistor 17 to the collector of the transistor 11 corresponding to the Hall voltage V _H.

At the same time, the NPN transistor 11
A current I _0b flows from the emitter of the transistor 16 to the collector of the transistor 19 in accordance with the current flowing in the transistor 16.
This point is different from the case of the first embodiment. In this way, when the current from the transistor 16 is passed through the output circuit, the current I ₅ flowing through the collector of the transistor 16 becomes smaller and becomes equal to the current I ₄ flowing through the collector of the transistor 17. As a result, the base-emitter voltage V _BE of the transistors 16 and 17 becomes equal, and no error occurs.
Here, the output voltage V ₀ is obtained from the currents I _0a and I _0b and the epi resistance R _E , as in the case of the first embodiment.

As described above, according to the second embodiment, since the collector currents of the two transistors forming the emitter follower are the same, it is possible to suppress the generation of the error voltage due to the difference in the collector currents, and the buffer current. A simple emitter follower can be used as the circuit.

Example 3. In the above Examples 1 and 2,
Although the output of the differential amplifier circuit is first received by the buffer circuit and then input to the operational amplifier, it may be directly input to the operational amplifier without passing through the buffer circuit.

FIG. 8 shows a circuit configuration according to the third embodiment. In the figure, the output of the first stage differential amplifier circuit composed of the base diffusion resistors 2 and 3, the NPN transistors 4 and 5, and the constant current source 6 is directly input to the next stage amplifier 10 without passing through the buffer circuit. To be done.

In the circuit of FIG. 8, the currents flowing through the collectors of the NPN transistors 4 and 5 have different values according to the Hall voltage V _H. However, the operational amplifier 10 and the NPN-type transistor 11 shunt the difference current I ₀ of these currents from the collector of the NPN-type transistor 5 so that these currents have the same value, and make the currents flow into the epi resistance 12 as they are. Since the difference current I _{0 at} this time is proportional to the Hall voltage V _H , the voltage V ₀ appearing at the output terminal 13 is proportional to the Hall voltage V _H.

In the cases of Examples 1 and 2, the Hall voltage V _H obtained by the Hall element 1 is converted into a current flowing in the transistors 4 and 5, and this current is converted into a voltage and then supplied to the buffer circuits 7 and 8. However, a complicated signal conversion is performed such that the difference between the output voltages of the buffer circuits 7 and 8 is converted into a current again, and then the current is supplied to the epi resistance to be converted into a voltage again. On the other hand, according to the third embodiment, since such a complicated procedure is not taken, it is possible to reduce the error that occurs.

Further, according to the third embodiment, since the potential at the point A and the potential at the point B in FIG. 8 are equal to each other, the relativity of the base diffusion resistors 2 and 3 and the relativity of the NPN type transistors 4 and 5 are high. Also, there is an effect that the performance is extremely improved and the accuracy of this differential amplifier circuit is improved.

[0043]

As described above, according to the first aspect of the invention, the Hall element that outputs the voltage corresponding to the strength of the applied magnetic field and the differential amplifier that amplifies the output voltage of the Hall element are provided. An amplifier that outputs a current corresponding to the strength of a magnetic field applied based on the output of the differential amplifier; and the amplifier is formed on the semiconductor substrate on which the hall element is formed in the vicinity of the hall element. Since the resistor which generates the voltage corresponding to the strength of the magnetic field applied upon receiving the output current is provided, the voltage fluctuation caused by the temperature change is canceled by the Hall element and the resistor. Therefore, even if the characteristics of the Hall element change due to the temperature change, the output fluctuation due to this change can be compensated and the magnetic flux density can be measured correctly.

According to a second aspect of the present invention, the amplifier has a first collector-grounded amplifier circuit which receives the first output of the differential amplifier and a second output of the differential amplifier. The second grounded collector amplifier circuit for inputting, and the first
And an operational amplifier which receives the output of the collector-grounded amplifier circuit and the output of the second collector-grounded amplifier circuit as input, and operates based on the output of the operational amplifier to divide the current from the first collector-grounded amplifier circuit. The output of the amplifier is composed of a first transistor for outputting and a second transistor for operating based on the output of the operational amplifier and shunting the current from the second grounded collector amplifier circuit to output the current. Since the output of the first transistor and the output of the second transistor are set to the sum, the amplifier circuit can be further simply configured by the collector-grounded amplifier circuit, and the current flowing through the collector-grounded amplifier circuit becomes the same, resulting in a difference in current. It is possible to suppress the generation of an error voltage due to.

According to a third aspect of the present invention, the amplifier is operated based on the output of the operational amplifier and the output of the differential amplifier, and the output terminal of the differential amplifier is operated. Since it is composed of a transistor that splits and outputs a current from one side, the amplifier circuit can be further simply configured and the conversion error can be reduced.

Further, according to the invention of claim 4, since the resistor is formed by a structure similar to that of the hall element so that the characteristics thereof are similar to those of the hall element, the semiconductor to be formed is further formed. Even if the characteristics of the Hall elements of the device vary, the fluctuations due to the variations cancel out and the output voltage stabilizes.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a Hall IC according to a first embodiment of the present invention.

FIG. 2 is an example of an arrangement of Hall elements and epi resistors on a semiconductor substrate according to Examples 1 to 3 of the present invention.

FIG. 3 is another example of arrangement of Hall elements and epi resistors on a semiconductor substrate according to Examples 1 to 3 of the present invention.

FIG. 4 is another example of arrangement of Hall elements and epi resistors on a semiconductor substrate according to Examples 1 to 3 of the present invention.

FIG. 5 is another example of the arrangement of the Hall element and the epi resistance on the semiconductor substrate according to the first to third embodiments of the present invention.

FIG. 6 is another example of arrangement of Hall elements and epi resistors on a semiconductor substrate according to Examples 1 to 3 of the present invention.

FIG. 7 is a circuit diagram of a Hall IC according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a Hall IC according to a third embodiment of the present invention.

FIG. 9 shows a functional block diagram of a conventional Hall IC.

[Explanation of symbols]

1 Hall element, 2, 3 resistance, 4, 5 NPN type transistor, 6 constant current source, 7, 8 buffer circuit, 9
Resistance, 10 operational amplifier, 11 NPN type transistor, 12 epi resistance, 16, 17 PNP type transistor, 18 resistance, 19 NPN type transistor.

Claims (4)

[Claims] 1. A Hall element that outputs a voltage corresponding to the strength of an applied magnetic field, a differential amplifier that amplifies the output voltage of the Hall element, and a magnetic field applied based on the output of the differential amplifier. An amplifier that outputs a current corresponding to the strength, and is formed on the semiconductor substrate on which the hall element is formed in the vicinity of the hall element, and corresponds to the strength of the magnetic field applied by receiving the output current of the amplifier. A semiconductor magneto-electric conversion device having a resistor that generates a voltage to operate. 2. A first collector-grounded amplifier circuit for inputting the first output of the differential amplifier, and a second collector-grounded amplifier for inputting the second output of the differential amplifier to the amplifier. A circuit, an operational amplifier that receives the output of the first collector-grounded amplifier circuit and the output of the second collector-grounded amplifier circuit, and the first collector-grounded amplifier circuit that operates based on the output of the operational amplifier. And a second transistor that operates based on the output of the operational amplifier and that divides and outputs the current from the second common-collector ground amplifier circuit, 2. The semiconductor magnetoelectric conversion device according to claim 1, wherein the output of the amplifier is the sum of the output of the first transistor and the output of the second transistor. 3. The amplifier operates based on an operational amplifier that receives the output of the differential amplifier and the output of the operational amplifier, and divides and outputs a current from one of the output terminals of the differential amplifier. The semiconductor magnetoelectric conversion device according to claim 1, wherein the semiconductor magnetoelectric conversion device comprises a transistor. 4. The resistor according to claim 1, wherein the resistor has a structure similar to that of the Hall element so that the characteristics of the resistor are similar to those of the Hall element. Semiconductor magnetoelectric converter.