JPH08111494A - Surface mounting type semiconductor device - Google Patents
Surface mounting type semiconductor deviceInfo
- Publication number
- JPH08111494A JPH08111494A JP6245474A JP24547494A JPH08111494A JP H08111494 A JPH08111494 A JP H08111494A JP 6245474 A JP6245474 A JP 6245474A JP 24547494 A JP24547494 A JP 24547494A JP H08111494 A JPH08111494 A JP H08111494A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor device
- sealing body
- outer leads
- flexible film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、面実装型半導体装置に
関し、特に、実装基板の実装面上に形成された接続端子
の表面上にろう材を介在してその接続部が固着されるア
ウターリードを封止体の一側面に複数本配列した面実装
型半導体装置に適用して有効な技術に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface-mounting type semiconductor device, and more particularly, to an outer member in which a connecting portion is fixed on a surface of a connecting terminal formed on a mounting surface of a mounting board with a brazing material interposed therebetween. The present invention relates to a technique effectively applied to a surface-mounted semiconductor device in which a plurality of leads are arranged on one side surface of a sealing body.
【０００２】[0002]
【従来の技術】ＴＳＯＰ（Ｔhin Ｓmall Ｏut-line Ｐa
ckage)型の面実装型半導体装置は、樹脂封止体の互いに
対向する２つの側面(厚さ方向の側面)の夫々に複数本の
アウターリードを配列した２方向リード配列構造で構成
される。また、ＱＦＰ（ＱuadＦlat Ｐackage）型の面
実装型半導体装置は、樹脂封止体の４つの側面（厚さ方
向の側面）の夫々に複数本のアターリードを配列した４
方向リード配列構造で構成される。この種の面実装型半
導体装置のアウターリードはガルウィング形状で構成さ
れる。BACKGROUND OF THE INVENTION TSOP (T hin S mall O ut -line P a
The ckage) type surface mount semiconductor device has a two-way lead arrangement structure in which a plurality of outer leads are arranged on each of two side surfaces (side surfaces in the thickness direction) of the resin encapsulating body which face each other. Further, QFP (Q uad F lat P ackage) type surface mounting type semiconductor device, an array of a plurality of Atarido to each of the four sides of the resin sealing body (thickness direction of the side face) 4
It is composed of a directional read array structure. The outer leads of this type of surface mount semiconductor device are formed in a gull wing shape.
【０００３】前記面実装型半導体装置のアウターリード
は、製造プロセスにおいて、リードフレームから切断さ
れ、ガルウィング形状に成形される。リードフレーム
は、例えばＦｅ−Ｎｉ系合金、Ｃｕ系合金等の金属材料
からなる板材にエッチング加工又はプレス打ち抜き加工
を施すことにより形成される。In the manufacturing process, the outer leads of the surface-mounted semiconductor device are cut from the lead frame and formed into a gull wing shape. The lead frame is formed, for example, by subjecting a plate material made of a metal material such as Fe—Ni based alloy or Cu based alloy to etching or press punching.
【０００４】前記面実装型半導体装置は、実装工程にお
いて、例えばメモリーボード、ＣＰＵボート等の実装基
板の実装面上に実装される。面実装型半導体装置のアウ
ターリードは、実装基板の実装面上に配置された接続端
子の表面上にろう材(半田材)を介在してその接続部が固
着され、電気的及び機械的に接続される。実装基板は、
例えば絶縁性の耐熱ガラスポリイミド系樹脂基板の表面
に配線が施され、この樹脂基板を複数枚積み重ねた多層
配線構造(又は単層配線構造)で構成される。In the mounting process, the surface-mounted semiconductor device is mounted on the mounting surface of a mounting board such as a memory board or a CPU board. The outer leads of a surface-mount type semiconductor device are electrically and mechanically connected to each other by fixing the connection part with a brazing material (solder material) on the surface of the connection terminals arranged on the mounting surface of the mounting board. To be done. The mounting board is
For example, the surface of an insulating heat-resistant glass-polyimide resin substrate is provided with wiring, and a plurality of resin substrates are stacked to form a multilayer wiring structure (or a single-layer wiring structure).
【０００５】[0005]
【発明が解決しようとする課題】前記実装基板の実装面
上に面実装型半導体装置を実装した後、環境試験(温度
サイクル)下での温度変化、実際の使用環境下での温度
変化、装置に組み込んだ時の組立歪み等により、反り、
ねじれ等の変形が実装基板に生じる。このため、実装基
板の接続端子の表面とろう材との界面又はアウターリー
ドの接続部の表面とろう材との界面に応力が発生し、接
続端子の表面からアウターリードの接続部が剥離する問
題があった。この剥離現象は、面実装型半導体装置のア
ウターリードの微細化や封止体の薄型化に伴って顕著に
なる。After mounting the surface mounting type semiconductor device on the mounting surface of the mounting board, temperature change under an environmental test (temperature cycle), temperature change under actual use environment, device Warp due to assembly distortion when assembled in
Deformation such as twisting occurs in the mounting board. Therefore, stress is generated at the interface between the surface of the connection terminal of the mounting board and the brazing material or the interface between the surface of the connection portion of the outer lead and the brazing material, and the connection portion of the outer lead is separated from the surface of the connection terminal. was there. This peeling phenomenon becomes remarkable as the outer leads of the surface-mounted semiconductor device are miniaturized and the sealing body is made thinner.
【０００６】本発明の目的は、面実装型半導体装置にお
いて、実装基板の実装面上に実装した後、封止体の一側
面に配列された複数本のアウターリードの夫々の剥離を
防止することが可能な技術を提供することにある。An object of the present invention is to prevent, in a surface-mounting type semiconductor device, peeling of each of a plurality of outer leads arranged on one side surface of a sealing body after being mounted on the mounting surface of a mounting board. Is to provide the technology that can.
【０００７】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【０００９】実装基板の実装面上に配置された接続端子
の表面上にろう材を介在してその接続部が固着されるア
ウターリードを封止体の一側面に複数本配列した面実装
型半導体装置において、前記複数本のアウターリードの
夫々を可撓性フィルムの表面上に形成された金属薄膜で
構成し、前記複数本のアウターリードの夫々の接続部を
可撓性フィルムを介在して前記実装基板の実装面と向か
い合う前記封止体の実装面に支持する。A surface mount type semiconductor in which a plurality of outer leads, to which the connecting portions are fixed by interposing a brazing material on the surface of the connecting terminals arranged on the mounting surface of the mounting board, are arranged on one side surface of the sealing body. In the device, each of the plurality of outer leads is formed of a metal thin film formed on the surface of the flexible film, and the connecting portion of each of the plurality of outer leads is interposed by the flexible film. The mounting surface of the sealing body facing the mounting surface of the mounting substrate is supported.
【００１０】[0010]
【作用】上述した手段によれば、実装基板の実装面上に
面実装型半導体装置を実装した後、環境試験下での温度
変化、実際の使用環境下での温度変化、装置に組み込ん
だ時の組立歪み等による実装基板の変形で接続端子の表
面とろう材との界面又はアウターリードの接続部の表面
とろう材との界面に発生する応力を可撓性フィルムの撓
みで吸収し、緩和することができるので、封止体の一側
面に配列された複数本のアウターリードの夫々の剥離を
防止することができる。According to the above-mentioned means, after mounting the surface-mounting type semiconductor device on the mounting surface of the mounting board, the temperature change under the environmental test, the temperature change under the actual use environment, when the device is incorporated into the device. The stress generated at the interface between the surface of the connection terminal and the brazing material or the interface between the surface of the connecting part of the outer lead and the brazing material due to the deformation of the mounting substrate due to the assembly distortion of the flexible film is absorbed and relaxed. Therefore, the plurality of outer leads arranged on one side surface of the sealing body can be prevented from peeling off from each other.
【００１１】[0011]
【実施例】以下、本発明の構成について、実施例ととも
に説明する。なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。EXAMPLES The structure of the present invention will be described below with reference to examples. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
【００１２】（実施例１）本発明の実施例１である面実
装型半導体装置の概略構成を図２（封止体の一部を除去
した状態の平面図）及び図３（図１に示すＡ−Ａ切断線
の位置で切った断面図）に示す。(Embodiment 1) FIG. 2 (a plan view of a state in which a part of a sealing body is removed) and FIG. 3 (shown in FIG. 1) are schematic structures of a surface mounting type semiconductor device which is Embodiment 1 of the present invention. A sectional view taken along the line AA).
【００１３】図２及び図３に示すように、面実装型半導
体装置は可撓性フィルム２のペレット塔載面上に半導体
ペレット１を塔載する。半導体ペレット１は接着層（図
示せず）を介在して可撓性フィルム２のペレット塔載面
上に固定される。可撓性フィルム２は例えばテープ状
(長尺状)のものを所定の長さに切断したものである。こ
の可撓性フィルム２は例えば絶縁性のポリイミド系樹脂
で形成される。As shown in FIGS. 2 and 3, in the surface mounting type semiconductor device, the semiconductor pellets 1 are mounted on the pellet mounting surface of the flexible film 2. The semiconductor pellet 1 is fixed on the pellet mounting surface of the flexible film 2 with an adhesive layer (not shown) interposed. The flexible film 2 is, for example, a tape shape
It is a (long shape) cut into a predetermined length. The flexible film 2 is made of, for example, an insulating polyimide resin.
【００１４】前記半導体ペレット１は、例えば平面が方
形状に形成された単結晶珪素基板を主体に構成される。
半導体ペレット１の主面には、記憶回路システム、論理
回路システム、或はそれらの混合回路システムが塔載さ
れる。また、半導体ペレット１の主面上には、その方形
状の各辺に沿った最外周部に複数個の外部端子（ボンデ
ィングパッド）が配置される。この外部端子は半導体ペ
レット１に塔載された回路システムと電気的に接続され
る。The semiconductor pellet 1 is mainly composed of, for example, a single crystal silicon substrate having a rectangular plane.
A memory circuit system, a logic circuit system, or a mixed circuit system thereof is mounted on the main surface of the semiconductor pellet 1. Further, on the main surface of the semiconductor pellet 1, a plurality of external terminals (bonding pads) are arranged at the outermost peripheral portion along each side of the rectangular shape. This external terminal is electrically connected to the circuit system mounted on the semiconductor pellet 1.
【００１５】前記半導体ペレット１の最外周囲の外側に
は、その方形状の各辺に沿って複数本のインナーリード
３Ａが配置される。この複数本のインナーリード３Ａの
夫々は、半導体ペレット２の主面上に配置された複数個
の外部端子の夫々にボンディングワイヤ４を介して電気
的に接続される。ボンディングワイヤ４は例えばアルミ
ニウム(Ａｌ)ワイヤ、金(Ａｕ)ワイヤ、銅(Ｃｕ)ワイ
ヤ、或は金属ワイヤの表面に絶縁性樹脂を被覆した被覆
ワイヤ等で形成される。Outside the outermost periphery of the semiconductor pellet 1, a plurality of inner leads 3A are arranged along each side of the quadrangle. Each of the plurality of inner leads 3A is electrically connected to each of a plurality of external terminals arranged on the main surface of the semiconductor pellet 2 via a bonding wire 4. The bonding wire 4 is formed of, for example, an aluminum (Al) wire, a gold (Au) wire, a copper (Cu) wire, or a coated wire in which the surface of a metal wire is coated with an insulating resin.
【００１６】前記半導体ペレット１、可撓性フィルム
２、インナーリード３Ａ、ボンディングワイヤ４等は封
止体５で封止される。封止体５は、例えばフェノール系
硬化剤、シリコーンゴム及びフィラーが添加された絶縁
性のエポキシ系樹脂６で形成される。The semiconductor pellet 1, the flexible film 2, the inner leads 3A, the bonding wires 4 and the like are sealed with a sealing body 5. The sealing body 5 is formed of, for example, an insulative epoxy resin 6 to which a phenolic curing agent, silicone rubber, and a filler are added.
【００１７】前記封止体５は例えば平面形状が方形状に
形成される。封止体５の４つの側面５Ｂの(厚さ方向の
側面)夫々には複数本のアウターリード３Ｂが配列され
る。この複数本のアウターリード３Ｂの夫々は、封止体
５で封止された複数本のインナーリード３Ａの夫々と一
体に形成される。つまり、本実施例の面実装型半導体装
置は、封止体５の４つの側面５Ｂの夫々に複数本のアウ
ターリード３Ｂを配列した４方向リード配列構造で構成
される。The sealing body 5 is formed, for example, in a rectangular plane shape. A plurality of outer leads 3B are arranged on each of the four side surfaces 5B (side surfaces in the thickness direction) of the sealing body 5. Each of the plurality of outer leads 3B is integrally formed with each of the plurality of inner leads 3A sealed by the sealing body 5. That is, the surface mount semiconductor device according to the present embodiment has a four-direction lead arrangement structure in which a plurality of outer leads 3B are arranged on each of the four side surfaces 5B of the sealing body 5.
【００１８】前記インナーリード３Ａ、アウターリード
３Ｂの夫々は、可撓性フィルム２の表面上に形成された
金属薄膜で構成される。金属薄膜は例えばＣｕ膜で形成
される。このＣｕ膜は、可撓性フィルム２の表面に張り
付けられた圧延箔膜にエッチング加工を施し、所定の形
状にパターンニングすることにより形成される。なお、
金属薄膜は、可撓性フィルム２の表面上に金属を堆積し
た堆積膜で形成してもよい。このように構成されるイン
ナーリード３Ａ、アウターリード３Ｂの夫々は、例えば
Ｆｅ−Ｎｉ系合金(例えばＮｉ含有量４２又は５０
［％］)、Ｃｕ系合金等の金属材料からなる板材にエッ
チング加工又はプレス打ち抜き加工を施して形成された
リードフレームのインナーリード、アウターリードに比
べて機械的強度が小さいので柔軟性に優れている。Each of the inner lead 3A and the outer lead 3B is composed of a metal thin film formed on the surface of the flexible film 2. The metal thin film is formed of, for example, a Cu film. This Cu film is formed by etching the rolled foil film attached to the surface of the flexible film 2 and patterning it into a predetermined shape. In addition,
The metal thin film may be formed by a deposited film in which a metal is deposited on the surface of the flexible film 2. Each of the inner lead 3A and the outer lead 3B configured in this way is made of, for example, an Fe-Ni alloy (for example, a Ni content of 42 or 50).
[%]), The mechanical strength of the lead frame formed by subjecting a plate material made of a metal material such as Cu-based alloy to etching or press punching is smaller than that of the inner lead and outer lead of the lead frame. There is.
【００１９】前記可撓性フィルム２は、図３及び図４
(要部斜視図)に示すように、封止体５の４つの側面５Ｂ
の夫々から引き出され、封止体５の側面５Ｂ及びその主
面５Ａと対向する実装面(裏面)５Ｃに密着される。つま
り、アウターリード３Ｂは封止体５の側面５Ｂ及びその
実装面５Ｃに沿って延在する。The flexible film 2 is shown in FIGS.
As shown in (perspective view of main part), four side surfaces 5B of the sealing body 5 are provided.
Of the above, and is closely attached to the side surface 5B of the sealing body 5 and the mounting surface (back surface) 5C facing the main surface 5A thereof. That is, the outer lead 3B extends along the side surface 5B of the sealing body 5 and the mounting surface 5C thereof.
【００２０】このように構成される面実装型半導体装置
は、図１(実装した状態の断面図)に示すように、実装基
板８の実装面８Ａ上に実装される。この面実装型半導体
装置は、封止体５の実装面５Ｃが実装基板８の実装面８
Ａと向かい合うように塔載される。The surface-mounted semiconductor device thus configured is mounted on the mounting surface 8A of the mounting substrate 8 as shown in FIG. 1 (a sectional view of the mounted state). In this surface mounting type semiconductor device, the mounting surface 5C of the sealing body 5 is the mounting surface 8 of the mounting substrate 8.
It is installed so as to face A.
【００２１】前記実装基板８は、例えば絶縁性の耐熱ガ
ラスポリイミド系樹脂基板の表面に配線が施され、この
樹脂基板を複数枚積み重ねた多層配線構造（又は単層配
線構造）で構成される。この実装基板８の実装面８Ａ上
には複数個の接続端子９が配置される。The mounting board 8 has a multilayer wiring structure (or a single-layer wiring structure) in which wiring is provided on the surface of an insulating heat-resistant glass-polyimide resin substrate and a plurality of the resin substrates are stacked. A plurality of connection terminals 9 are arranged on the mounting surface 8A of the mounting board 8.
【００２２】前記複数個の接続端子９の夫々の表面上に
はろう材１０を介在して面実装型半導体装置の複数本の
アウターリード３Ｂの夫々の接続部３Ｂ1 が固着され、
電気的及び機械的に接続される。ろう材は例えばＳｎ−
Ｐｂ系合金からなる半田材で形成される。On the respective surfaces of the plurality of connecting terminals 9, the connecting portions 3B 1 of the plurality of outer leads 3B of the surface mounting type semiconductor device are fixedly attached with the brazing material 10 interposed therebetween.
Electrically and mechanically connected. The brazing material is, for example, Sn-
It is formed of a solder material made of a Pb-based alloy.
【００２３】前記複数本のアウターリード３Ｂの夫々の
接続部３Ｂ1 は可撓性フィルム２を介在して封止体５の
実装面５Ｃに支持される。可撓性フィルム２は封止体
５、ろう材１０の夫々に比べて機械的強度が小さく、柔
軟性に優れているので、実装基板８の実装面８Ａ上に面
実装型半導体装置を実装した後、環境試験（温度サイク
ル）下での温度変化、実際の使用環境下での温度変化、
装置に組み込んだ時の組立歪み等による実装基板８の変
形(反り、ねじれ等)で接続端子９の表面とろう材１０と
の界面又はアウターリード３Ｂの接続部３Ｂ1 の表面と
ろう材１０との界面に発生する応力を吸収し、緩和する
ことができる。Each connecting portion 3B 1 of the plurality of outer leads 3B is supported by the mounting surface 5C of the sealing body 5 with the flexible film 2 interposed therebetween. Since the flexible film 2 has smaller mechanical strength and excellent flexibility as compared with the sealing body 5 and the brazing material 10, respectively, the surface mounting type semiconductor device is mounted on the mounting surface 8A of the mounting substrate 8. After that, temperature change under environmental test (temperature cycle), temperature change under actual use environment,
Deformation (warping, twisting, etc.) of the mounting substrate 8 caused by assembly distortion or the like when incorporated in the device causes an interface between the surface of the connection terminal 9 and the brazing material 10 or the surface of the connecting portion 3B 1 of the outer lead 3B and the brazing material 10. The stress generated at the interface of can be absorbed and relieved.
【００２４】このように、実装基板８の実装面８Ａ上に
配置された接続端子９の表面上にろう材１０を介在して
その接続部３Ｂ1 が固着されるアウターリード３Ｂを封
止体５の４つの側面５Ｂの夫々に複数本配列した４方向
リード配列構造の面実装型半導体装置において、前記複
数本のアウターリード３Ｂの夫々を可撓性フィルム２の
表面上に形成された金属薄膜で構成し、前記複数本のア
ウターリード３Ｂの夫々の接続部３Ｂ1 を可撓性フィル
ム２を介在して前記実装基板８の実装面８Ａと向かい合
う前記封止体５の実装面５Ｃに支持する。As described above, the outer lead 3B, to which the connecting portion 3B 1 is fixed via the brazing material 10 on the surface of the connecting terminal 9 arranged on the mounting surface 8A of the mounting substrate 8, is sealed with the sealing body 5. In the surface-mounting type semiconductor device having a four-way lead arrangement structure in which a plurality of wires are arranged on each of the four side surfaces 5B, each of the plurality of outer leads 3B is formed of a metal thin film formed on the surface of the flexible film 2. Each of the connecting portions 3B 1 of the plurality of outer leads 3B is supported by the mounting surface 5C of the sealing body 5 facing the mounting surface 8A of the mounting substrate 8 with the flexible film 2 interposed therebetween.
【００２５】この構成により、実装基板８の実装面８Ａ
上に面実装型半導体装置を実装した後、環境試験(温度
サイクル)下での温度変化、実際の使用環境下での温度
変化、装置に組み込んだ時の組立歪み等による実装基板
８の変形(反り、ねじれ等)で接続端子９の表面とろう材
１０との界面又はアウターリード３Ｂの接続部３Ｂ1 の
表面とろう材１０との界面に発生する応力を吸収し、緩
和することができるので、封止体５の４つの側面５Ｂの
夫々に配列された複数本のアウターリード３Ｂの夫々の
剥離を防止することができる。With this structure, the mounting surface 8A of the mounting substrate 8 is
After mounting the surface-mounting type semiconductor device on the top, deformation of the mounting substrate 8 due to temperature change under environmental test (temperature cycle), temperature change under actual use environment, assembly distortion when assembled in the device ( (Warp, twist, etc.) can absorb and relax the stress generated at the interface between the surface of the connection terminal 9 and the brazing material 10 or the interface between the surface of the connecting portion 3B 1 of the outer lead 3B and the brazing material 10. It is possible to prevent the plurality of outer leads 3B arranged on each of the four side surfaces 5B of the sealing body 5 from peeling off.
【００２６】（実施例２）本発明の実施例２である面実
装型半導体装置の概略構成を図５（封止体の一部を除去
した状態の要部平面図）及び図６(要部斜視図)に示す。(Embodiment 2) A schematic structure of a surface mounting type semiconductor device which is Embodiment 2 of the present invention is shown in FIG. 5 (a plan view of a main part with a part of a sealing body removed) and FIG. 6 (main part). (Perspective view).
【００２７】図５及び図６に示すように、面実装型半導
体装置は、封止体５の４つの側面５Ｂの夫々に複数本の
アウターリード３Ｂを配列した４方向リード配列構造で
構成される。この複数本のアウターリード３Ｂの夫々
は、前述の実施例１と同様に、可撓性フィルム２の表面
上に形成された金属薄膜で構成され、封止体５の側面５
Ｂ及びその実装面５Ｃに沿って延在する。複数本のアウ
ターリード３Ｂの夫々の接続部３Ｂ1 は、可撓性フィル
ム２を介在して封止体５の実装面５Ｃに支持される。As shown in FIGS. 5 and 6, the surface mount semiconductor device has a four-direction lead arrangement structure in which a plurality of outer leads 3B are arranged on each of the four side surfaces 5B of the sealing body 5. . Each of the plurality of outer leads 3B is made of a metal thin film formed on the surface of the flexible film 2 as in the first embodiment, and the side surface 5 of the sealing body 5 is formed.
It extends along B and its mounting surface 5C. The respective connecting portions 3B 1 of the plurality of outer leads 3B are supported on the mounting surface 5C of the sealing body 5 with the flexible film 2 interposed therebetween.
【００２８】前記可撓性フィルム２のアウターリード３
Ｂ間にはスリット２Ａが設けられている。このスリット
２Ａはアウターリード３Ｂの延在方向に沿って形成され
る。このように、可撓性フィルム２のアウターリード３
Ｂ間に、このアウターリード３Ｂの延在方向に沿ってス
リット２Ａを設けることにより、実装基板(８)の実装面
(８Ａ)上に面実装型半導体装置を実装した後のフラック
ス洗浄工程において、実装基板(８)の実装面(８Ａ)上に
配置された接続端子(９)の表面上にろう材（１０）を介
在してアウターリード３Ｂの接続部３Ｂ1 が固着された
各接続部に、可撓性フィルム２のスリット２Ａを通して
洗浄液を供給することができるので、各接続部のフラッ
クス洗浄を確実に行うことができる。Outer leads 3 of the flexible film 2
A slit 2A is provided between B. The slit 2A is formed along the extending direction of the outer lead 3B. Thus, the outer leads 3 of the flexible film 2
By providing the slit 2A between the B and along the extending direction of the outer lead 3B, the mounting surface of the mounting substrate (8) is mounted.
In the flux cleaning step after mounting the surface mounting type semiconductor device on (8A), the brazing material (10) is provided on the surface of the connection terminal (9) arranged on the mounting surface (8A) of the mounting board (8). Since the cleaning liquid can be supplied to each connection portion to which the connection portion 3B 1 of the outer lead 3B is fixed via the slit 2A of the flexible film 2, the flux cleaning of each connection portion must be ensured. You can
【００２９】また、温度変化による可撓性フィルム２の
リード配列方向（アウターリード３Ｂの配列方向）の膨
張、収縮の割合を低減することができるので、可撓性フ
ィルム２の膨張、収縮によるアウターリード３Ｂの変形
を防止することができる。Further, since it is possible to reduce the rate of expansion and contraction of the flexible film 2 in the lead arrangement direction (the arrangement direction of the outer leads 3B) due to the temperature change, the outer due to the expansion and contraction of the flexible film 2. It is possible to prevent the lead 3B from being deformed.
【００３０】（実施例３）本発明の実施例３である面実
装型半導体装置の概略構成を図７（断面図）に示す。(Embodiment 3) FIG. 7 (cross-sectional view) shows a schematic structure of a surface mounting type semiconductor device which is Embodiment 3 of the present invention.
【００３１】図７に示すように、面実装型半導体装置
は、封止体５の４つの側面５Ｂの夫々に複数本のアウタ
ーリード３Ｂを配列した４方向リード配列構造で構成さ
れる。この複数本のアウターリード３Ｂの夫々は、前述
の実施例１と同様に、可撓性フィルム２の表面上に形成
された金属薄膜で構成され、その夫々の接続部３Ｂ1 は
可撓性フィルム２を介在して封止体５の実装面５Ｃに支
持される。As shown in FIG. 7, the surface mount semiconductor device has a four-direction lead arrangement structure in which a plurality of outer leads 3B are arranged on each of the four side surfaces 5B of the sealing body 5. Each of the plurality of outer leads 3B is composed of a metal thin film formed on the surface of the flexible film 2 as in the case of the above-described first embodiment, and each of the connecting portions 3B 1 has a flexible film. It is supported by the mounting surface 5C of the sealing body 5 with the interposition of 2.
【００３２】前記可撓性フィルム２は、封止体５の４つ
の側面５Ｂの夫々から引き出され、封止体５の実装面５
Ｃ側に折り返されている。この封止体５の側面５Ｂと可
撓性フィルム２との間には隙間７Ａが設けられている。
このように、封止体５の側面５Ｂと可撓性フィルム２と
の間に隙間７Ａを設けることにより、温度変化によるア
ウターリード３Ｂの延在方向の膨張、収縮に伴い可撓性
フィルム２の膨張、収縮を追従させることができるの
で、アウターリード３Ｂの変形を防止することができる
と共に、アウターリード３Ｂの断線を防止することがで
きる。The flexible film 2 is pulled out from each of the four side surfaces 5B of the sealing body 5, and is mounted on the mounting surface 5 of the sealing body 5.
It is folded back to the C side. A gap 7A is provided between the side surface 5B of the sealing body 5 and the flexible film 2.
In this way, by providing the gap 7A between the side surface 5B of the sealing body 5 and the flexible film 2, the flexible film 2 is expanded and contracted in the extending direction of the outer lead 3B due to temperature change. Since expansion and contraction can be followed, deformation of the outer lead 3B can be prevented, and disconnection of the outer lead 3B can be prevented.
【００３３】（実施例４）本発明の実施例４である面実
装型半導体装置の概略構成を図８（断面図）に示す。(Embodiment 4) FIG. 8 (cross-sectional view) shows a schematic structure of a surface mounting type semiconductor device which is Embodiment 4 of the present invention.
【００３４】図８に示すように、面実装型半導体装置
は、封止体５の４つの側面５Ｂの夫々に複数本のアウタ
ーリード３Ｂを配列した４方向リード配列構造で構成さ
れる。この複数本のアウターリード３Ｂの夫々は、前述
の実施例１と同様に、可撓性フィルム２の表面上に形成
された金属薄膜で構成され、封止体５の側面５Ｂ及びそ
の実装面５Ｃに沿って延在する。複数本のアウターリー
ド３Ｂの夫々の接続部３Ｂ1 は可撓性フィルム２を介在
して封止体５の実装面５Ｃに支持される。As shown in FIG. 8, the surface-mounted semiconductor device has a four-direction lead arrangement structure in which a plurality of outer leads 3B are arranged on each of the four side surfaces 5B of the sealing body 5. Each of the plurality of outer leads 3B is made of a metal thin film formed on the surface of the flexible film 2 as in the first embodiment, and the side surface 5B of the sealing body 5 and its mounting surface 5C are formed. Extend along. The respective connecting portions 3B 1 of the plurality of outer leads 3B are supported by the mounting surface 5C of the sealing body 5 with the flexible film 2 interposed therebetween.
【００３５】前記封止体５は、その側面５Ｂとその実装
面５Ｃとが交わる角を複数本のアウターリード３Ｂが配
列されたリード配列の方向に沿って除去した形状で構成
される。例えば本実施例において、封止体５は、側面５
Ｂと実装面５Ｃとの間に段差部を形成し、側面５Ｂと実
装面５Ｃとが交わる角を除去した形状で構成される。な
お、封止体５の形状は側面５Ｂと実装面５Ｃが交わる角
に面取り加工を施した形状で構成してもよい。The sealing body 5 has a shape in which the corner where the side surface 5B and the mounting surface 5C intersect is removed along the direction of the lead arrangement in which a plurality of outer leads 3B are arranged. For example, in this embodiment, the sealing body 5 has the side surface 5
A stepped portion is formed between B and the mounting surface 5C, and the corners where the side surface 5B and the mounting surface 5C intersect are removed. The shape of the sealing body 5 may be configured by chamfering the corner where the side surface 5B and the mounting surface 5C intersect.
【００３６】このように、封止体５の側面５Ｂとその実
装面５Ｃとが交わる角を複数本のアウターリード３Ｂが
配列されたリード配列の方向に沿って除去した形状で封
止体５を構成することにより、封止体５の角部と可撓性
フィルム２との間に隙間７Ｂを形成することができるの
で、この封止体５の角部での可撓性フィルム５の亀裂に
よるアウターリード３Ｂの断線を防止することができ
る。As described above, the sealing body 5 is formed in a shape in which the corner where the side surface 5B of the sealing body 5 intersects with the mounting surface 5C is removed along the direction of the lead arrangement in which the plurality of outer leads 3B are arranged. With this configuration, the gap 7B can be formed between the corner of the sealing body 5 and the flexible film 2, and therefore the crack of the flexible film 5 at the corner of the sealing body 5 is caused. It is possible to prevent disconnection of the outer lead 3B.
【００３７】また、実装基板(８)の実装面上に面実装型
半導体装置を実装した後のフラック洗浄工程において、
実装基板(８)の実装面(８Ａ)上に配置された接続端子
(９)の表面上にろう材（１０）を介在してアウターリー
ド３Ｂの接続部３Ｂ1 が固着された各接続部に、隙間７
Ｂを通して洗浄液を供給することができるので、各接続
部のフラックス洗浄を確実に行うことができる。In the flack cleaning step after mounting the surface mounting type semiconductor device on the mounting surface of the mounting board (8),
Connection terminals arranged on the mounting surface (8A) of the mounting board (8)
On the surface of (9), a gap 7 is formed at each connection part where the connection part 3B 1 of the outer lead 3B is fixed with the brazing material (10) interposed.
Since the cleaning liquid can be supplied through B, the flux cleaning of each connection portion can be reliably performed.
【００３８】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３９】例えば、本発明は２方向リード配列構造の
面実装型半導体装置に適用できる。For example, the present invention can be applied to a surface mounting type semiconductor device having a two-way lead arrangement structure.
【００４０】また、本発明は１方向リード配列方向の面
実装型半導体装置に適用できる。Further, the present invention can be applied to a surface mounting type semiconductor device in the one-direction lead arrangement direction.
【００４１】また、本発明は、封止体をセラミックスで
形成したセラミックス封止型の面実装型半導体装置に適
用できる。Further, the present invention can be applied to a ceramics-sealed surface-mounting type semiconductor device in which the sealing body is made of ceramics.
【００４２】[0042]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４３】面実装型半導体装置において、実装基板の
実装面上に実装した後、封止体の一側面に配列された複
数本のアウターリードの夫々の剥離を防止できる。In the surface mounting type semiconductor device, after mounting on the mounting surface of the mounting substrate, it is possible to prevent the plurality of outer leads arranged on one side surface of the sealing body from peeling off from each other.
【図１】 本発明の実施例１である面実装型半導体装置
を実装基板の実装面上に実装した状態の要部断面図。FIG. 1 is a cross-sectional view of essential parts in a state in which a surface-mounted semiconductor device that is Embodiment 1 of the present invention is mounted on a mounting surface of a mounting board.
【図２】 面実装型半導体装置の封止体の一部を除去し
た状態の平面図。FIG. 2 is a plan view showing a state where a part of the sealing body of the surface-mounted semiconductor device is removed.
【図３】 図１に示すＡ−Ａ切断線の位置で切った断面
図。FIG. 3 is a sectional view taken along the line AA of FIG.
【図４】 面実装型半導体装置の要部斜視図。FIG. 4 is a perspective view of a main part of a surface-mounted semiconductor device.
【図５】 本発明の実施例２である面実装型半導体装置
の封止体の一部を除去した状態の要部平面図。FIG. 5 is a plan view of a main part of the surface mount semiconductor device according to the second embodiment of the present invention with a part of the sealing body removed.
【図６】 面実装型半導体装置の要部斜視図。FIG. 6 is a perspective view of a main part of a surface-mounted semiconductor device.
【図７】 本発明の実施例３である面実装型半導体装置
の断面図。FIG. 7 is a sectional view of a surface-mounted semiconductor device that is Embodiment 3 of the present invention.
【図８】 本発明の実施例４である面実装型半導体装置
の断面図。FIG. 8 is a sectional view of a surface-mounted semiconductor device that is Embodiment 4 of the present invention.
１…半導体ペレット、２…可撓性フィルム、２Ａ…スリ
ット、３Ａ…アウターリード、３Ｂ…アウターリード、
３Ｂ1 …接続部、４…ボンディングワイヤ、５…封止
体、５Ａ…主面、５Ｂ…側面、５Ｃ…実装面、６…樹
脂、７Ａ，７Ｂ…隙間、８…実装基板、９…接続端子、
１０…ろう材。1 ... Semiconductor pellet, 2 ... Flexible film, 2A ... Slit, 3A ... Outer lead, 3B ... Outer lead,
3B 1 ... Connection part, 4 ... Bonding wire, 5 ... Sealing body, 5A ... Main surface, 5B ... Side surface, 5C ... Mounting surface, 6 ... Resin, 7A, 7B ... Gap, 8 ... Mounting board, 9 ... Connection terminal ,
10 ... brazing material.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 斉藤 雅浩 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 (72)発明者 佐藤 仁久 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 (72)発明者 佐藤 幸弘 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 (72)発明者 青木 寿世 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 (72)発明者 星 彰郎 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Saito 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Nissei Tobu Semiconductor Co., Ltd. In the Eastern Eastern Semiconductor Co., Ltd. (72) Inventor Yukihiro Sato 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Nissho Eastern Eastern Semiconductor Ltd. Inside Semiconductor Co., Ltd. (72) Inventor Akio Hoshi 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture
Claims (4)
子の表面上にろう材を介在してその接続部が固着される
アウターリードを封止体の一側面に複数本配列した面実
装型半導体装置において、前記複数本のアウターリード
の夫々を可撓性フィルムの表面上に形成された金属薄膜
で構成し、前記複数本のアウターリードの夫々の接続部
を可撓性フィルムを介在して前記実装基板の実装面と向
かい合う前記封止体の実装面に支持したことを特徴とす
る面実装型半導体装置。1. A surface mount in which a plurality of outer leads, to which the connecting portions are fixed via a brazing material, are arranged on one side surface of a sealing body on the surface of a connecting terminal arranged on the mounting surface of a mounting board. In the semiconductor device, each of the plurality of outer leads is composed of a metal thin film formed on the surface of the flexible film, and the connecting portion of each of the plurality of outer leads is interposed by the flexible film. A surface mounting type semiconductor device, wherein the surface mounting semiconductor device is supported by a mounting surface of the sealing body that faces a mounting surface of the mounting substrate.
に、このアウターリードの延在方向に沿ってスリットを
設けたことを特徴とする請求項１に記載の面実装型半導
体装置。2. The surface mounting type semiconductor device according to claim 1, wherein slits are provided between the outer leads of the flexible film along the extending direction of the outer leads.
ムとの間に隙間を設けたことを特徴とする請求項１又は
請求項２に記載の面実装型半導体装置。3. The surface mount semiconductor device according to claim 1, wherein a gap is provided between one side surface of the sealing body and the flexible film.
わる角を前記複数本のアウターリードが配列されたリー
ド配列の方向に沿って除去した形状で前記封止体を構成
したことを特徴とする請求項１又は請求項２に記載の面
実装型半導体装置。4. The sealing body is formed in a shape in which a corner where one side surface of the sealing body intersects with a mounting surface thereof is removed along a direction of a lead arrangement in which the plurality of outer leads are arranged. The surface-mount type semiconductor device according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6245474A JPH08111494A (en) | 1994-10-11 | 1994-10-11 | Surface mounting type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6245474A JPH08111494A (en) | 1994-10-11 | 1994-10-11 | Surface mounting type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08111494A true JPH08111494A (en) | 1996-04-30 |
Family
ID=17134203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6245474A Pending JPH08111494A (en) | 1994-10-11 | 1994-10-11 | Surface mounting type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08111494A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5498604B1 (en) * | 2013-04-17 | 2014-05-21 | エムテックスマツムラ株式会社 | Hollow package for solid-state image sensor |
-
1994
- 1994-10-11 JP JP6245474A patent/JPH08111494A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5498604B1 (en) * | 2013-04-17 | 2014-05-21 | エムテックスマツムラ株式会社 | Hollow package for solid-state image sensor |
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