JPH0810735B2 - Ceramic package - Google Patents

Ceramic package

Info

Publication number
JPH0810735B2
JPH0810735B2 JP2246023A JP24602390A JPH0810735B2 JP H0810735 B2 JPH0810735 B2 JP H0810735B2 JP 2246023 A JP2246023 A JP 2246023A JP 24602390 A JP24602390 A JP 24602390A JP H0810735 B2 JPH0810735 B2 JP H0810735B2
Authority
JP
Japan
Prior art keywords
heat dissipation
silicon nitride
ceramic package
ceramic
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2246023A
Other languages
Japanese (ja)
Other versions
JPH04125952A (en
Inventor
博明 阪井
信介 矢野
隆雄 相馬
学 磯村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
Original Assignee
NGK Insulators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Insulators Ltd filed Critical NGK Insulators Ltd
Priority to JP2246023A priority Critical patent/JPH0810735B2/en
Priority to US07/760,145 priority patent/US5294750A/en
Priority to EP19910308469 priority patent/EP0476971B1/en
Priority to DE1991615408 priority patent/DE69115408T2/en
Publication of JPH04125952A publication Critical patent/JPH04125952A/en
Publication of JPH0810735B2 publication Critical patent/JPH0810735B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は熱伝導率の高い窒化珪素焼結体を、半導体チ
ップを搭載する基板に使用した、熱放散性に優れたセラ
ミックパッケージに関するものである。
Description: TECHNICAL FIELD The present invention relates to a ceramic package excellent in heat dissipation, which uses a silicon nitride sintered body having a high thermal conductivity as a substrate on which a semiconductor chip is mounted. is there.

(従来の技術) 半導体チップの高集積化や高速化に伴い、発生する熱
量が増大している。特にバイポーラ系の回路を有するチ
ップに関してその傾向は顕著で、近年はこれらのチップ
を搭載するパッケージとして、放熱性の優れたつまり熱
伝導率の良好な材料を使用したセラミックパッケージが
要求されるようになった。
(Prior Art) Along with the high integration and high speed of semiconductor chips, the amount of heat generated is increasing. This tendency is particularly remarkable for chips having a bipolar circuit, and in recent years, as a package for mounting these chips, a ceramic package using a material having excellent heat dissipation, that is, having good thermal conductivity is required. became.

従来このようなチップには、アルミナセラミックを材
料にしたセラミックパッケージが、樹脂を使用した基板
に比較して信頼性が高く熱放散性が良好な為に広く使用
されていた。例えば、第4図に示した様なアルミナセラ
ミック21の内部に金属導体配線を有し、搭載した半導体
チップ22と外部回路との接続端子用に多数の金属ピン23
が配列したピングリッドアレータイプのセラミックパッ
ケージや金属ピンの替わりに金属リードを使用したチッ
プキャリヤータイプのセラミックパッケージが知られて
いる。
Conventionally, a ceramic package made of alumina ceramic has been widely used for such a chip because of its high reliability and good heat dissipation compared with a substrate using a resin. For example, as shown in FIG. 4, the alumina ceramic 21 has metal conductor wiring inside, and a large number of metal pins 23 are used for connecting terminals of the mounted semiconductor chip 22 and external circuits.
There is known a pin grid array type ceramic package in which are arranged, and a chip carrier type ceramic package using metal leads instead of metal pins.

しかしながら、最近のますます増大する半導体チップ
の発熱量にたいしては、アルミナパッケージの放熱性で
は不充分であり、熱放散性の優れたパッケージが要望さ
れていた。また、アルミナパッケージは、半導体チップ
の材質であるシリコンの熱膨脹係数と整合しておらず、
チップに熱応力が生じたり、場合によっては熱ストレス
により破壊したりする問題があった。
However, with respect to the heat generation amount of semiconductor chips, which is increasing more and more recently, the heat dissipation of the alumina package is insufficient, and a package having excellent heat dissipation has been demanded. Also, the alumina package does not match the thermal expansion coefficient of silicon, which is the material of the semiconductor chip,
There has been a problem that the chip is thermally stressed or, in some cases, is broken by the thermal stress.

最近では熱伝導性がより優れ、また熱膨脹係数もシリ
コンと整合のとれた窒化アルミニウムセラミックが第4
図に示したパッケージのセラミック材料として使用され
始めている。しかしながら、窒化アルミニウムセラミッ
クは耐水性や耐アルカリ性などの耐環境性が悪い問題点
があった。また、ムライトセラミックも、熱膨脹係数が
シリコンと整合がとれているので第4図に示したパッケ
ージのセラミック材料として使用され始めている。しか
しながら、ムライトは熱伝導率が悪いのでパッケージの
熱放散性が悪い欠点があった。
Recently, aluminum nitride ceramics, which has better thermal conductivity and a coefficient of thermal expansion that matches that of silicon, are the fourth
It is beginning to be used as the ceramic material in the package shown. However, the aluminum nitride ceramic has a problem of poor environmental resistance such as water resistance and alkali resistance. In addition, mullite ceramics have begun to be used as the ceramic material of the package shown in FIG. 4 because the thermal expansion coefficient of silicon is matched with that of silicon. However, since mullite has a poor thermal conductivity, it has a drawback that the heat dissipation of the package is poor.

従って、最近ではこれらの問題点を解決する為、第1
図や第2図に示す様なパッケージが使用され始めてい
る。これらは、半導体チップが搭載される基板部分のみ
熱伝導率の高いセラミック基板を放熱用基板として使用
し、内部に回路配線を有する基板部分は、アルミナやム
ライトセラミックを使用する。
Therefore, recently, in order to solve these problems,
Packages such as those shown in Figures and 2 are beginning to be used. In these, a ceramic substrate having a high thermal conductivity is used as a heat dissipation substrate only in a substrate portion on which a semiconductor chip is mounted, and alumina or mullite ceramic is used in a substrate portion having circuit wiring inside.

これらのアルミナやムライトセラミックは工業的に大
量に使用されており安価であり、また製造プロセスも焼
成温度が低いことや、従来多量に使用されているこれら
セラミックを使用したパッケージの製造プロセスがその
まま使用出来るなどの利点もある。また、配線回路に高
速の信号が伝播したり、電源回路の抵抗を小さくしたい
場合には、Ag系、Cu系、Au系など導通抵抗の小さな導体
を使用する必要があるのでこれら低抵抗金属の融点以下
である1100℃以下で焼成する低温焼成セラミックが使用
される。さらに、絶縁材料にポリイミド系樹脂を使用
し、導体としてスパッタ、蒸着、メッキ等により薄膜を
形成しフォトリソグラフィーにより導体パターンを得る
ことにより配線回路とする場合もある。そして、半導体
チップが搭載される放熱用基板部分には、窒化アルミニ
ウムやBe0を添加して絶縁体とした炭化珪素基板が使用
されていた。
These alumina and mullite ceramics are industrially used in large quantities and are inexpensive, and the manufacturing process has a low firing temperature, and the manufacturing process of packages using these ceramics, which have been used in large quantities in the past, is used as is. It also has the advantage that it can be done. In addition, if a high-speed signal propagates in the wiring circuit or if you want to reduce the resistance of the power supply circuit, it is necessary to use a conductor with a low conduction resistance such as Ag, Cu, or Au, so these low resistance metal A low temperature fired ceramic that is fired below 1100 ° C., which is below the melting point, is used. Further, a wiring circuit may be formed by using a polyimide resin as an insulating material, forming a thin film as a conductor by sputtering, vapor deposition, plating or the like, and obtaining a conductor pattern by photolithography. Then, a silicon carbide substrate, which is made into an insulator by adding aluminum nitride or Be0, is used for the heat dissipation substrate portion on which the semiconductor chip is mounted.

放熱用基板と内部に回路配線を有する基板との接合に
は、ガラスによる接合や、AgやCuもしくはそれらの合金
にTiやZr金属を含んだ活性化金属による接合や、それぞ
れの基板に接合用に形成した導体を金属ろうにより接合
する場合や、金属ペーストの焼成により接合する場合が
ある。ただし、内部に回路配線を有する基板としてアル
ミナ基板を使用する場合は、放熱用基板の窒化アルミニ
ウムやBa0を添加して絶縁体とした炭化珪素基板と熱膨
脹係数が整合していないので、そのまま接合すると熱応
力によりクラックが生じたりするので中間の熱膨脹係数
を有するセラミックや金属の枠体を間に挟む場合もあ
る。
For joining the heat dissipation board and the board that has circuit wiring inside, join with glass, join with activated metal containing Ti or Zr metal in Ag, Cu or their alloys, or join with each board There is a case where the conductors formed in the above are joined by a metal braze, or a case where the conductors are joined by firing a metal paste. However, when an alumina substrate is used as a substrate having circuit wiring inside, the coefficient of thermal expansion does not match that of the silicon carbide substrate that has been made into an insulator by adding aluminum nitride or Ba0, which is a heat dissipation substrate. Since cracks may be generated due to thermal stress, a ceramic or metal frame having an intermediate coefficient of thermal expansion may be sandwiched between them.

また、低温焼成セラミックを内部に回路配設を有する
基板として使用する場合は、低温焼成セラミックの焼成
時に接合も同時に行うこともできる。また、ポリイミド
系樹脂を使用する場合は、放熱用基板上に直接ポリイミ
ド系樹脂と薄膜回路により配線回路を形成する。しかし
ながら、放熱用基板に使用する窒化アルミニウムは耐水
性や耐アルカリ性などの耐環境性がわるく、他の配線基
板部分の耐環境性は良いのにパッケージ全体の信頼性を
損ねていた。また、炭化珪素基板はセラミックの結晶粒
子の粒界部分しか絶縁性を有していないので、耐電圧が
低い問題点があり絶縁体の基板としては問題があった。
When the low temperature fired ceramic is used as a substrate having a circuit arrangement inside, the low temperature fired ceramics can be joined at the same time when firing. When a polyimide resin is used, a wiring circuit is directly formed on the heat dissipation substrate by the polyimide resin and a thin film circuit. However, the aluminum nitride used for the heat dissipation substrate has poor environment resistance such as water resistance and alkali resistance, and although the environment resistance of other wiring board parts is good, the reliability of the entire package is impaired. Further, since the silicon carbide substrate has an insulating property only in the grain boundary portion of the crystal grains of the ceramic, there is a problem that the withstand voltage is low, and there is a problem as an insulating substrate.

(発明が解決しようとする課題) 本発明では、窒化珪素焼結体を放熱用基板材料として
使用する。良く知られているように、窒化珪素は絶縁性
が非常に良く、耐環境性も優れている。また、熱膨脹係
数もアルミナの6〜7ppm/℃に比較するとシリコンの熱
膨脹係数3〜4ppm/℃に近く、より整合がとれているの
で、半導体チップを搭載した場合の信頼性も高い。しか
し、通常の窒化珪素は室温および高温での機械的強度を
追求した組成のものが多く、これらの熱伝導率は小さく
アルミナセラミックと同等であった。従って、第1図や
第2図のような構造にしても熱放散性の良いパッケージ
を得ることはできなかった。
(Problems to be Solved by the Invention) In the present invention, a silicon nitride sintered body is used as a substrate material for heat dissipation. As is well known, silicon nitride has very good insulating properties and excellent environmental resistance. Further, the coefficient of thermal expansion is closer to that of silicon, which is 3 to 4 ppm / ° C., as compared with that of alumina, which is 6 to 7 ppm / ° C., and is more closely matched, so that reliability when a semiconductor chip is mounted is also high. However, most of ordinary silicon nitrides have a composition that pursues mechanical strength at room temperature and high temperature, and their thermal conductivity is small, which is equivalent to that of alumina ceramics. Therefore, it was not possible to obtain a package having good heat dissipation even with the structure shown in FIGS.

本発明の目的は上述した課題を解消して、熱放散性の
良好なセラミックパッケージを提供しようとするもので
ある。
An object of the present invention is to solve the above-mentioned problems and to provide a ceramic package having good heat dissipation.

(課題を解決するための手段) 本発明のセラミックパッケージは、半導体チップを搭
載する窒化珪素からなる放熱基板と、この放熱基板と接
続し、内部に信号伝播用の配線回路および電源用の配線
回路を有する配線基板とからなり、前記放熱基板が、結
晶粒子を直線距離10μm中に20個以下含む窒化珪素から
なるとともに、アルミナ換算でアルミニウムを0.3重量
%以下含むことを特徴とするものである。
(Means for Solving the Problems) A ceramic package of the present invention is a heat dissipation board made of silicon nitride on which a semiconductor chip is mounted, and a wiring circuit for signal propagation and a power supply wiring circuit, which are connected to the heat dissipation board. And a heat dissipation substrate made of silicon nitride containing 20 or less crystal particles in a linear distance of 10 μm, and containing 0.3 wt% or less of aluminum in terms of alumina.

(作 用) 本発明では、アルミナ換算でアルミニウムを0.3重量
%以下含む窒化珪素焼結体で半導体チップが搭載される
基板が構成される。焼成後、この窒化珪素焼結体は直線
距離10μmに窒化珪素結晶粒子が20個以下含まれること
で特徴づけられる。窒化珪素焼結体は、通常焼結助剤と
して焼成中に液相を形成する成分が添加される。代表的
には、希土類の酸化物、アルカリ土類金属の酸化物、そ
の他金属酸化物が考えられる。
(Operation) In the present invention, a substrate on which a semiconductor chip is mounted is constituted by a silicon nitride sintered body containing 0.3% by weight or less of aluminum in terms of alumina. After firing, this silicon nitride sintered body is characterized by containing 20 or less silicon nitride crystal grains at a linear distance of 10 μm. A component forming a liquid phase during firing is usually added to a silicon nitride sintered body as a sintering aid. Typically, rare earth oxides, alkaline earth metal oxides, and other metal oxides are considered.

また、パッケージ用のセラミックに特有な添加物とし
てモリブデンやタングステン金属、もしくはこれらの酸
化物や化合物が着色用に添加される場合もある。
In addition, molybdenum, tungsten metal, or oxides or compounds thereof may be added for coloring as an additive peculiar to the ceramics for the package.

本発明には、アルミニウムが上記の限定量以下である
ならば、基本的にはどのような組成系の窒化珪素焼結体
にも適用できる。これは、窒化珪素焼結体の熱伝導率が
アルミニウム量にもっとも大きく影響されるためであ
る。
The present invention can be applied to a silicon nitride sintered body of basically any composition as long as the amount of aluminum is not more than the above-mentioned limited amount. This is because the thermal conductivity of the silicon nitride sintered body is most affected by the amount of aluminum.

本発明に使用する窒化珪素焼結体は、熱伝導率が40W/
mk以上、代表的には100W/mkとアルミナの20W/mk程度よ
りも充分に大きいので熱放散性の良いパッケージが得ら
れる。アルミナ換算でアルミニウムを0.3重量%を越え
る窒化珪素焼結体を使用するとセラミックの熱伝導率が
劣化した熱放散性の悪いパッケージになる。
The silicon nitride sintered body used in the present invention has a thermal conductivity of 40 W /
Since it is more than mk, typically 100 W / mk, which is much larger than about 20 W / mk of alumina, a package with good heat dissipation can be obtained. If a silicon nitride sintered body containing more than 0.3% by weight of aluminum in terms of alumina is used, the heat conductivity of the ceramic deteriorates, resulting in a package with poor heat dissipation.

また、本発明の窒化珪素基板材料は、耐環境性も非常
に優れており窒化アルミニウムで生ずるような問題はな
い。耐電圧特性も非常に良いので炭化珪素で生ずる様な
問題はない。
Further, the silicon nitride substrate material of the present invention is also extremely excellent in environmental resistance, and does not have the problem that aluminum nitride causes. Since the withstand voltage characteristic is also very good, there is no problem like silicon carbide.

(実施例) 第1図〜第3図は本発明のセラミックパッケージの一
例の構成を示す断面図である。第1図に示す例では、所
定の窒化珪素からなる放熱基板1上に金めっき層2を介
して半導体チップ3を搭載するとともに、ムライトから
なる配線基板4の配線導体5と半導体チップ3とをボン
ディングワイヤー6で接続し、さらに外部回路との接続
端子用に多数の金属ピン7を配列し、最後に放熱基板1
と配線基板5とを接続用活性金属8を介して接続しキャ
ップ9を設けたピングリットアレータイプのセラミック
パッケージを示している。第2図は金属ピン7を代りに
金属リード10を使用したチップキャリアタイプのセラミ
ックパッケージを示している。第3図は、配線基板4と
してポリイミド系樹脂中にAu薄膜で多層配線基板を使用
し、外部との接続を外部端子用の導体パッド11を使用し
たセラミックパッケージを示している。
(Embodiment) FIGS. 1 to 3 are sectional views showing the structure of an example of the ceramic package of the present invention. In the example shown in FIG. 1, the semiconductor chip 3 is mounted on the heat dissipation substrate 1 made of a predetermined silicon nitride via the gold plating layer 2, and the wiring conductor 5 and the semiconductor chip 3 of the wiring substrate 4 made of mullite are arranged. Connecting with the bonding wire 6, and arranging a large number of metal pins 7 for connecting terminals to the external circuit, and finally, the heat dissipation board 1
2 shows a pingrit array type ceramic package in which the wiring board 5 and the wiring board 5 are connected to each other through a connection active metal 8 and a cap 9 is provided. FIG. 2 shows a chip carrier type ceramic package using metal leads 10 instead of metal pins 7. FIG. 3 shows a ceramic package in which a multilayer wiring board made of Au thin film in a polyimide resin is used as the wiring board 4 and a conductor pad 11 for an external terminal is used for connection with the outside.

以下、実際の例について説明する。 Hereinafter, an actual example will be described.

実施例1 Al2O3含有量の異なる窒化珪素粉末に焼結助剤として
表1に示す希土類酸化物を添加し、水を加えて窒化珪素
玉石と樹脂製ポットを用いて湿式混合した。得られたス
ラリーをスプレードライヤにより乾燥造粒した。造粒粉
末を金型を使用して通常の乾式プレス成形により所定の
形状に成形した。成形体を9.5気圧の窒化雰囲気下で表
1に示すように、1750〜1950℃、1〜10時間焼成した。
得られた焼結体について、熱伝導率をレーザーフラッシ
ュ法により測定した。また、焼成体の窒化珪素粒子の数
を直線距離10μmあたりに存在する窒化珪素粒子の数か
ら求めた。粒子の個数は以下のようにして測定した。ま
ず、走査型電子顕微鏡にて、窒化珪素体の任意断面にお
ける微構造をSi3N4粒子を個々に識別できる倍率で写真
に撮った。次に、写真に直線を描き、直線が横切る粒子
の個数を計測した。粒子の数が1000個を越えるまでの視
野を変えて直線を引き、1000個の粒子を計測するのに要
した直線の総距離L(μm)から(1000/L)×10により
10μm当りの個数に換算した。例えば、1000個の粒子を
計測するのに直線500μmを要したとすれば、10μm当
りの個数は20個となる。焼結体中のAl2O3量を蛍光X線
分析法により測定した。これらの測定値を表1に示す。
また、熱膨脹係数はどの焼結体においても2〜4ppm/℃
であった。
Example 1 Rare earth oxides shown in Table 1 were added as a sintering aid to silicon nitride powders having different Al 2 O 3 contents, water was added, and the mixture was wet mixed with silicon nitride boulders using a resin pot. The obtained slurry was dried and granulated with a spray dryer. The granulated powder was molded into a predetermined shape by usual dry press molding using a mold. The molded body was fired in a nitriding atmosphere of 9.5 atm at 1750 to 1950 ° C. for 1 to 10 hours as shown in Table 1.
The thermal conductivity of the obtained sintered body was measured by the laser flash method. Further, the number of silicon nitride particles in the fired body was calculated from the number of silicon nitride particles present per linear distance of 10 μm. The number of particles was measured as follows. First, a microstructure of an arbitrary cross section of a silicon nitride body was photographed with a scanning electron microscope at a magnification at which Si 3 N 4 particles could be individually identified. Next, a straight line was drawn on the photograph, and the number of particles crossing the straight line was counted. By changing the field of view until the number of particles exceeds 1000, draw a straight line, and from the total distance L (μm) of the straight line required to measure 1000 particles, (1000 / L) × 10
It was converted to the number per 10 μm. For example, if a straight line of 500 μm is required to measure 1000 particles, the number of particles per 10 μm will be 20. The amount of Al 2 O 3 in the sintered body was measured by a fluorescent X-ray analysis method. Table 1 shows these measured values.
In addition, the coefficient of thermal expansion is 2 to 4 ppm / ° C for any sintered body.
Met.

得られた焼結体を半導体チップが搭載される放熱基板
として使用した。さらに内部に配線を有する基板として
は、絶縁材料にムライトセラミックを、導体にタングス
テンを使用した配線基板を使用した。これらの基板をAg
ろうTiを少量加えた活性化金属により接合した。このよ
うにして第1図に示す構造の半導体チップパッケージを
作成した。実際に半導体チップを搭載して発熱させ風速
4m/sの条件で空冷しパッケージの熱抵抗を測定した。そ
の結果を表1に示した。比較のため、アルミナを放熱基
板として同様の方法で測定した熱抵抗は22℃/Wであっ
た。
The obtained sintered body was used as a heat dissipation substrate on which a semiconductor chip was mounted. Further, as a substrate having wiring inside, a wiring substrate using mullite ceramic as an insulating material and tungsten as a conductor was used. Ag these substrates
Bonding was performed with an activated metal containing a small amount of brazing Ti. Thus, the semiconductor chip package having the structure shown in FIG. 1 was prepared. Actually mounted semiconductor chip to generate heat and wind speed
The thermal resistance of the package was measured after cooling with air under the condition of 4 m / s. The results are shown in Table 1. For comparison, the thermal resistance measured by the same method using alumina as a heat dissipation substrate was 22 ° C./W.

表1から、窒化珪素の放熱基板はアルミナと比較して
放熱特性が優れるのがわかる。また、窒化珪素において
も、直線距離10μmあたりに存在する窒化珪素粒子の数
が20個以下で、含有するAl2O3量が0.3wt%以下であれば
さらに優れるのがわかる。この理由は、直線距離10μm
あたりに存在する窒化珪素粒子の数が20個以上である
と、粒界での熱の散乱が大きくなって熱伝導率が低くな
るためと考えられ、Al2O3量が0.3wt%以上であると、窒
化珪素粒子内に固溶し、窒化珪素粒子の熱伝導度を低下
させるためと考えられる。
It can be seen from Table 1 that the heat dissipation substrate made of silicon nitride has excellent heat dissipation characteristics as compared with alumina. Further, in the case of silicon nitride as well, it can be seen that it is further excellent if the number of silicon nitride particles present per linear distance of 10 μm is 20 or less and the amount of Al 2 O 3 contained is 0.3 wt% or less. The reason for this is a linear distance of 10 μm
It is considered that if the number of silicon nitride particles present per area is 20 or more, the heat scattering at the grain boundaries becomes large and the thermal conductivity decreases, and if the amount of Al 2 O 3 is 0.3 wt% or more. It is considered that if there is, it forms a solid solution in the silicon nitride particles and reduces the thermal conductivity of the silicon nitride particles.

実施例2 コージェライト系組成のガラス粉末90重量%とアルミ
ナ粉末10重量%からなる低温焼成基板用のセラミック組
成混合粉末、アクリル系有機バインダー、可塑剤、トル
エンおよびアルコール系の溶剤をアルミナポットおよび
アルミナボールで良く混合しスラリーとした。さらに、
ドクターブレード法により0.3mm厚みのグリーンテープ
を作成した。
Example 2 Ceramic composition mixed powder for low temperature firing substrate consisting of 90% by weight of glass powder of cordierite composition and 10% by weight of alumina powder, acrylic organic binder, plasticizer, toluene and alcohol solvent in alumina pot and alumina. Mix well with a ball to make a slurry. further,
A green tape with a thickness of 0.3 mm was created by the doctor blade method.

Ag系粉末、アクリル系有機バインダーおよびテルピネ
オール系の有機溶剤を3本ローラーにより良く混練し印
刷用の導体ペーストにした。このペーストを使用して、
グリーンテープ上に導体配線パターンを印刷した。これ
らの導体パターンが印刷されたグリーンテープを、所定
の順番で重ねた後、実施例1と同様の方法で作成した窒
化珪素基板上に置き100℃、100kg/cm2の条件で圧力をか
け積層一体化した。各導体層の接続は、グリーンテープ
にパンチング等により成形したスルーホールに導体ペー
ストを充填して実現した。Air雰囲気で900℃焼成した。
その結果、第2図に示したように、窒化珪素基板上に、
低温焼成配線基板が接合した構造のパッケージが得られ
た。金属リードは、Au−Sn合金ろうにより接合した。
Ag-based powder, acrylic organic binder, and terpineol-based organic solvent were well kneaded with a three-roller to obtain a conductive paste for printing. Using this paste
A conductor wiring pattern was printed on the green tape. The green tapes on which these conductor patterns are printed are superposed in a predetermined order, placed on a silicon nitride substrate prepared by the same method as in Example 1, and laminated under pressure of 100 ° C. and 100 kg / cm 2. Integrated. The connection of each conductor layer was realized by filling a through hole formed by punching a green tape with a conductor paste. It was baked at 900 ° C in an air atmosphere.
As a result, as shown in FIG. 2, on the silicon nitride substrate,
A package having a structure in which low-temperature fired wiring boards are joined was obtained. The metal leads were joined by Au—Sn alloy brazing.

実施例3 実施例1と同様の方法で得た本発明の窒化珪素基板上
に、感光性ポリイミド系樹脂とAuスパッタ薄膜を使用し
フォトリソグラフィーにより導体パターンと層間導体パ
ターンを接続するビアホールを形成し多層配線回路を得
た。この結果、第3図に示すようなパッケージを得た。
Example 3 On a silicon nitride substrate of the present invention obtained by the same method as in Example 1, a via hole for connecting a conductor pattern and an interlayer conductor pattern was formed by photolithography using a photosensitive polyimide resin and an Au sputtered thin film. A multilayer wiring circuit was obtained. As a result, a package as shown in FIG. 3 was obtained.

(発明の効果) 以上詳細に説明したところから明らかなように、本発
明によれば、放熱基板を窒化珪素、好ましくはアルミナ
換算でアルミニウムを0.3重量%以下含み、結晶粒子を
直線距離10μm中に20個以下含む窒化珪素とすることに
より、熱放散特性を良好にできるため、熱放散性に優れ
たセラミックパッケージを得ることができる。
(Effects of the Invention) As is clear from the above description, according to the present invention, the heat dissipation substrate contains silicon nitride, preferably 0.3% by weight or less of aluminum in terms of alumina, and the crystal particles are contained in a linear distance of 10 μm. By including 20 or less of silicon nitride, heat dissipation characteristics can be improved, and thus a ceramic package having excellent heat dissipation can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図〜第3図はそれぞれ本発明のセラミックパッケー
ジの一例の構成を示す断面図、 第4図は従来のセラミックパッケージの一例の構成を示
す断面図である。 1……放熱基板、2……金めっき層 3……半導体チップ、4……配線基板 5……配線導体、6……ボンディングワイヤ 7……金属ピン、8……接続用活性化金属 9……キャップ、10……金属リード 11……導体パッド
1 to 3 are sectional views showing the structure of an example of the ceramic package of the present invention, and FIG. 4 is a sectional view showing the structure of an example of a conventional ceramic package. 1 ... Heat dissipation board, 2 ... Gold plating layer 3 ... Semiconductor chip, 4 ... Wiring board 5 ... Wiring conductor, 6 ... Bonding wire 7 ... Metal pin, 8 ... Connection activation metal 9 ... … Cap, 10 …… Metal lead 11 …… Conductor pad

───────────────────────────────────────────────────── フロントページの続き (72)発明者 磯村 学 愛知県名古屋市天白区表山3丁目150番地 日本ガイシ八事寮B―204 (56)参考文献 特開 昭62−232943(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Manabu Isomura 3-150 Omoteyama, Tenpaku-ku, Nagoya, Aichi NGK Yasushi Dormitory B-204 (56) References JP-A-62-232943 (JP, A)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体チップを搭載する窒化珪素からなる
放熱基板と、この放熱基板と接続し、内部に信号伝播用
の配線回路および電源用の配線回路を有する配線基板と
からなり、前記放熱基板が、結晶粒子を直線距離10μm
中に20個以下含む窒化珪素からなるとともに、アルミナ
換算でアルミニウムを0.3重量%以下含むことを特徴と
するセラミックパッケージ。
1. A heat dissipation board made of silicon nitride on which a semiconductor chip is mounted, and a wiring board connected to this heat dissipation board and having a wiring circuit for signal propagation and a wiring circuit for power supply therein. However, the linear distance of the crystal particles is 10 μm
A ceramic package which is made of silicon nitride containing 20 or less and contains 0.3% by weight or less of aluminum in terms of alumina.
【請求項2】前記配線回路基板の絶縁材料がムライトセ
ラミックからなる請求項1記載のセラミックパッケー
ジ。
2. The ceramic package according to claim 1, wherein the insulating material of the printed circuit board is mullite ceramic.
【請求項3】前記配線回路基板の絶縁材料が焼成温度11
00℃以下で焼成してなり、内部の配線導体がAg系、Cu
系、Au系からなる請求項1記載のセラミックパッケー
ジ。
3. The insulating material of the printed circuit board has a firing temperature of 11.
It is fired at a temperature below 00 ° C, and the internal wiring conductor is Ag-based, Cu
The ceramic package according to claim 1, wherein the ceramic package is made of an Au-based material.
【請求項4】前記配線回路基板の絶縁材料がポリイミド
系樹脂からなる請求項1記載のセラミックパッケージ。
4. The ceramic package according to claim 1, wherein the insulating material of the printed circuit board is a polyimide resin.
JP2246023A 1990-09-18 1990-09-18 Ceramic package Expired - Lifetime JPH0810735B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2246023A JPH0810735B2 (en) 1990-09-18 1990-09-18 Ceramic package
US07/760,145 US5294750A (en) 1990-09-18 1991-09-16 Ceramic packages and ceramic wiring board
EP19910308469 EP0476971B1 (en) 1990-09-18 1991-09-17 Ceramic packages and ceramic wiring board
DE1991615408 DE69115408T2 (en) 1990-09-18 1991-09-17 Ceramic packings and ceramic circuit boards

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2246023A JPH0810735B2 (en) 1990-09-18 1990-09-18 Ceramic package

Publications (2)

Publication Number Publication Date
JPH04125952A JPH04125952A (en) 1992-04-27
JPH0810735B2 true JPH0810735B2 (en) 1996-01-31

Family

ID=17142300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2246023A Expired - Lifetime JPH0810735B2 (en) 1990-09-18 1990-09-18 Ceramic package

Country Status (1)

Country Link
JP (1) JPH0810735B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996029736A1 (en) * 1995-03-20 1996-09-26 Kabushiki Kaisha Toshiba Silicon nitride circuit substrate
JP5612558B2 (en) * 2011-11-16 2014-10-22 日機装株式会社 Semiconductor package substrate and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714014B2 (en) * 1986-04-02 1995-02-15 住友電気工業株式会社 Substrate material for semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH04125952A (en) 1992-04-27

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