JPH09260544A - Ceramic circuit board and manufacture therefor - Google Patents

Ceramic circuit board and manufacture therefor

Info

Publication number
JPH09260544A
JPH09260544A JP6766696A JP6766696A JPH09260544A JP H09260544 A JPH09260544 A JP H09260544A JP 6766696 A JP6766696 A JP 6766696A JP 6766696 A JP6766696 A JP 6766696A JP H09260544 A JPH09260544 A JP H09260544A
Authority
JP
Japan
Prior art keywords
circuit board
conductor
aln
sintering
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6766696A
Other languages
Japanese (ja)
Inventor
Akihiro Horiguchi
昭宏 堀口
Mitsuo Kasori
光男 加曽利
Hiroyasu Sumino
裕康 角野
Fumio Ueno
文雄 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6766696A priority Critical patent/JPH09260544A/en
Publication of JPH09260544A publication Critical patent/JPH09260544A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Landscapes

  • Ceramic Products (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent generating of warp, wire breaking or so on by providing an insulating part having AIN as a main component and a conductive part which is comprised of specific elements and which contains AIN with specific range of weight%. SOLUTION: A circuit board 1 is provided at a part at least with an insulating part 2 having AIN as a main component and a conductive part 3 of which main component is one of W or Mo at least, which contains one or more elements selected from a group made of Ni, Co and Fe and which also contains AIN with 0.1-20weight%. Because the AIN which is a main component of the insulating layer 2 is added as a common material to the conductive layer 3, generating of warp is significantly prevented by achieving a absorption ratio matching between the insulating layer 2 and the conductive layer 3. At least one of element selected from alkaline earth elements and rare earth elements may be contained in the conductive layer 3. The fine conductive layer is obtained by adding these.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は窒化アルミニウム焼
結体を絶縁体層として用いた回路基板に係り、特に導体
層と絶縁体層とが一体焼結した多層配線を有する回路基
板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board using an aluminum nitride sintered body as an insulating layer, and more particularly to a circuit board having a multilayer wiring in which a conductor layer and an insulating layer are integrally sintered.

【0002】[0002]

【従来の技術】電子機器の小型化にともない、回路基板
に実装される半導体素子からの発熱をいかに効率良く放
熱するかが重要な問題となってくる。従来、回路基板用
の絶縁材料としてはAl23 セラミックスが広く用い
られていたが、Al23 は熱伝導性が低く、放熱性に
問題があった。これに代わるものとして、電気絶縁性等
の絶縁体としての電気諸特性に優れ、かつ熱伝導性に優
れたAlNセラミックスの回路基板への応用が検討され
ている(特開昭60−178688号公報)。
2. Description of the Related Art With the miniaturization of electronic devices, how to efficiently dissipate heat generated from semiconductor elements mounted on a circuit board has become an important issue. Conventionally, Al 2 O 3 ceramics have been widely used as an insulating material for circuit boards, but Al 2 O 3 has a low thermal conductivity and has a problem in heat dissipation. As an alternative to this, application of AlN ceramics, which has excellent electrical characteristics such as electrical insulation as an insulator and has excellent thermal conductivity, to a circuit board has been studied (Japanese Patent Laid-Open No. 60-178688). ).

【0003】ところで電子機器の小型化、高密度化を考
慮すると回路基板の配線にも高密度化が要求され、多層
化は必須の技術となり、AlNセラミックスの多層基板
も検討されている(特開昭60−253295号公報、
特開昭60−253294号公報)。ここで、1,80
0℃程度の高温での、AlN製グリーンシート/導体ペ
ースト・積層体の一体焼結技術は既に存在する。しかし
ながら、この技術を1,600℃未満の低温焼結に応用
する場合、導体層の高抵抗化、絶縁体層と導体層の収縮
率ミスマッチングによる低い位置精度、反りの発生、導
体回路の断線、あるいは剥離などという問題が生じる。
Considering the miniaturization and high density of electronic equipment, the wiring of the circuit board is required to have a high density, and multilayering is an indispensable technique. AlN ceramics multilayer boards are also under consideration (Japanese Patent Application Laid-Open No. 2003-242242). Sho 60-253295,
JP-A-60-253294). Where 1,80
The AlN green sheet / conductor paste / laminate integrated sintering technology at a high temperature of about 0 ° C. already exists. However, when this technology is applied to low-temperature sintering at less than 1,600 ° C., the resistance of the conductor layer is increased, the positional accuracy is low due to the shrinkage ratio mismatch between the insulator layer and the conductor layer, warpage is generated, and the conductor circuit is disconnected. Or a problem such as peeling occurs.

【0004】また、特開平3−146488号公報に
は、AlNセラミック絶縁体層に、タングステンを主成
分とし、更にニッケル、鉄、コバルト等を含む導体層を
用いる技術が開示されている。しかしながら、この技術
では、1,600℃以上という高い温度で焼結処理をす
る必要があり、しかも、その結果得られた絶縁体層/導
体層結合体は、ヘリウムリークテストにおいて10-8
オーダーであることからわかるように、十分な封止効果
のあるものではない。
Further, Japanese Patent Application Laid-Open No. 3-146488 discloses a technique in which a conductor layer containing tungsten as a main component and further containing nickel, iron, cobalt or the like is used for an AlN ceramic insulator layer. However, with this technique, it is necessary to perform the sintering treatment at a high temperature of 1,600 ° C. or higher, and the resulting insulator layer / conductor layer combination has an order of 10 −8 in the helium leak test. As can be seen from the above, it does not have a sufficient sealing effect.

【0005】[0005]

【発明が解決しようとする課題】本発明は、導体層の低
抵抗化、絶縁層と導体層の収縮率がマッチングした高い
位置精度、導体層と絶縁体層との密着性が強固で、反り
や断線等の生じにくいという高信頼性を有する、とくに
同時焼結による一層配線や多層配線を有する高熱伝導性
AlNセラミック回路基板およびそれを用いた半導体装
置並びに高熱伝導性高信頼性回路基板の製造方法を提供
することを目的とする。
DISCLOSURE OF THE INVENTION The present invention provides a conductor layer having a low resistance, a high positional accuracy in which the contraction rates of the insulating layer and the conductor layer are matched with each other, a strong adhesion between the conductor layer and the insulator layer, and a warp. A highly heat-conductive AlN ceramic circuit board having a high reliability in that it is unlikely to cause breakage or disconnection, and in particular having a single wiring or a multi-layer wiring by simultaneous sintering, a semiconductor device using the same, and a highly heat-conductive highly reliable circuit board. The purpose is to provide a method.

【0006】[0006]

【課題を解決するための手段】本発明者らは、AlNを
主成分とする絶縁体部と、W、Moの少なくとも一種を
主成分とし、Ni、CoおよびFeからなる群より選択
される一種以上の元素を含有し、更にAlNを0.1〜
20重量%含有する導体部とを、少なくともその一部に
有することを特徴とする回路基板およびそれを用いる半
導体装置が、上記課題を解決し得ることを見出した。
DISCLOSURE OF THE INVENTION The inventors of the present invention have found that an insulator portion containing AlN as a main component and a component containing at least one of W and Mo as a main component and selected from the group consisting of Ni, Co and Fe. It contains the above elements and 0.1 to 0.1% AlN.
It has been found that a circuit board having a conductor portion containing 20% by weight in at least a part thereof and a semiconductor device using the same can solve the above problems.

【0007】また、本発明者らは、W、Moの少なくと
も一種を主成分とし、Ni、CoおよびFe元素からな
る群より選択される一種以上の元素を単体または化合物
の形態で含有し、周期律表のIIa族および IIIa族元素
からなる群より選択される一種以上の元素を化合物の形
態で含有し、かつAlN粉末を含有する導体ペーストを
使用して、少なくとも一部の導体部を形成し、かつ1,
600℃未満で焼結することを特徴とする、AlN回路
基板の製造方法が上記課題を解決し得ることを見出し
た。
Further, the inventors of the present invention have at least one of W and Mo as main components, and contain one or more elements selected from the group consisting of Ni, Co and Fe elements in the form of a simple substance or a compound, and At least a part of the conductor portion is formed by using a conductor paste containing one or more elements selected from the group consisting of Group IIa and Group IIIa elements in the table in the form of a compound and containing AlN powder. , And 1,
It has been found that a method for manufacturing an AlN circuit board, which is characterized by sintering at less than 600 ° C., can solve the above problems.

【0008】ここでAlNを主成分とする絶縁体部と
は、絶縁層に占めるAlNの含有率が、50wt%以上か
つ50vol%以上であることとする。つまり、絶縁体層中
の粒界相成分さらに着色成分等のAlN以外の相の合計
含有率が、50wt%以下かつ、50vol%以下であること
とする。
Here, the insulator portion containing AlN as a main component means that the content of AlN in the insulating layer is 50 wt% or more and 50 vol% or more. That is, the total content of the phases other than AlN, such as the grain boundary phase component and the coloring component, in the insulator layer is 50 wt% or less and 50 vol% or less.

【0009】また、W、Moの少なくとも一種を主成分
にするとは、導体層に占めるWとMoとの合計含有率
が、50wt%以上かつ50vol%以上であることとする。
なお、この場合、Mo、Wは両成分が入っている必要は
なくWあるいはMoの一方が0wt%(0vol%)であって
も良い。さらに、他の成分、具体的にはAlN、VIII属
元素成分等の導体層中のWとMo以外の合計含有率が5
0wt%以下かつ50vol%以下であることとする。
Further, the expression "containing at least one of W and Mo as a main component" means that the total content of W and Mo in the conductor layer is 50 wt% or more and 50 vol% or more.
In this case, Mo and W do not need to contain both components, and either W or Mo may be 0 wt% (0 vol%). Furthermore, the total content other than W and Mo in the conductor layer of other components, specifically, AlN and Group VIII element components, is 5
It should be 0 wt% or less and 50 vol% or less.

【0010】[0010]

【発明の実施の形態】まず、本発明に係る回路基板中の
絶縁体層について説明する。絶縁体層は、AlNを主成
分とする多結晶体である。この絶縁体層の強度は、25
0MPa 以上であることが好ましく、組成や焼結条件の最
適化により350MPa 以上とするのがより好ましい。さ
らにアルカリ金属元素を添加することで400MPa 以上
の強度を有する絶縁層も得ることができる。
BEST MODE FOR CARRYING OUT THE INVENTION First, an insulator layer in a circuit board according to the present invention will be described. The insulator layer is a polycrystalline body containing AlN as a main component. The strength of this insulator layer is 25
It is preferably 0 MPa or more, and more preferably 350 MPa or more by optimizing the composition and sintering conditions. Further, by adding an alkali metal element, an insulating layer having a strength of 400 MPa or more can be obtained.

【0011】また、熱伝導率は、アルミナのそれよりも
高い120W/mK以上であることが好ましい。酸素含有量
の少ないAlN原料粉末を用いることにより、140W/
mKの熱伝導性を有する絶縁体層、場合により150W/mK
以上の絶縁体層も得ることができる。また、焼結条件を
最適化することで210W/mK以上の熱伝導率をもつ絶縁
体層も得ることができる。
The thermal conductivity is preferably 120 W / mK or higher, which is higher than that of alumina. By using AlN raw powder with low oxygen content, 140W /
Insulator layer with thermal conductivity of mK, sometimes 150W / mK
The above insulator layers can also be obtained. Also, by optimizing the sintering conditions, an insulating layer having a thermal conductivity of 210 W / mK or more can be obtained.

【0012】次に、この絶縁体層の製造方法を説明す
る。まず、AlNグリーンシートを作製する。このグリ
ーンシートは、AlN粉末、焼結助剤、結合剤(バイン
ダ)等を溶剤と共に十分混合したものを用い、例えばド
クターブレード法等により得られるものである。
Next, a method of manufacturing this insulator layer will be described. First, an AlN green sheet is produced. The green sheet is obtained by, for example, a doctor blade method using a mixture of AlN powder, a sintering aid, a binder (binder) and the like, which are sufficiently mixed with a solvent.

【0013】用いるAlN粉末に関し、特に制限はない
が、絶縁体層の熱伝導率を考慮すると、酸素量が3.0
重量%以下のAlN粉末を用いることが好ましい。より
好ましくは酸素量が2.0重量%未満であり、さらに好
ましくは1.3重量%未満である。焼結体中の酸素量が
少ないほど熱伝導率が高くなるからである。
The AlN powder used is not particularly limited, but when the thermal conductivity of the insulating layer is taken into consideration, the amount of oxygen is 3.0.
It is preferable to use less than or equal to wt% of AlN powder. More preferably, the amount of oxygen is less than 2.0% by weight, and even more preferably less than 1.3% by weight. This is because the thermal conductivity increases as the amount of oxygen in the sintered body decreases.

【0014】また、用いるAlN粉末は、粒子径が小さ
いものが揃っているほうが好ましく、平均粒子径は1.
5μm 未満であるものが好ましい。より好ましくは0.
8μm 未満であるが、特に、0.7μm 未満の粒子を7
0体積%以上含む粉末が最適である。なお、0.03μ
m 以上の粉末を用いることがハンドリングの点から好ま
しい。また、含有する陽イオン不純物は3,000ppm
未満であることが好ましく、より好ましくは1,500
ppm 未満、さらに好ましくは900ppm 未満である。陽
イオン不純物を多量に含有すると、焼結体が高い熱伝導
率をもたなくなるという欠点が生じる。酸素以外の陰イ
オン不純物は2,000ppm 未満であることが好まし
く、より好ましくは1,000ppm 、さらに好ましくは
500ppm 未満である。酸素以外の陰イオン不純物も陽
イオン不純物と同様に多量に含有すると、焼結体が高い
熱伝導率をもたなくなるという欠点が生じる。
It is preferable that the AlN powder used has a small particle size, and the average particle size is 1.
It is preferably less than 5 μm. More preferably, 0.
Particles smaller than 8 μm, but especially smaller than 0.7 μm
A powder containing 0% by volume or more is optimal. In addition, 0.03μ
From the viewpoint of handling, it is preferable to use a powder of m or more. In addition, the cation impurities contained are 3,000 ppm.
It is preferably less than 1, more preferably 1,500
It is less than ppm, more preferably less than 900 ppm. If a large amount of cationic impurities is contained, there is a drawback that the sintered body does not have high thermal conductivity. Anionic impurities other than oxygen are preferably less than 2,000 ppm, more preferably 1,000 ppm, still more preferably less than 500 ppm. If a large amount of anionic impurities other than oxygen are contained as in the case of cationic impurities, there is a drawback that the sintered body does not have high thermal conductivity.

【0015】添加する焼結助剤は、希土類元素およびア
ルカリ土類元素から選択される一種以上の元素を、単
体、化合物の少なくとも一種の形で添加すればよい。S
c、Y、La、Ce、Pr、Nd、Pm、Sm、Eu、
Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、C
a、Sr、Baがいずれも使用できる。これら希土類元
素およびアルカリ土類元素は、AlNセラミックスの緻
密化に寄与すると共に、AlN粉末中の酸素元素を粒界
の副構成相にトラップし、高熱伝導化に大きく貢献す
る。特に好ましい元素は、このような効果の大きいY、
Yb、Eu、Ca元素である。
The sintering aid to be added may be one or more elements selected from rare earth elements and alkaline earth elements in the form of at least one of a simple substance and a compound. S
c, Y, La, Ce, Pr, Nd, Pm, Sm, Eu,
Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, C
Any of a, Sr, and Ba can be used. These rare earth elements and alkaline earth elements contribute to the densification of the AlN ceramics and trap the oxygen element in the AlN powder in the sub-constituent phase of the grain boundary, which greatly contributes to the high thermal conductivity. Particularly preferred elements are Y, which has such a large effect,
Yb, Eu, and Ca elements.

【0016】これら元素を含有する化合物の形態として
は、酸化物の形態が特に好ましく、焼結条件下で酸化物
となる化合物も用いてもよい。例えば、炭酸塩、硝酸
塩、シュウ酸塩、硫酸塩、水酸化物などでも使用し得
る。また、酸化物でなくとも、ハロゲン化物、酸ハロゲ
ン化物、アセチリド化合物、炭化物、水素化物、窒化
物、硼化物、ケイ化物、硫化物などでもよい。これら希
土類元素およびアルカリ土類元素は、原料粉末中に含ま
れる酸素量との兼ね合いで最適量を決定すべきではある
が、酸化物換算で0.5〜12重量%であることが望ま
しい。好ましくは1.0〜8重量%であることが望まし
い。さらに好ましくは2.0〜6.0重量%である。ま
た、希土類元素およびアルカリ土類元素を含む化合物を
両方添加するか、両類元素を含有する複合化合物を添加
すると、低温で焼結することが可能となり、焼結開始温
度を最大で400℃低下させることができる。また、希
土類元素およびアルカリ土類元素を含むハロゲン化合物
を添加しても低温で焼結することが可能となり、焼結開
始温度を最大で400℃低下させることができる。
As a form of a compound containing these elements, an oxide form is particularly preferable, and a compound which becomes an oxide under sintering conditions may be used. For example, carbonates, nitrates, oxalates, sulfates, hydroxides and the like can also be used. Further, it may be a halide, an acid halide, an acetylide compound, a carbide, a hydride, a nitride, a boride, a silicide, a sulfide, etc., instead of the oxide. The optimum amount of these rare earth elements and alkaline earth elements should be determined in consideration of the amount of oxygen contained in the raw material powder, but it is preferably 0.5 to 12% by weight in terms of oxide. It is preferably 1.0 to 8% by weight. More preferably, it is 2.0 to 6.0% by weight. In addition, if both a compound containing a rare earth element and an alkaline earth element is added or a composite compound containing both elements is added, it becomes possible to sinter at a low temperature, and the sintering start temperature is lowered by 400 ° C at the maximum. Can be made. Moreover, even if a halogen compound containing a rare earth element and an alkaline earth element is added, it becomes possible to sinter at a low temperature, and the sintering start temperature can be lowered by 400 ° C. at the maximum.

【0017】低温での焼結性を向上させるために、アル
ミナを添加してもよい。添加量は0.8重量%以下であ
ることが好ましく、0.25重量%以下であることがさ
らに好ましい。
Alumina may be added to improve the sinterability at low temperature. The addition amount is preferably 0.8% by weight or less, and more preferably 0.25% by weight or less.

【0018】さらに、回路基板は用途に応じて、着色、
つまり、遮光性が求められる。この場合には、周期律表
のIVa、Va、VIa、 VIIa、VIII族元素を単体もしく
は化合物の形態で添加すれば近紫外域から赤外域までの
遮光が可能となる。添加量は、元素換算で0.03〜5
重量%添加すればよい。より好ましくは0.1〜3重量
%、さらに好ましくは、0.2〜1重量%添加すればよ
い。
Further, the circuit board may be colored, depending on the application.
That is, the light shielding property is required. In this case, if the IVa, Va, VIa, VIIa, and VIII elements of the periodic table are added in the form of a single substance or a compound, it is possible to shield light from the near ultraviolet region to the infrared region. The addition amount is 0.03 to 5 in element conversion.
It may be added by weight%. It is more preferable to add 0.1 to 3% by weight, and further preferably 0.2 to 1% by weight.

【0019】これらの焼結助剤等の添加方法は、予め原
料粉末に添加すればよい。ただし、添加物の種類によっ
ては、含浸等の方法で後に添加してもよい。
As a method of adding these sintering aids and the like, they may be added in advance to the raw material powder. However, depending on the type of additive, it may be added later by a method such as impregnation.

【0020】用いる結合剤は、1,400℃以下の温度
で分解する有機高分子体が好ましい。具体的には、ポリ
メチルメタクリレート、ポリビニルブチラール、ポリア
クリル酸エステル、ポリビニルアルコール、セルロース
アセテートブチレート、セルロース等の酸素含有有機高
分子体を1〜3種類、場合によってはそれ以上混合した
ものを用いてもよい。バインダの種類や量ならびに溶剤
量等の選択はAlN原料粉末の特性や、作製したいシー
トの厚み等で随意選択する。さらに、脱バインダは、N
2 、Ar、H2 等の非酸化性雰囲気中で行えば良い。さ
らに、脱バインダー後のカーボンを少なくしたい場合に
はH2 Oを含有させても良い。
The binder used is preferably an organic polymer which decomposes at a temperature of 1,400 ° C. or lower. Specifically, one to three types of oxygen-containing organic polymer such as polymethylmethacrylate, polyvinyl butyral, polyacrylic acid ester, polyvinyl alcohol, cellulose acetate butyrate, and cellulose are mixed, and in some cases, a mixture thereof is used. May be. The type and amount of the binder and the amount of the solvent are arbitrarily selected depending on the characteristics of the AlN raw material powder, the thickness of the sheet to be produced, and the like. Further, the binder removal is N
It may be performed in a non-oxidizing atmosphere of 2 , Ar, H 2, or the like. Further, if it is desired to reduce the amount of carbon after debinding, H 2 O may be contained.

【0021】以上のようなAlN粉末、焼結助剤や結合
剤等を含有するグリーンシートを焼結すると絶縁層が形
成されるが、好ましい焼結条件については後述する。
An insulating layer is formed by sintering the green sheet containing the AlN powder, the sintering aid, the binder and the like as described above, and preferable sintering conditions will be described later.

【0022】次に、本発明に係る回路基板中の導体層に
ついて説明する。
Next, the conductor layer in the circuit board according to the present invention will be described.

【0023】この導体層中の導電体は、主成分がMo、
Wの少なくとも一種であり、さらに、周期律表のVIII族
元素の少なくとも一種の元素を含むものである。この導
電体は、周期律表のIVaおよびVa族元素を、単体、化
合物の少なくとも一種の形態で副導体成分として含んで
いてもよく、さらに微量の低融点貴金属元素(Au、A
g、Cu、Pt、Pd等)を含有していてもよい。
The conductor in this conductor layer is mainly composed of Mo,
It is at least one element of W and further contains at least one element of the Group VIII elements of the periodic table. This conductor may contain Group IVa and Va elements of the periodic table as a sub-conductor component in the form of at least one of a simple substance and a compound. Furthermore, a trace amount of a low melting point noble metal element (Au, A
g, Cu, Pt, Pd, etc.) may be contained.

【0024】周期律表のVIII族元素であるNi、Co、
Fe元素を添加すると、導体層の主成分であるMo、W
の焼結性が著しく向上する。これは、導体層中に液相が
焼結途中に生成しMo、Wが液相焼結により焼結が促進
されるためである。これらNi、Co、Fe元素は単体
金属の粉末で添加してもよいし、化合物の形で添加して
もよい。化合物の形で添加する際には、酸化物で添加す
るのが最も好ましいが、焼結途中に酸化物となる化合物
を添加してもよい。具体的には、炭酸塩、硝酸塩、水酸
化物、硫酸塩等が挙げられる。また、酸化物でなくと
も、硼化物、ケイ化物、水素化物、弗化物、窒化物、炭
化物、リン化物等の形で添加してもよい。
Ni, Co, which are Group VIII elements of the periodic table,
When Fe element is added, the main components of the conductor layer are Mo, W
Sinterability is significantly improved. This is because the liquid phase is generated in the conductor layer during the sintering, and Mo and W are promoted by the liquid phase sintering. These Ni, Co and Fe elements may be added in the form of powder of a single metal or in the form of compound. When it is added in the form of a compound, it is most preferable to add it as an oxide, but a compound which becomes an oxide may be added during sintering. Specific examples include carbonates, nitrates, hydroxides, sulfates and the like. Further, it may be added in the form of boride, silicide, hydride, fluoride, nitride, carbide, phosphide, etc., instead of the oxide.

【0025】添加量は、一酸化物換算で、0.01〜5
重量%の範囲が好ましい。0.01重量%未満の添加量
のときには、導体層中に十分な量の液相が生成しないた
めにMo、Wの焼結が十分促進されない。つまり、導体
の相対密度が低い値で焼結は停止してしまう。したがっ
て、相対密度が低く、収縮率が小さいために絶縁層と収
縮率ミスマッチングが発生し、反りの発生や、位置精度
の低い回路基板となってしまう。さらにはHeリーク特
性も悪くなる。また、5重量%を超える添加を行うと、
焼結途中に生成する液相が多すぎて、液相の蒸発により
導体層中に膨れが発生すると共に、高抵抗の合金相が多
量生成してしまい、導体全体の抵抗率が高くなってしま
う。添加量はより好ましくは0.05〜2重量%、さら
に好ましくは0.1〜1重量%である。0.01〜5重
量%の範囲でVIII族元素を添加した場合には導体層の相
対密度は90%以上となり、抵抗率も16μΩcm以下に
なる。条件を最適化すれば相対密度が95%以上で抵抗
率が14μΩcm以下の緻密で低抵抗な導体が得られる。
さらに最適化すれば10μΩcm以下の低抵抗な導体も得
られる。その結果得られる回路基板は、絶縁層と導体層
の収縮率マッチングが達成されているために、各部分の
位置精度は±1%以内、最適化したものでは±0.5%
以下の位置精度を有する。さらに、反りの発生が抑制さ
れ、20μm/10mm対角線以下になる。最適化を行う
と、5μm/10mm対角線の反り量にまで小さくなる。さ
らに周期律表のVIII族を添加した導体にNiメッキを施
す場合には、導体層とメッキ層の接合強度が大きな値で
得られる。
The amount of addition is 0.01 to 5 in terms of monoxide.
A range of weight% is preferred. When the addition amount is less than 0.01% by weight, a sufficient amount of liquid phase is not generated in the conductor layer, so that sintering of Mo and W is not sufficiently promoted. That is, the sintering stops when the relative density of the conductor is low. Therefore, since the relative density is low and the shrinkage ratio is small, shrinkage ratio mismatch with the insulating layer occurs, resulting in warpage and a circuit board with low positional accuracy. Further, the He leak characteristic is also deteriorated. Moreover, if the addition exceeds 5% by weight,
Too much liquid phase is generated during sintering, causing swelling in the conductor layer due to evaporation of the liquid phase, and a large amount of high-resistance alloy phase is generated, increasing the resistivity of the entire conductor. . The addition amount is more preferably 0.05 to 2% by weight, and further preferably 0.1 to 1% by weight. When the Group VIII element is added in the range of 0.01 to 5% by weight, the relative density of the conductor layer becomes 90% or more, and the resistivity becomes 16 μΩcm or less. If the conditions are optimized, a dense and low-resistance conductor having a relative density of 95% or more and a resistivity of 14 μΩcm or less can be obtained.
If further optimized, a conductor having a low resistance of 10 μΩcm or less can be obtained. The resulting circuit board has achieved shrinkage rate matching between the insulating layer and the conductor layer, so the positional accuracy of each part is within ± 1%, and ± 0.5% for the optimized one.
It has the following positional accuracy. Further, the occurrence of warpage is suppressed, and the diagonal line becomes 20 μm / 10 mm or less. When the optimization is performed, the warp amount of the diagonal line of 5 μm / 10 mm is reduced. Furthermore, when Ni plating is applied to a conductor to which Group VIII of the Periodic Table is added, the bonding strength between the conductor layer and the plating layer can be obtained with a large value.

【0026】導体形成に用いるMo、W粉末の粒度が
1.5μm 以上のもの、特に2.0μm 以上のものを使
用するときに、周期律表のVIII族元素を添加すると効果
が大きい。このように、周期律表のVIII族を添加する
と、導体の収縮が促進されるため、さらに1,600℃
未満での低温焼結、場合によっては1,550℃以下の
低温焼結が可能となり収縮率マッチングが達成される。
When using Mo or W powder having a particle size of 1.5 μm or more, particularly 2.0 μm or more, which is used for forming the conductor, the addition of the Group VIII element of the periodic table has a great effect. Thus, the addition of Group VIII of the Periodic Table promotes the contraction of the conductor, and
Low-temperature sintering at less than 1,550 ° C. or less is possible in some cases, and shrinkage ratio matching is achieved.

【0027】導体層には、絶縁層の主成分であるAlN
を共材という形で添加する。これにより、絶縁層部分の
収縮率と導体部分の収縮率のマッチングが容易に達成さ
れる。ただし、添加するAlNは絶縁体であるために、
多量の添加は導体層の抵抗率の上昇に結び付くために好
ましくない。また、添加量が少ないとAlNの共材添加
の効果が小さくなるので好ましくない。共材の添加量
は、0.1〜20重量%の範囲であるとき上記の効果が
得られる。好ましくは0.5〜10重量%の範囲、さら
に好ましくは1〜5重量%の範囲である。AlN共材を
添加した回路基板では、絶縁体層と導体層間の収縮率マ
ッチングが達成されるために、反りの発生が極端に抑制
される。そのために、焼結後の反りを無くすための反り
直しの工程を行う必要もない。また、その結果、位置精
度も±1%以下、添加量を最適化すると容易に±0.5
%以下にすることができる。さらにMo、W導体につい
ては、AlN共材を添加すると収縮が促進され緻密な導
体となるために低抵抗な導体が得られる。
The conductor layer is made of AlN which is the main component of the insulating layer.
Is added in the form of co-material. Thereby, the contraction rate of the insulating layer portion and the contraction rate of the conductor portion can be easily matched. However, since the added AlN is an insulator,
Addition of a large amount is not preferable because it leads to an increase in the resistivity of the conductor layer. Also, if the addition amount is small, the effect of adding the AlN co-material is reduced, which is not preferable. The above effect is obtained when the additive amount of the co-material is in the range of 0.1 to 20% by weight. It is preferably in the range of 0.5 to 10% by weight, more preferably in the range of 1 to 5% by weight. In the circuit board to which the AlN co-material is added, contraction rate matching between the insulator layer and the conductor layer is achieved, so that warpage is extremely suppressed. Therefore, there is no need to perform a step of rewarping to eliminate warpage after sintering. As a result, the positional accuracy is ± 1% or less, and it is easily ± 0.5 if the addition amount is optimized.
% Or less. Further, regarding the Mo and W conductors, when an AlN co-material is added, shrinkage is promoted and the conductor becomes a dense conductor, so that a conductor having a low resistance can be obtained.

【0028】本発明の導体層中には、さらにアルカリ土
類元素および希土類元素から選択される少なくとも一種
の元素が含まれていてもよい。これらを単体、化合物の
少なくとも一種の形で添加すると、ヘリウムリーク試験
で確認できるように緻密な導体が得られる。希土類元素
およびアルカリ土類元素としては、例えば、Sc、Y、
La、Ce、Pr、Nd、Pm、Sm、Eu、Gd、T
b、Dy、Ho、Er、Tm、Yb、Lu、Ca、S
r、Baが挙げられる。特に、工業的には、Y、Yb、
Er、Caが好ましい。これら元素の酸化物は特に好ま
しく、焼結条件下で酸化物となる化合物も用いることが
できる。このような添加物は、酸化物はもとより、ハロ
ゲン化物、酸ハロゲン化物、アセチリド化合物、炭化
物、水素化物、窒化物、硼化物、ケイ化物、硫化物等の
形態で添加される。希土類元素およびアルカリ土類元素
を含有する化合物の導体層中の含有量は、酸化物換算で
0.01〜15重量%が好ましい。あまり多いと導体層
の導電率が低下し、少ないと導体層の剥離防止、基板の
反り防止などの効果を得ることができない場合があるか
らである。
The conductor layer of the present invention may further contain at least one element selected from alkaline earth elements and rare earth elements. When these are added in the form of at least one of a simple substance and a compound, a dense conductor can be obtained as can be confirmed by a helium leak test. Examples of rare earth elements and alkaline earth elements include Sc, Y,
La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, T
b, Dy, Ho, Er, Tm, Yb, Lu, Ca, S
r and Ba are mentioned. Particularly, industrially, Y, Yb,
Er and Ca are preferred. Oxides of these elements are particularly preferable, and compounds that become oxides under sintering conditions can also be used. Such additives are added in the form of halides, acid halides, acetylide compounds, carbides, hydrides, nitrides, borides, silicides, sulfides, etc., as well as oxides. The content of the compound containing the rare earth element and the alkaline earth element in the conductor layer is preferably 0.01 to 15% by weight in terms of oxide. This is because if the amount is too large, the conductivity of the conductor layer is lowered, and if the amount is too small, it may not be possible to obtain the effect of preventing the conductor layer from peeling off and the substrate from warping.

【0029】導体層中に、更に、Al元素を含有する単
体もしくは化合物を添加すると、無添加時と比較して相
対密度の大きな緻密な導体が得られ、導体層の剥離防止
および接合強度の向上、基板の反り防止などの効果を得
ることができる。例えば、Al23 が挙げられる。こ
のような添加物は、同時燒結時にアルミネート液相を形
成する。また、同時燒結時に絶縁体層中にもアルミネー
ト液相が生じる。この様に、導体層中にアルミネート液
相が生じることにより、絶縁体層に生じる液相の導体層
による吸い上げが防止され、このような吸い上げによる
絶縁体層中の組成の不均一を防止し、基板の反りを防止
することができる。
When a simple substance or a compound containing an Al element is further added to the conductor layer, a dense conductor having a large relative density is obtained as compared with the case where it is not added, and the conductor layer is prevented from peeling and the joint strength is improved. Thus, it is possible to obtain the effect of preventing the warp of the substrate. For example, Al 2 O 3 can be mentioned. Such additives form an aluminate liquid phase upon simultaneous sintering. In addition, an aluminate liquid phase also occurs in the insulating layer during simultaneous sintering. In this way, by forming the aluminate liquid phase in the conductor layer, the liquid phase generated in the insulator layer is prevented from being sucked up by the conductor layer, and the nonuniformity of the composition in the insulator layer due to such sucking is prevented. It is possible to prevent the warp of the substrate.

【0030】以下に本発明の回路基板の製造方法につい
て述べる。
The method of manufacturing the circuit board of the present invention will be described below.

【0031】まず、同時焼結した後も導電性を維持し得
る、具体的にはMoおよびW金属を主成分とし、周期律
表のVIII族元素の単体、その酸化物などの化合物の少な
くとも一種を粉末にしたものをペースト化し、AlNグ
リーンシート上に所望のパターンで印刷する。また、ペ
ースト化する際、副導体成分として、周期律表のIVaお
よびVa族元素から選択される一種以上の元素を、単
体、化合物の少なくとも一種の形態で添加してもよい。
この際、グリーンシートにはパンチングマシーンなどを
用いてビアホールを形成しておき、予め焼結体となる導
電ペーストを圧入やメタルマスクなどを用いて印刷充填
などにより充填しておく。このビアホールによりグリー
ンシートを挟む上下導体間の電気的接続を行う。
First, it is possible to maintain conductivity even after co-sintering. Specifically, at least one of compounds containing Mo and W metals as main components, a simple substance of Group VIII element of the periodic table, and oxides thereof. Is made into a powder and printed in a desired pattern on an AlN green sheet. When forming a paste, one or more elements selected from Group IVa and Va elements of the periodic table may be added as a sub-conductor component in the form of at least one of a simple substance and a compound.
At this time, a via hole is formed in the green sheet using a punching machine or the like, and a conductive paste to be a sintered body is previously filled by press-fitting or printing using a metal mask. The via holes electrically connect the upper and lower conductors that sandwich the green sheet.

【0032】この導体ペーストには、AlNセラミック
粉末を添加しておく。さらに、希土類元素およびアルカ
リ土類元素から選択される一種以上の元素を単体、化合
物の少なくとも一種の形態で、さらにはAl23 (ア
ルミナ)を添加してもよい。希土類元素を含有する単
体、化合物の少なくとも一種と共に、混合物の形態でア
ルミナを添加する場合には、アルミネートを形成するよ
うな比率で混合することが好ましい。
AlN ceramic powder is added to this conductor paste. Further, at least one element selected from rare earth elements and alkaline earth elements may be added in the form of at least one of a simple substance and a compound, and further Al 2 O 3 (alumina) may be added. When alumina is added in the form of a mixture with at least one of a simple substance and a compound containing a rare earth element, it is preferable to mix them in such a ratio as to form an aluminate.

【0033】導体の体積が大きくなるビアホール部分に
のみAlNを添加しても、基板の反りを最小に抑制し得
る。すなわち、基板の大きさや、設計で決めた導体層の
配置によっては、少なくとも一部分の導体層に添加すれ
ば反りの少ない回路基板が得られる場合がある。
Even if AlN is added only to the via hole portion where the volume of the conductor becomes large, the warp of the substrate can be suppressed to a minimum. That is, depending on the size of the board and the arrangement of the conductor layers determined by design, a circuit board with less warpage may be obtained by adding it to at least a part of the conductor layers.

【0034】このような成分を含有する導電ペーストを
塗布した多層グリーン成形体を脱バインダした後、焼結
工程に供する。この焼結工程については、公知のAlN
で行われる焼結方法がそのまま採用され特には限定はさ
れないが、焼結炉にセットする際のセッタは、様々な材
質のものを用い得るが、AlNセッタを用いるとWやM
oが反応により化合物とならずに低抵抗な導体が得られ
る。焼結上りの表面粗さは、非常に小さなものとなり良
好な回路基板が得られる。表面粗さは、平均表面粗さR
aで1.0μm 以下になる。より良好な表面をもつもの
では0.5μm以下、さらに良好な表面をもつものでは
0.3μm 以下になる。一般には、常圧下、加圧下、減
圧下の非酸化性雰囲気下、例えば窒素雰囲気やアルゴン
雰囲気下で、1,450℃以上1,600℃未満の温度
で焼結を実施すればよい。焼結に必要な時間は焼結に供
される成形体の厚さや焼結温度などの諸条件によって異
なるが、一般に、0.5時間〜100時間の範囲から選
択をすればよい。これらの条件は実施に先立ち諸条件に
応じて適当な範囲を予め決定して実施するのが好まし
い。
After removing the binder from the multilayer green compact coated with the conductive paste containing such components, it is subjected to a sintering step. For this sintering step, known AlN
Although the sintering method performed in (3) is adopted as it is and is not particularly limited, the setter for setting in the sintering furnace can be made of various materials.
The reaction of o does not form a compound, and a low-resistance conductor is obtained. The surface roughness after sintering becomes very small and a good circuit board can be obtained. The surface roughness is the average surface roughness R
a is 1.0 μm or less. Those having a better surface have a thickness of 0.5 μm or less, and those having a better surface have a thickness of 0.3 μm or less. Generally, sintering may be performed at a temperature of 1,450 ° C. or more and less than 1,600 ° C. under a non-oxidizing atmosphere under normal pressure, increased pressure, and reduced pressure, for example, a nitrogen atmosphere or an argon atmosphere. The time required for sintering varies depending on various conditions such as the thickness of the molded body to be sintered and the sintering temperature, but generally, it may be selected from the range of 0.5 hours to 100 hours. It is preferable that an appropriate range of these conditions is determined in advance according to various conditions prior to execution.

【0035】得られるAlN回路基板を高熱伝導で緻
密、さらには高強度にするためには、特に1000℃以
上の高温部で平均昇温速度を1〜40℃/minの範囲とす
ることが好ましい。より好ましくは、5〜30℃/min、
さらに好ましくは8〜25℃/minの範囲とすることが好
ましい。上記焼結により、相対密度が98%以上のAl
N絶縁層が得られる。より緻密なものとして99%以上
の絶縁層が得られる。
In order to make the obtained AlN circuit board have high thermal conductivity, high density, and high strength, it is preferable to set the average heating rate in the range of 1 to 40 ° C./min particularly in a high temperature portion of 1000 ° C. or higher. . More preferably, 5 to 30 ° C / min,
More preferably, the range is 8 to 25 ° C./min. Due to the above sintering, Al having a relative density of 98% or more
An N insulating layer is obtained. As a more dense structure, 99% or more of the insulating layer can be obtained.

【0036】このようにして製造された回路基板は次の
ような特性を有する。
The circuit board manufactured in this way has the following characteristics.

【0037】まず、この本発明の回路基板は、表裏平行
度が非常に小さな値となっており、反りやうねりが非常
に小さく、外部端子の数が非常に多い(例えば1,00
0端子以上の)回路基板でも実装時に半田接続が容易に
行うことができる。基板の反りやうねりの有無を表す表
裏平行度は、焼結体多層回路基板の対角線10cm当たり
を基準にして中央部と周縁部との反りの最大値を測定し
て求めた場合、この値が0.2mm以下の非常に小さな値
となる。大面積の回路基板の場合には、表裏平行度が
0.05mm以下の本発明に係る基板を用いれば実装が可
能となる。
First, in the circuit board of the present invention, the parallelism between the front and back is very small, warpage and undulation are very small, and the number of external terminals is very large (for example, 1.00).
Even circuit boards (with 0 or more terminals) can be easily soldered during mounting. The front and back parallelism, which indicates the presence or absence of warpage or waviness of the board, is obtained by measuring the maximum value of the warpage between the central part and the peripheral part on the basis of 10 cm diagonal line of the sintered multilayer circuit board. It is a very small value of 0.2 mm or less. In the case of a large-area circuit board, mounting can be performed by using the board according to the present invention having front and back parallelism of 0.05 mm or less.

【0038】また、この回路基板の表面抵抗および内部
抵抗は、16μΩcm以下と良好な値となる。最適化を行
うと14μΩcm、場合により10μΩcm以下というさら
に好ましい値となる。周期律表のVIII族元素を含有させ
て導体層を形成させるために、導体の密度が高くなり、
抵抗率の低い導体が得られる。さらに、AlNを導体層
に添加しているので、絶縁体層と導体層の収縮挙動がほ
ぼ同一のものとなり、収縮率のマッチングが達成されて
±1%以下の位置精度が得られる。場合により、±0.
5%以下という優れた位置精度が得られる。このような
位置精度と平坦性を有する回路基板では、フリップチッ
プ実装を容易に行うことができる。
The surface resistance and internal resistance of this circuit board are 16 μΩcm or less, which is a good value. When optimized, it becomes a more preferable value of 14 μΩcm, and in some cases 10 μΩcm or less. Since the conductor layer is formed by containing the Group VIII element of the periodic table, the density of the conductor is increased,
A conductor having a low resistivity can be obtained. Furthermore, since AlN is added to the conductor layer, the contraction behavior of the insulator layer and the conductor layer are almost the same, the contraction rate matching is achieved, and the positional accuracy of ± 1% or less is obtained. In some cases, ± 0.
Excellent position accuracy of 5% or less can be obtained. A circuit board having such positional accuracy and flatness can be easily flip-chip mounted.

【0039】さらに、この回路基板中の絶縁体層と導体
層の接合強度は、5 kg/2mm×2mm以上の値となる。5
kg/2mm×2mm未満の値では、外部端子にピンを用いた
場合、接合強度としては不足であり、AlNと導体間で
ピンの脱落が生じる。特に、BGA(ボールグリッドア
レイパッケージ)の場合に、プリント配線板のような熱
膨張率の大きな有機材料に、ボール間隔が狭ピッチで表
面実装を行うときには、さらに高強度な接合強度が要求
される。そのときには6 kg/2mm×2mm以上の接合強度
を有する導体層組成を選択すればよい。さらに最適化す
ることで7 kg/2mm×2mm以上の接合強度を有するもの
が得られる。
Further, the joint strength between the insulator layer and the conductor layer in this circuit board has a value of 5 kg / 2 mm × 2 mm or more. 5
When the value is less than kg / 2 mm × 2 mm, when the pin is used for the external terminal, the bonding strength is insufficient, and the pin may drop between the AlN and the conductor. In particular, in the case of BGA (ball grid array package), even higher bonding strength is required when surface mounting an organic material having a large coefficient of thermal expansion such as a printed wiring board with a narrow pitch between balls. . In that case, a conductor layer composition having a bonding strength of 6 kg / 2 mm × 2 mm or more may be selected. By further optimizing it, one having a joint strength of 7 kg / 2 mm × 2 mm or more can be obtained.

【0040】本発明の回路基板を用いた好適な半導体装
置を、図2および図3を参照しながら説明する。この半
導体装置は、基板上面12aにECLなどの(特に素子
の種類は限定されるものではない)半導体6が搭載さ
れ、この半導体素子と電気的に接続された配線パターン
を有する多層セラミック回路基板12と、前記配線パタ
ーンと電気的に接続されるとともに、多層セラミック回
路基板12の基板下面12bに形成された外部端子と、
半導体素子6を覆うように、多層セラミック回路基板の
基板上面12aに接合された高熱伝導性封止部材13と
を備えている。ただし、外部端子と半導体素子が同一の
一主面にあっても特に問題なく使用することができる。
なお、外部端子は、好ましくは図2に示されるようにリ
ードピン7であり、あるいは図3に示されるように半田
ボール15(BGAボールグリッドアレイ)でもよい。
また、Si素子は、回路基板の位置精度が良好であり、
平坦性も良好であるので、フリップチップタイプの実装
方法も容易に行うことができる。また、高熱伝導性封止
部材は、100W/mK以上の熱伝導率を有するAlN焼結
体や、合金を含む金属から構成するとよい。
A preferred semiconductor device using the circuit board of the present invention will be described with reference to FIGS. In this semiconductor device, a semiconductor 6 such as ECL (the type of element is not particularly limited) is mounted on a substrate upper surface 12a, and a multilayer ceramic circuit board 12 having a wiring pattern electrically connected to this semiconductor element. And an external terminal electrically connected to the wiring pattern and formed on the substrate lower surface 12b of the multilayer ceramic circuit substrate 12,
A high thermal conductive sealing member 13 bonded to the substrate upper surface 12a of the multilayer ceramic circuit substrate is provided so as to cover the semiconductor element 6. However, even if the external terminal and the semiconductor element are on the same main surface, they can be used without any particular problem.
The external terminals are preferably lead pins 7 as shown in FIG. 2 or solder balls 15 (BGA ball grid array) as shown in FIG.
Further, the Si element has good positional accuracy of the circuit board,
Since the flatness is also good, the flip-chip type mounting method can be easily performed. The high thermal conductivity sealing member may be made of an AlN sintered body having a thermal conductivity of 100 W / mK or more, or a metal containing an alloy.

【0041】上記構成に係る半導体装置によれば、半導
体素子において発生する熱が、効率良く、放熱フィンな
ど(フィンを用いない場合もある)に伝達され、優れた
放熱性を発揮させることができる。
According to the semiconductor device having the above structure, the heat generated in the semiconductor element can be efficiently transmitted to the heat radiation fins or the like (in some cases, no fin is used), and excellent heat radiation performance can be exhibited. .

【0042】また、半導体装置を構成する上で、外部端
子の接合面と対向するAlN回路基板の他の主面に半導
体素子を搭載した場合には、多ピン化に対応しているう
えに、半導体装置を小形化することができ、高速の半導
体装置としてより好ましい。また、半導体が作動してい
るときと作動停止したときの温度変化が生じた場合に、
回路基板の絶縁層がAlNで構成されているため、外部
端子のピンや半田ボール部分に応力がかかる。しかし、
強度が高いために、割れなどの不具合は発生しない。さ
らに、一つの回路基板に多数の半導体を搭載するマルチ
チップモジュール(MCM)の形で半導体装置を構成す
ると、広い面積で外部端子をボードに接合しなければな
らないが、この場合にも耐熱応力の点で十分使用できる
だけの信頼性が得られる。
When a semiconductor element is mounted on the other main surface of the AlN circuit board that faces the bonding surface of the external terminal in constructing the semiconductor device, the number of pins is increased, and The semiconductor device can be miniaturized, which is more preferable as a high-speed semiconductor device. Also, when a temperature change occurs when the semiconductor is operating and when it is not operating,
Since the insulating layer of the circuit board is made of AlN, stress is applied to the pins of the external terminals and the solder ball portions. But,
Due to its high strength, no defects such as cracks occur. Furthermore, when a semiconductor device is configured in the form of a multi-chip module (MCM) in which a large number of semiconductors are mounted on one circuit board, external terminals must be joined to the board over a large area. The point is that it is reliable enough to use.

【0043】本発明をさらに具体的に説明するために、
以下に実施例を挙げて説明するが、本発明はこれらの実
施例に限定されるものではない。
To explain the present invention more specifically,
Examples will be described below, but the present invention is not limited to these examples.

【0044】[0044]

【実施例】以下に本発明の実施例を説明する。実施例1 不純物として酸素を0.9重量%含有し、平均粒径が
0.6μm のAlN粉末と、焼結助剤として平均粒径
0.5μm のY23 と、平均粒径が0.5μm のCa
CO3 と、0.5μm のAl23 と、着色剤としてW
3 とを、94.42:3:1.78:0.5:0.3
(重量%)となるよう配合し、AlN製ボールを用いて
24時間湿式混合を行い原料を調整した。ついで、この
原料に有機バインダーを有機溶媒と共に分散し、スラリ
ーを作製した。このスラリーを脱泡した後、ドクタープ
レード法により、100〜800μm 程度の均一なグリ
ーンシートを作製した。次に、このシートを約130mm
×130mmの大きさに切断し、各層間の電気回路の接続
になるビアホールをパンチングマシーンで100〜30
0μm φの太さに開けた。
Embodiments of the present invention will be described below. Example 1 AlN powder containing 0.9% by weight of oxygen as an impurity and having an average particle size of 0.6 μm, Y 2 O 3 having an average particle size of 0.5 μm as a sintering aid, and an average particle size of 0. 0.5 μm Ca
CO 3 , 0.5 μm of Al 2 O 3 and W as a colorant
O 3 and 94.42: 3: 1.78: 0.5: 0.3
(% By weight), and wet mixing was performed for 24 hours using AlN balls to prepare raw materials. Then, an organic binder was dispersed in this raw material together with an organic solvent to prepare a slurry. After defoaming this slurry, a uniform green sheet of about 100 to 800 μm was prepared by the doctor blade method. Next, this sheet is about 130mm
Cut to a size of 130 mm and use a punching machine to make 100 to 30 via holes for connecting electrical circuits between layers.
It was opened to a thickness of 0 μm φ.

【0045】一方、平均粒径2.0μm のタングステン
と、平均粒径0.6μm のAlN粉末と、平均粒径0.
5μm のY23 粉末と、平均粒径0.5μm のCaC
3粉末と、平均粒径0.5μm のAl23 粉末と、
平均粒径0.8μm のNiOとを、97.1:2.36
8:0.075:0.045:0.013:0.4(重
量%)となるよう配合して、有機溶媒と共に混合、分散
し、フィラー添加の導体ペーストを作製した。ビアホー
ルの形成されたグリーンシート上に、この無機質フィラ
ー添加のタングステンペーストを圧入機を用いて充填
し、さらにスクリーン印刷機を用いて同一面内の回路を
印刷した。これら複数枚を加熱プレスすることで積層過
程を終えた。これを100mm×100mmの大きさにカッ
トし、次にN2 +H2 +H2 O雰囲気中、最高温度90
0℃で脱バインダを行った後、AlNセッターに脱バイ
ンダした成形体を配置し、窒素雰囲気1気圧中1,59
0℃、6時間加圧焼結し、多層セラミック基板を得た。
On the other hand, tungsten having an average particle size of 2.0 μm, AlN powder having an average particle size of 0.6 μm, and an average particle size of 0.
5 μm Y 2 O 3 powder and CaC with average particle size 0.5 μm
And O 3 powder, and Al 2 O 3 powder having an average particle diameter of 0.5 [mu] m,
NiO having an average particle size of 0.8 μm was used as 97.1: 2.36
It mixed so that it might become 8: 0.075: 0.045: 0.013: 0.4 (weight%), and it mixed and disperse | distributed with the organic solvent, and produced the conductor paste of the filler addition. This inorganic filler-added tungsten paste was filled on the green sheet in which the via holes were formed using a press-fitting machine, and a circuit in the same plane was printed using a screen printing machine. The lamination process was completed by hot pressing these multiple sheets. This is cut into a size of 100 mm × 100 mm, and then, in a N 2 + H 2 + H 2 O atmosphere, the maximum temperature is 90.
After debindering at 0 ° C., the debindered compact was placed in an AlN setter, and it was placed in a nitrogen atmosphere at 1 atm for 1,59
Pressure sintering was performed at 0 ° C. for 6 hours to obtain a multilayer ceramic substrate.

【0046】得られた基板の導体部のない部分から円板
(直径10mm、厚さ3.5mm)を切り出し、これを試験
片としてレーザーフラッシュ法により熱伝導率を測定し
た。この結果、155W/mKという高い熱伝導率を示し
た。また、基板の反りの有無を表す表裏平行度は、焼結
体多層基板の対角線を基準にして中央部と周縁部との反
りの最大値を測定することにより求めた。なお、長さ1
0cm当たりの値を用いることにした。この結果、0.0
4mmと僅かな反り量であることが確認された。また、回
路基板内部の各部の位置精度は±0.4%と良好な値で
あった。
A disk (diameter: 10 mm, thickness: 3.5 mm) was cut out from a portion of the obtained substrate having no conductor portion, and a thermal conductivity was measured by a laser flash method using this as a test piece. As a result, it showed a high thermal conductivity of 155 W / mK. The front-back parallelism indicating the presence or absence of warpage of the substrate was determined by measuring the maximum value of the warpage between the central part and the peripheral part with reference to the diagonal line of the sintered multilayer substrate. In addition, length 1
We decided to use the value per 0 cm. As a result, 0.0
It was confirmed that the amount of warpage was as small as 4 mm. Further, the positional accuracy of each part inside the circuit board was a good value of ± 0.4%.

【0047】次に、導体層の断面積を算出し、抵抗値か
ら導体層の導体抵抗率を求めた。ただし表面の配線に関
しては導体層に金属メッキなどを行わずに測定し、無機
質フィラーの添加の影響を調べた。その結果、9.5μ
Ωcmと低抵抗を示すことが分った。さらに、得られた基
板の2mmの導体部分にNiメッキをしてワイヤーを半田
付けした後引張強度試験を行い、AlN基板と導体層間
の接着強度を測定した。この結果、7.0kgと非常に高
い強度を有することが確認された。
Next, the cross-sectional area of the conductor layer was calculated, and the conductor resistivity of the conductor layer was obtained from the resistance value. However, the surface wiring was measured without metal plating on the conductor layer, and the influence of the addition of the inorganic filler was investigated. As a result, 9.5μ
It was found to show a low resistance of Ωcm. Further, a 2 mm conductor portion of the obtained substrate was plated with Ni and soldered with a wire, and then a tensile strength test was conducted to measure the adhesive strength between the AlN substrate and the conductor layer. As a result, it was confirmed to have a very high strength of 7.0 kg.

【0048】実施例2〜35および比較例1〜7 第1表に示すように、AlN粉末、焼結助剤粉末、その
他添加物および着色剤の種類および添加量、導体成分の
種類および添加量、無機質フィラーおよびVIII族添加物
の種類および添加量ならびに焼結条件を種々変えて、上
記実施例1と同様にしてAlN多層セラミック基板を作
製した。それぞれについて熱伝導率、引張強度、表裏平
行度および導体抵抗率を測定した。その結果を第2表に
示した。第2表から明らかなように、本発明に係る回路
基板では、導体層の密着強度が向上することが分る。
Examples 2-35 and Comparative Examples 1-7 As shown in Table 1, AlN powder, sintering aid powder, other additives and colorants, types and amounts, conductor components, types and amounts. An AlN multilayer ceramic substrate was prepared in the same manner as in Example 1 except that the type and amount of the inorganic filler and the Group VIII additive and the sintering conditions were variously changed. The thermal conductivity, tensile strength, front-back parallelism, and conductor resistivity were measured for each. The results are shown in Table 2. As is clear from Table 2, the circuit board according to the present invention has improved adhesion strength of the conductor layer.

【0049】[0049]

【表1】 [Table 1]

【0050】[0050]

【表2】 [Table 2]

【0051】[0051]

【表3】 [Table 3]

【0052】[0052]

【表4】 [Table 4]

【0053】[0053]

【表5】 [Table 5]

【0054】[0054]

【表6】 [Table 6]

【0055】例えば、実施例2では引張強度が8.0 k
g/2mm×2mmであるのに対し、比較例1では3.2 kg/
2mm×2mmと密着強度に著しい差異があることが分る。
また、すべての実施例に係る同時焼結体は、表裏平行度
が0.20 mm/対角線以下と反りが少なく、さらに実施
例の導体層は種々の無機質フィラーを含んでいるにも拘
らず、このような無機質フィラーを含まない比較例4〜
7のそれと比べても、導体層の抵抗率が低いことが分
る。
For example, in Example 2, the tensile strength is 8.0 k.
g / 2 mm × 2 mm, in Comparative Example 1, 3.2 kg /
It can be seen that there is a significant difference in the adhesion strength of 2 mm x 2 mm.
In addition, the co-sintered bodies according to all the examples have a front and back parallelism of 0.20 mm / diagonal line or less, which is small in warpage, and the conductor layers of the examples include various inorganic fillers. Comparative Example 4 containing no such inorganic filler
It can be seen that the resistivity of the conductor layer is lower than that of No. 7 as well.

【0056】焼結後の導体層の相対密度を測定するため
に、スクリーン印刷したときのペーストのグリーン密度
と同一になるように導体層組成物のプレス成形体を作製
し、回路基板を作製する条件と同一の条件で焼結した後
測定を行った。焼結後の両試料の微構造を観察して同一
の微構造をしていることを確認した。第2表に示される
ように、相対密度の測定値は大きく緻密であることが分
った。
In order to measure the relative density of the conductor layer after sintering, a press-molded body of the conductor layer composition is prepared so as to have the same green density as the paste when screen-printed, and a circuit board is prepared. The measurement was performed after sintering under the same conditions. The microstructures of both samples after sintering were observed and confirmed to have the same microstructure. As shown in Table 2, the measured values of relative density were found to be large and dense.

【0057】さらに、得られた回路基板を高熱伝導性封
止部材で封止し、ヘリウムリーク試験を行った。封止し
た試料を、5気圧のヘリウムガスで満たしたチャンバ中
に40分放置した後、チャンバ内を10-3torrオーダー
に減圧し、再び空気を1気圧まで導入した。このヘリウ
ム洗浄工程を3回行った後、試料をチャンバから取り出
し、空気中で30分放置した。このように処理した後、
ヘリウムリーク試験(ファインリークの検知)にかけ
た、ヘリウムリーク量の検出は、質量分析計で行った。
その結果、1.0×10-10atm・cc・s-1 未満であり、良
好な値であった。さらに、3M 製フロリナート40番を
120℃に暖めた中に前記試料を入れて3分間放置する
グロスリーク試験を行った。第2表に示されるように、
気泡の発生はなく、グロスリークも確認されなかった。
Further, the obtained circuit board was sealed with a high thermal conductive sealing member and a helium leak test was conducted. After the sealed sample was left in a chamber filled with helium gas at 5 atm for 40 minutes, the pressure in the chamber was reduced to the order of 10 −3 torr and air was introduced up to 1 atm again. After performing this helium cleaning step three times, the sample was taken out of the chamber and left in the air for 30 minutes. After processing like this,
The amount of helium leak that was subjected to the helium leak test (detection of fine leak) was detected by a mass spectrometer.
As a result, it was less than 1.0 × 10 −10 atm · cc · s −1 , which was a good value. Further, a gross leak test was conducted in which the above sample was placed in 3M Fluorinert No. 40 heated to 120 ° C. and left for 3 minutes. As shown in Table 2,
No bubbles were generated and no gross leak was confirmed.

【0058】実施例36 実施例1と同様な構成の絶縁層と導体層を用い、内部配
線層を有する25mm×25mm×2.6mmの窒化アルミニ
ウム多層回路基板を作製した。窒化アルミニウム多層回
路基板の他面側に、銀ろうを用いて240本のリードピ
ンを接合した。この後、半導体素子として消費電力10
W のシリコン素子を窒化アルミニウム多層回路基板の上
面に接合搭載し、ボンディングワイヤを付設して電気的
な接続を完了させた。
Example 36 A 25 mm × 25 mm × 2.6 mm aluminum nitride multilayer circuit board having an internal wiring layer was prepared by using an insulating layer and a conductor layer having the same structure as in Example 1. 240 lead pins were joined to the other side of the aluminum nitride multilayer circuit board using silver solder. After that, the power consumption of the semiconductor element is 10
A W silicon element was bonded and mounted on the upper surface of the aluminum nitride multilayer circuit board, and a bonding wire was attached to complete electrical connection.

【0059】さらに、155W/mKの熱伝導率を有する窒
化アルミニウム焼結体を用いて、放熱部材を兼ねる高熱
伝導性封止部材を実施例1の絶縁体部を作製する要領で
作製した。そして、窒化アルミニウム多層回路基板の上
面にこの封止部材をAu−Sn半田で接合し、さらに封
止部材上に直径25mmの円形7段構造の放熱フィンを配
置して目的とする半導体装置を得た。この半導体装置の
放熱性を評価するために、冷却風速を1.5m/s に設定
して△VBE法により熱抵抗を測定したところ、2.5
℃/Wと低熱抵抗値であり、放熱性の高い半導体装置が得
られることが判明した。
Further, an aluminum nitride sintered body having a thermal conductivity of 155 W / mK was used to produce a high thermal conductive sealing member which also serves as a heat radiating member in the same manner as the insulating portion of Example 1 was produced. Then, this sealing member is joined to the upper surface of the aluminum nitride multilayer circuit board by Au-Sn solder, and a radiation fin having a circular 7-step structure with a diameter of 25 mm is arranged on the sealing member to obtain a target semiconductor device. It was In order to evaluate the heat dissipation of this semiconductor device, the cooling air velocity was set to 1.5 m / s and the thermal resistance was measured by the ΔVBE method.
It was found that a semiconductor device having a low heat resistance value of ℃ / W and high heat dissipation can be obtained.

【0060】比較例8 実施例36において、絶縁層にアルミナを用いた構成の
絶縁体層と導体層を用い、実施例36と同様に半導体装
置を作製した。この半導体装置の熱抵抗値は、8.5℃
/Wと、実施例36のものと比較し、著しく高い値を示し
た。
Comparative Example 8 A semiconductor device was manufactured in the same manner as in Example 36 except that the insulating layer and the conductor layer each having alumina as the insulating layer were used in Example 36. The thermal resistance value of this semiconductor device is 8.5 ° C.
/ W was significantly higher than that of Example 36.

【0061】[0061]

【発明の効果】以上述べたように、本発明に係るAlN
セラミック回路基板は絶縁体が高熱伝導性を有し、導体
層の密着性が強固でかつ焼結過程における基板の変形が
少なく、さらに、引張強度は十分に実用可能な特性値を
示し、緻密で低抵抗率を有するなど様々な優れた性質を
有するものであり、その工業的価値は極めて大きいもの
である。
As described above, the AlN according to the present invention is
The ceramic circuit board has an insulator with high thermal conductivity, strong adhesion of the conductor layer and little deformation of the board during the sintering process, and the tensile strength shows a sufficiently practical characteristic value and is dense. It has various excellent properties such as low resistivity, and its industrial value is extremely large.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る多層セラミック回路基板を示す部
分切欠斜視図である。
FIG. 1 is a partially cutaway perspective view showing a multilayer ceramic circuit board according to the present invention.

【図2】本発明に係る多層セラミック回路基板を用いた
半導体装置(外部端子がリードピンの場合)を示した図
である。
FIG. 2 is a diagram showing a semiconductor device (when external terminals are lead pins) using a multilayer ceramic circuit board according to the present invention.

【図3】外部端子が半田ボールである、本発明に係る半
導体装置の部分断面図である。
FIG. 3 is a partial cross-sectional view of a semiconductor device according to the present invention in which external terminals are solder balls.

【符号の説明】[Explanation of symbols]

1,12 多層セラミック回路基板 2,14 絶縁層 3 導体層 4 ビアホール 5 放熱フィン 6 半導体素子 7 リードピン 8 ボンディングワイヤ 9 導体層(内部配線層) 9a ビアホール 10 表面配線層 11 配線パターン 12a 基板上面 12b 基板下面 13 高熱伝導性封止部材 13a 凸状外縁部 13b 凹状部 15 半田ボール A 接合面 1,12 Multilayer ceramic circuit board 2,14 Insulating layer 3 Conductor layer 4 Via hole 5 Radiating fin 6 Semiconductor element 7 Lead pin 8 Bonding wire 9 Conductor layer (internal wiring layer) 9a Via hole 10 Surface wiring layer 11 Wiring pattern 12a Substrate top surface 12b Substrate Lower surface 13 High thermal conductivity sealing member 13a Convex outer edge portion 13b Concave portion 15 Solder ball A Bonding surface

───────────────────────────────────────────────────── フロントページの続き (72)発明者 上野 文雄 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Fumio Ueno 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 AlNを主成分とする絶縁体部と、W、
Moの少なくとも一種を主成分とし、Ni、Coおよび
Feからなる群より選択される一種以上の元素を含有
し、更にAlNを0.1〜20重量%含有する導体部と
を、少なくともその一部に有することを特徴とする回路
基板。
1. An insulator portion containing AlN as a main component, W,
At least a part of a conductor part containing at least one kind of Mo as a main component, one or more elements selected from the group consisting of Ni, Co and Fe, and further containing 0.1 to 20% by weight of AlN. A circuit board having:
【請求項2】 導体部が、更にアルカリ土類元素および
希土類元素とからなる群より選択される一種以上の元素
を含む、請求項1記載の回路基板。
2. The circuit board according to claim 1, wherein the conductor portion further contains one or more elements selected from the group consisting of alkaline earth elements and rare earth elements.
【請求項3】 導体部が更にアルミナを含む、請求項1
記載の回路基板。
3. The conductor portion further contains alumina.
The described circuit board.
【請求項4】 導体部の相対密度が93%以上である、
請求項1記載の回路基板。
4. The relative density of the conductor portion is 93% or more,
The circuit board according to claim 1.
【請求項5】 請求項1記載の回路基板上に半導体素子
を搭載した半導体装置。
5. A semiconductor device in which a semiconductor element is mounted on the circuit board according to claim 1.
【請求項6】 W、Moの少なくとも一種を主成分と
し、Ni、CoおよびFe元素からなる群より選択され
る一種以上の元素を含有し、かつAlN粉末を含有する
導体ペーストを使用して、少なくとも一部の導体部を形
成し、かつ1,600℃未満で焼結することを特徴とす
る、AlN回路基板の製造方法。
6. A conductor paste containing at least one of W and Mo as a main component, containing at least one element selected from the group consisting of Ni, Co and Fe elements, and containing AlN powder, A method for manufacturing an AlN circuit board, which comprises forming at least a part of a conductor portion and sintering at less than 1,600 ° C.
JP6766696A 1996-03-25 1996-03-25 Ceramic circuit board and manufacture therefor Pending JPH09260544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6766696A JPH09260544A (en) 1996-03-25 1996-03-25 Ceramic circuit board and manufacture therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6766696A JPH09260544A (en) 1996-03-25 1996-03-25 Ceramic circuit board and manufacture therefor

Publications (1)

Publication Number Publication Date
JPH09260544A true JPH09260544A (en) 1997-10-03

Family

ID=13351563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6766696A Pending JPH09260544A (en) 1996-03-25 1996-03-25 Ceramic circuit board and manufacture therefor

Country Status (1)

Country Link
JP (1) JPH09260544A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000188453A (en) * 1998-12-21 2000-07-04 Kyocera Corp Wiring substrate and its manufacture
JP2002171044A (en) * 2000-11-29 2002-06-14 Kyocera Corp Wiring board
JP2002171045A (en) * 2000-11-29 2002-06-14 Kyocera Corp Wiring board
JP2005506666A (en) * 2001-10-18 2005-03-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Electroluminescent device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000188453A (en) * 1998-12-21 2000-07-04 Kyocera Corp Wiring substrate and its manufacture
JP2002171044A (en) * 2000-11-29 2002-06-14 Kyocera Corp Wiring board
JP2002171045A (en) * 2000-11-29 2002-06-14 Kyocera Corp Wiring board
JP4530525B2 (en) * 2000-11-29 2010-08-25 京セラ株式会社 Wiring board
JP4530524B2 (en) * 2000-11-29 2010-08-25 京セラ株式会社 Wiring board
JP2005506666A (en) * 2001-10-18 2005-03-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Electroluminescent device
US7557502B2 (en) 2001-10-18 2009-07-07 Tpo Displays Corp. Electroluminescent display with gas-tight enclosure

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