JPH0810734B2 - Semiconductor chip carrier - Google Patents
Semiconductor chip carrierInfo
- Publication number
- JPH0810734B2 JPH0810734B2 JP2215178A JP21517890A JPH0810734B2 JP H0810734 B2 JPH0810734 B2 JP H0810734B2 JP 2215178 A JP2215178 A JP 2215178A JP 21517890 A JP21517890 A JP 21517890A JP H0810734 B2 JPH0810734 B2 JP H0810734B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuits
- mounting portion
- step portion
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
本発明は、PGAなどICチップ等の半導体チップを実装
するために使用される半導体チップキャリアに関するも
のである。The present invention relates to a semiconductor chip carrier used for mounting a semiconductor chip such as an IC chip such as PGA.
ICチップ等の半導体チップの高密度化に伴って半導体
チップキャリアの回路数が増大しているために、半導体
チップキャリアとして回路を多層に設けた多層構造のも
のが提供されている。 第６図はその一例を示すものであり、エポキシ樹脂積
層板等の樹脂積層板を積層することによって作成される
多層積層板でキャリア基板２を形成し、キャリア基板２
には信号線や電源線、アース線などの回路1a,1b,1c…が
多層に設けてある。この各回路1a,1b,1c…はキャリア基
板２に貫通して設けらたスルーホール９の内周のスルー
ホールメッキ層9aを介して電気的に接続してある。そし
てキャリア基板２の表面に開口するように半導体チップ
搭載部３が凹設してあり、半導体チップ搭載部３内に半
導体チップ10を搭載すると共に半導体チップ搭載部３の
開口部の周囲に形成したボンディング用回路11にワイヤ
ー12をボンディングすることによって、半導体チップ10
を必要な回路1a,1b,1c…に接続することができる。Since the number of circuits in a semiconductor chip carrier is increasing with the increase in the density of semiconductor chips such as IC chips, a semiconductor chip carrier having a multilayer structure in which circuits are provided in multiple layers is provided. FIG. 6 shows an example thereof, in which the carrier substrate 2 is formed of a multi-layer laminated board made by laminating resin laminated boards such as epoxy resin laminated boards.
Are provided in multiple layers with circuits 1a, 1b, 1c, etc. such as signal lines, power lines, and ground lines. The circuits 1a, 1b, 1c ... Are electrically connected to each other through a through-hole plating layer 9a on the inner periphery of a through-hole 9 penetrating the carrier substrate 2. The semiconductor chip mounting portion 3 is recessed so as to open on the surface of the carrier substrate 2. The semiconductor chip 10 is mounted in the semiconductor chip mounting portion 3 and formed around the opening of the semiconductor chip mounting portion 3. By bonding the wire 12 to the bonding circuit 11, the semiconductor chip 10
Can be connected to the required circuits 1a, 1b, 1c ...
しかし、半導体チップの高密度化に伴って回路1a,1b,
1c…の配線密度が高まっており、回路1a,1b,1c…の配線
上の制限からスルーホール９を設けることが難しくなっ
ているのが現状である。このことを逆にいえば、スルー
ホール９によって回路1a,1b,1c…の配線の設計の自由度
が制約され、半導体チップの高密度化に対応しきれなく
なっているという問題が生じているものである。 本発明は上記の点に鑑みて為されたものであり、スル
ーホールを設ける必要なく回路間の接続をおこなうこと
ができる半導体チップキャリアを提供することを目的と
するものである。However, with the increase in the density of semiconductor chips, circuits 1a, 1b,
At present, the wiring density of 1c ... Is increasing, and it is difficult to provide the through holes 9 due to restrictions on the wiring of the circuits 1a, 1b, 1c. To put it the other way around, the through hole 9 restricts the degree of freedom in designing the wiring of the circuits 1a, 1b, 1c, ... Is. The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor chip carrier capable of connecting circuits without providing a through hole.
本発明に係る半導体チップキャリアは、多層の回路1
a,1b,1c…を設けてキャリア基板２を形成すると共にキ
ャリア基板２の表面に半導体チップ搭載部３を凹設し、
半導体チップ搭載部３の周囲においてキャリア基板２に
凹段部４を設け、凹段部４の内周面に導体層５を設ける
と共に凹段部４の内周に露出する複数の回路1a,1b,1c…
をこの導体層５で接続し、凹段部４の底面に形成された
ボンディング用回路11と半導体チップ搭載部３に搭載さ
れた半導体チップ10との間にワイヤー12をボンディング
して成ることを特徴とするものである。The semiconductor chip carrier according to the present invention is a multilayer circuit 1
a, 1b, 1c ... Are provided to form the carrier substrate 2 and the semiconductor chip mounting portion 3 is recessed on the surface of the carrier substrate 2,
A plurality of circuits 1a, 1b provided on the carrier substrate 2 around the semiconductor chip mounting portion 3 are provided with a recessed step portion 4, a conductor layer 5 is provided on the inner peripheral surface of the recessed step portion 4 and exposed on the inner periphery of the recessed step portion 4. , 1c ...
Are connected by the conductor layer 5, and a wire 12 is bonded between the bonding circuit 11 formed on the bottom surface of the concave step portion 4 and the semiconductor chip 10 mounted on the semiconductor chip mounting portion 3. It is what
本発明にあっては、半導体チップ搭載部３の周囲にお
いてキャリア基板２に設けた凹段部４の内周面に導体層
５を設けると共に凹段部４の内周に露出する複数の回路
1a,1b,1c…をこの導体層５で接続するようにしているた
めに、半導体チップ搭載部３の周囲に導体層５で各回路
1a,1b,1c…間の接続をおこなうことができ、各回路1a,1
b,1c…の接続のためにスルーホールを設ける必要がなく
なる。In the present invention, the conductor layer 5 is provided on the inner peripheral surface of the recessed step portion 4 provided on the carrier substrate 2 around the semiconductor chip mounting portion 3 and a plurality of circuits exposed on the inner periphery of the recessed step portion 4 are provided.
Since the conductor layers 1a, 1b, 1c ... Are connected to each other by the conductor layer 5, each circuit is formed around the semiconductor chip mounting portion 3 by the conductor layer 5.
Connection between 1a, 1b, 1c… can be done and each circuit 1a, 1c
There is no need to provide through holes for b, 1c ... connections.
以下本発明を実施例によって詳述する。 第１図は本発明の一実施例を示すものであり、エポキ
シ樹脂積層板やイミド樹脂積層板等の樹脂積層板を積層
することによって作成される多層積層板でキャリア基板
２を形成するようにしてあり、各樹脂積層板の表面に積
層した胴箔等をエッチング加工して形成した導体によっ
て、キャリア基板２には信号線や電源線、アース線など
の回路1a,1b,1c…が多層に設けてある。またキャリア基
板２の表面に開口するように座ぐり加工などして半導体
チップ搭載部３が凹設してあり、半導体チップ搭載部３
の周囲には半導体チップ搭載部３を囲むように凹段部４
が座ぐり加工などで設けてある。このように凹段部４を
設けることによって、回路1a,1b,1c…の一部が凹段部４
の内周に露出されることになる。また半導体チップ搭載
部３にはその底面から側面にかけて銅メッキ等のメッキ
層13が形成してあり、このメッキ層13は一部の回路1a,1
b,1c…に接続するようにしてある。また凹段部４の底面
には第１図のようにボンディング用回路11が設けてあ
る。そして、凹段部４の内周面に銅メッキなどを施すこ
とによって導体層５を形成し、導体層５を回路1a,1b,1c
…の凹段部４に露出する部分に接続させることによっ
て、必要とする回路1a,1b,1c…間の電気的な接続をおこ
なうようにしてある。 上記のようにして作成される半導体チップキャリアに
あって、ICチップ等の半導体チップ10を半導体チップ搭
載部３内に配設して接着等すると共に、第１図のように
凹段部４の底面に設けたボンディング用回路11と半導体
チップ10との間に金線等のワイヤー12をボンディングす
ることによって、半導体チップ10を回路1a,1b,1c…と接
続して半導体チップ10の実装をおこなうことができる。
そしてこの半導体チップキャリアＡでは、凹段部４の内
周面に形成した導体層５で回路1a,1b,1c…間の接続をお
こなうことができるために、従来のようにスルーホール
を加工して回路1a,1b,1c…間の接続をおこなうような必
要がなくなる。従って、スルーホールによって回路1a,1
b,1c…の配線の設計の自由度が制約されるようなことが
なくなり、半導体チップの高密度化に対応した配線設計
を自由におこなうことが可能になる。またこの導体層５
は半導体チップ搭載部３の周囲に存在するために、電源
線やアース線となる回路1a,1b,1c…に半導体チップ10か
ら最短距離で接続することが可能になり、半導体チップ
10の高速化に対応することが容易になる。 第２図は本発明の他の実施例を示すものであり、凹段
部４の内周面に上下複数箇所において導体層５を設け、
回路1a,1b,1c…の接続を複数箇所でおこなうことができ
るようにしてある。またこの第２図の実施例のように、
配線設計に支障にならない場合にはスルーホール９を設
けるようにしてもよい。第３図の実施例では、凹段部４
を二段構造に形成し、下段4aと上段4bの内周面にそれぞ
れ導体層５を設け、回路1a,1b,1c…の接続を下段4aと上
段4bとで複数箇所においておこなうことができるように
してある。第４図の実施例では、半導体チップ搭載部３
をキャリア基板２の上下両面に設けると共に凹段部４も
上下両面に設け、各凹段部４において導体層５で回路1
a,1b,1c…の接続がおこなえるようにしてある。第５図
（ａ）（ｂ）の実施例は、平面多角形状に形成される凹
段部４の内周の各面にそれぞれ電気的に接続されない独
立した導体層５を設け、各導体層５で回路1a,1b,1c…の
接続をおこなうようにしたものである。Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 shows an embodiment of the present invention, in which the carrier substrate 2 is formed of a multi-layer laminated plate prepared by laminating resin laminated plates such as an epoxy resin laminated plate and an imide resin laminated plate. The conductors formed by etching the body foil etc. laminated on the surface of each resin laminated plate are formed on the carrier substrate 2 in multiple layers of circuits 1a, 1b, 1c ... It is provided. Further, the semiconductor chip mounting portion 3 is provided with a recess by boring so as to open on the surface of the carrier substrate 2.
A concave step portion 4 is formed around the semiconductor chip mounting portion 3 so as to surround the semiconductor chip mounting portion 3.
Are provided by spot facing. By providing the concave step portion 4 in this manner, a part of the circuits 1a, 1b, 1c ...
Will be exposed to the inner circumference. In addition, a plating layer 13 such as copper plating is formed on the semiconductor chip mounting portion 3 from the bottom surface to the side surfaces thereof.
It is connected to b, 1c .... A bonding circuit 11 is provided on the bottom surface of the recessed step portion 4 as shown in FIG. Then, the conductor layer 5 is formed by applying copper plating or the like to the inner peripheral surface of the recessed step portion 4, and the conductor layer 5 is connected to the circuits 1a, 1b, 1c.
The required circuits 1a, 1b, 1c, ... Are electrically connected by connecting to the exposed portions of the concave step portion 4. In the semiconductor chip carrier created as described above, the semiconductor chip 10 such as an IC chip is arranged in the semiconductor chip mounting portion 3 and bonded, and the concave step portion 4 is formed as shown in FIG. By bonding a wire 12 such as a gold wire between the bonding circuit 11 provided on the bottom surface and the semiconductor chip 10, the semiconductor chip 10 is connected to the circuits 1a, 1b, 1c ... And the semiconductor chip 10 is mounted. be able to.
In this semiconductor chip carrier A, since the conductor layers 5 formed on the inner peripheral surface of the concave step portion 4 can connect the circuits 1a, 1b, 1c ..., Through holes are processed as in the conventional case. It becomes unnecessary to connect the circuits 1a, 1b, 1c ... Therefore, the circuit 1a, 1
The degree of freedom in the wiring design of b, 1c ... Is not restricted, and the wiring design corresponding to the high density of the semiconductor chip can be freely performed. Also, this conductor layer 5
Exists around the semiconductor chip mounting portion 3, so that it becomes possible to connect the circuits 1a, 1b, 1c, which are power lines and ground lines, from the semiconductor chip 10 at the shortest distance.
It becomes easy to support 10 speedups. FIG. 2 shows another embodiment of the present invention, in which the conductor layers 5 are provided on the inner peripheral surface of the concave step portion 4 at a plurality of upper and lower positions,
The circuits 1a, 1b, 1c ... Can be connected at a plurality of points. Further, as in the embodiment of FIG. 2,
The through hole 9 may be provided if it does not hinder the wiring design. In the embodiment shown in FIG. 3, the concave step portion 4
Is formed in a two-stage structure, conductor layers 5 are provided on the inner peripheral surfaces of the lower stage 4a and the upper stage 4b, respectively, so that the circuits 1a, 1b, 1c ... Can be connected at a plurality of points in the lower stage 4a and the upper stage 4b. I am doing it. In the embodiment shown in FIG. 4, the semiconductor chip mounting portion 3
Are provided on both the upper and lower surfaces of the carrier substrate 2, and the concave step portions 4 are also provided on the upper and lower surfaces.
The connection of a, 1b, 1c ... can be done. In the embodiment shown in FIGS. 5A and 5B, independent conductor layers 5 that are not electrically connected to each other are provided on the inner peripheral surfaces of the concave step portion 4 formed in a planar polygonal shape. The circuit 1a, 1b, 1c ... Is connected.
上述のように本発明にあっては、多層の回路を設けて
キャリア基板を形成すると共にキャリア基板の表面に半
導体チップ搭載部を凹設し、半導体チップ搭載部の周囲
においてキャリア基板に凹段部を設け、凹段部の内周面
に導体層を設けると共に凹段部の内周に露出する複数の
回路をこの導体層で接続するようにしたので、半導体チ
ップ搭載部の周囲に設けた導体層で各回路間の接続をお
こなうことができ、各回路の接続のためにスルーホール
を設ける必要がなくなるものであり、スルーホールによ
って回路の配線の設計の自由度が制約されるようなこと
がなくなり、半導体チップの高密度化や高速化に対応し
た配線設計を自由におこなうことが可能になると共に、
また凹段部の底面に形成されたボンディング用回路と半
導体チップ搭載部に搭載された半導体チップとの間にワ
イヤーボンディングするようにしたので、回路間の接続
をおこなう導体層を形成するために設けた凹段部を利用
してその底面にボンディング用回路を設けることができ
るものである。As described above, according to the present invention, a multi-layer circuit is provided to form a carrier substrate, a semiconductor chip mounting portion is recessed on the surface of the carrier substrate, and a recessed step portion is formed on the carrier substrate around the semiconductor chip mounting portion. Since the conductor layer is provided on the inner peripheral surface of the recessed step portion and a plurality of circuits exposed on the inner periphery of the recessed step portion are connected by this conductor layer, the conductor provided around the semiconductor chip mounting portion is provided. Connections between circuits can be made in layers, and it is not necessary to provide through holes for connecting each circuit.Thus, through holes may limit the freedom of circuit wiring design. It becomes possible to freely design wiring corresponding to higher density and higher speed of semiconductor chips,
In addition, since the wire bonding is performed between the bonding circuit formed on the bottom surface of the recessed portion and the semiconductor chip mounted on the semiconductor chip mounting portion, it is provided to form the conductor layer for connecting the circuits. It is possible to provide a bonding circuit on the bottom surface by utilizing the concave step portion.
第１図は本発明の一実施例の断面図、第２図乃至第４図
はそれぞれ同上の他の実施例の断面図、第５図（ａ）
（ｂ）は同上のさらに他の実施例の断面図と平面図、第
６図は従来例の断面図である。 1a,1b,1cは回路、２はキャリア基板、３は半導体チップ
搭載部、４は凹段部、５は導体層、10は半導体チップ、
11はボンディング用回路、12はワイヤーである。FIG. 1 is a sectional view of an embodiment of the present invention, FIGS. 2 to 4 are sectional views of other embodiments of the same, respectively, and FIG. 5 (a).
(B) is a sectional view and a plan view of still another embodiment of the above, and FIG. 6 is a sectional view of a conventional example. 1a, 1b, 1c are circuits, 2 is a carrier substrate, 3 is a semiconductor chip mounting portion, 4 is a concave step portion, 5 is a conductor layer, 10 is a semiconductor chip,
Reference numeral 11 is a bonding circuit, and 12 is a wire.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 樋口 徹 大阪府門真市大字門真1048番地 松下電工 株式会社内 (56)参考文献 特開 昭58−197861（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Higuchi 1048, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (56) References JP-A-58-197861 (JP, A)
Claims (1)
ると共にキャリア基板の表面に半導体チップ搭載部を凹
設し、半導体チップ搭載部の周囲においてキャリア基板
に凹段部を設け、凹段部の内周面に導体層を設けると共
に凹段部の内周に露出する複数の回路をこの導体層で接
続し、凹段部の底面に形成されたボンディング用回路と
半導体チップ搭載部に搭載された半導体チップとの間に
ワイヤーボンディングして成ることを特徴とする半導体
チップキャリア。1. A multi-layer circuit is provided to form a carrier substrate, and a semiconductor chip mounting portion is recessed on the surface of the carrier substrate, and a recessed step portion is provided on the carrier substrate around the semiconductor chip mounting portion. A conductor layer is provided on the inner peripheral surface of the, and a plurality of circuits exposed on the inner periphery of the recessed step portion are connected by this conductor layer, and mounted on the bonding circuit formed on the bottom surface of the recessed step portion and the semiconductor chip mounting portion. A semiconductor chip carrier characterized by being wire-bonded to a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2215178A JPH0810734B2 (en) | 1990-08-14 | 1990-08-14 | Semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2215178A JPH0810734B2 (en) | 1990-08-14 | 1990-08-14 | Semiconductor chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0497548A JPH0497548A (en) | 1992-03-30 |
| JPH0810734B2 true JPH0810734B2 (en) | 1996-01-31 |
Family
ID=16667964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2215178A Expired - Lifetime JPH0810734B2 (en) | 1990-08-14 | 1990-08-14 | Semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810734B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197861A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Ceramic substrate and manufacture thereof |
| JPS5910240A (en) * | 1982-07-09 | 1984-01-19 | Nec Corp | Semiconductor device |
| JPS6256664A (en) * | 1985-09-03 | 1987-03-12 | フオ−ド モ−タ− カンパニ− | Transmission using fluid type torque converter |
| US5235211A (en) * | 1990-06-22 | 1993-08-10 | Digital Equipment Corporation | Semiconductor package having wraparound metallization |
-
1990
- 1990-08-14 JP JP2215178A patent/JPH0810734B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0497548A (en) | 1992-03-30 |
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