JPH08107133A - Method of connecting chip part to board - Google Patents

Method of connecting chip part to board

Info

Publication number
JPH08107133A
JPH08107133A JP26308894A JP26308894A JPH08107133A JP H08107133 A JPH08107133 A JP H08107133A JP 26308894 A JP26308894 A JP 26308894A JP 26308894 A JP26308894 A JP 26308894A JP H08107133 A JPH08107133 A JP H08107133A
Authority
JP
Japan
Prior art keywords
substrate
chip component
wiring pattern
bumps
pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26308894A
Other languages
Japanese (ja)
Other versions
JP3095959B2 (en
Inventor
Masanori Iwata
征憲 岩田
Tatsuya Saito
達也 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP06263088A priority Critical patent/JP3095959B2/en
Publication of JPH08107133A publication Critical patent/JPH08107133A/en
Application granted granted Critical
Publication of JP3095959B2 publication Critical patent/JP3095959B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To provide a method of securely connecting chip parts to a board without causing a short circuit even if high-density mounting is made on wiring patterns lessened in space between them. CONSTITUTION: When a chip part is made to bear against a wiring pattern through the intermediary of metal bumps, a prescribed pressure is applied onto a pressing member so as to absorb the irregularity of the metal bumps in height, to enable the bumps to come surely into contact with the wiring pattern, the metal bumps are fused by heating, the pressing member is controlled in position and lessened in pressing force corresponding to a fusion state of the metal bumps, and furthermore the pressing member is controlled to widen the gap between the chip part and the board so as to eliminate a thermal expansion effect of the pressing member. Moreover, the pressing member is controlled to adjust the gap between the chip part and the board so as to repress an effect caused by a pressure change induced by the shrinkage of the board when the metal bumps are hardened by cooling after heating is stopped.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、基板上へのチップ部品
の接続方法に関し、特に半田バンプ等の金属バンプを利
用した半導体等のチップ部品の基板上への高密度接続方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting chip parts on a substrate, and more particularly to a method for high density connection of chip parts such as semiconductors to a substrate using metal bumps such as solder bumps.

【0002】[0002]

【従来の技術】近年、半導体等のチップ部品の小型化、
高集積化及び多ピン化に伴い基板に対するこれらチップ
部品の高密度接続技術の確立が不可欠となっている。
2. Description of the Related Art In recent years, miniaturization of chip parts such as semiconductors,
With the high integration and the increase in the number of pins, it is essential to establish a high-density connection technology for these chip parts to the substrate.

【0003】従来より、セラミック基板、ガラス基板、
エポキシ樹脂基板、あるいはテープキャリア等の基板上
へのチップ部品の接続方法としては、半田バンプを利用
したリフローによるセルフアライメント接続法が一般的
に用いられている。この方法では、チップ部品の接続パ
ッド上もしくは基板上に形成された配線パターン上に予
めほぼ球形の半田バンプが形成され、この半田バンプを
介してチップ部品を前記配線パターン上に載せ、半田バ
ンプを加熱することにより、溶融した半田バンプの表面
張力の作用でチップ部品が配線パターン上に位置決め・
接続されるものである。一方、テープキャリア等のプラ
スチックフィルム基板へのチップ部品の接続方法として
は、金バンプと錫メッキパターンとを高温高圧下で熱圧
着させる熱圧着法又はワイヤボンディング法が一般的に
用いられている。
Conventionally, ceramic substrates, glass substrates,
As a method of connecting a chip component to a substrate such as an epoxy resin substrate or a tape carrier, a self-alignment connection method by reflow using solder bumps is generally used. In this method, substantially spherical solder bumps are previously formed on the connection pads of the chip components or on the wiring pattern formed on the substrate, the chip components are placed on the wiring pattern via the solder bumps, and the solder bumps are formed. By heating, the chip components are positioned on the wiring pattern due to the surface tension of the melted solder bumps.
It is connected. On the other hand, as a method for connecting a chip component to a plastic film substrate such as a tape carrier, a thermocompression bonding method or a wire bonding method in which a gold bump and a tin plating pattern are thermocompression bonded under high temperature and high pressure is generally used.

【0004】しかしながら、上記したリフロー方式の接
続方法では、半田バンプはチップ部品の自重による加圧
力を受けるため、図に示すように、チップ部品1の接続
パッド2上の半田バンプ3は、溶融時に基板(図示せ
ず)上の配線パターン4とチップ部品1上の接続パッド
2との間で樽状に押しつぶされた状態で冷却・固化され
る。このため、隣接する半田バンプ3,3同士が接触し
てブリッジを形成する危険性が高くなる。この半田バン
プ3,3同士の接触を回避するためには接続パッド及び
配線パターン4の配設ピッチ間隔を広げる必要があるた
め、高密度接続化か困難になっている。
However, in the above-described reflow-type connection method, the solder bumps are pressed by the weight of the chip component, so that the solder bumps 3 on the connection pads 2 of the chip component 1 are melted as shown in the figure. Between the wiring pattern 4 on the substrate (not shown) and the connection pads 2 on the chip component 1, the material is cooled and solidified while being crushed in a barrel shape. Therefore, there is a high risk that adjacent solder bumps 3, 3 will come into contact with each other to form a bridge. In order to avoid the contact between the solder bumps 3 and 3, it is necessary to widen the arrangement pitch interval of the connection pad and the wiring pattern 4, so that high density connection is difficult.

【0005】また、チップ部品と基板とを半田バンプ等
の金属バンプを用いて接続する構造においては、温度サ
イクル負荷をかけたときのチップ部品と基板との熱膨張
係数の差に起因した熱疲労の問題を考える必要がある
が、特にリフロー方式の接続法で形成される略樽状の接
続半田3は横断面積に対する接続高さ比が小さいため、
熱疲労による導通不良が早期に発生しやすく、高信頼性
の確保が困難となっている。
Further, in a structure in which the chip component and the substrate are connected by using metal bumps such as solder bumps, thermal fatigue caused by a difference in thermal expansion coefficient between the chip component and the substrate when a temperature cycle load is applied. However, since the approximately barrel-shaped connection solder 3 formed by the reflow connection method has a small connection height to cross-sectional area ratio,
Conduction failure due to thermal fatigue is likely to occur at an early stage, making it difficult to secure high reliability.

【0006】一方、上述した熱圧着法においては、配線
ピッチ間隔が100μm程度の高密度接続が可能である
が、チップ部品に高温高圧によるダメージを与える危険
性があり、また金バンプを用いるためコストが高くなる
欠点がある。さらに、高精度・高剛性の装置が必要で、
300ピン以上の多ピン同時接続となると加圧荷重が大
きすぎて実現困難になるという問題がある。また、図に
示すように、チップ部品1上の接続パッド2と基板(図
示せず)上の配線パターン4とを接続する金バンプ5は
高圧下で板状もしくは膜状に押しつぶされるため、温度
サイクル負荷をかけたときのチップ部品1と基板との熱
膨張係数の差に起因した疲労の点については、リフロー
方式の接続法と同様の問題が生じている。
On the other hand, in the thermocompression bonding method described above, high-density connection with a wiring pitch interval of about 100 μm is possible, but there is a risk of damaging chip components due to high temperature and high pressure, and the cost is increased because gold bumps are used. Has the drawback of being high. In addition, a device with high precision and high rigidity is required,
If multiple pins of 300 pins or more are connected at the same time, there is a problem in that it is difficult to realize because the pressure load is too large. Further, as shown in the figure, since the gold bumps 5 connecting the connection pads 2 on the chip component 1 and the wiring patterns 4 on the substrate (not shown) are crushed into a plate or film under high pressure, Regarding the point of fatigue caused by the difference in thermal expansion coefficient between the chip component 1 and the substrate when a cycle load is applied, the same problem as in the reflow connection method occurs.

【0007】ワイヤボンディング法はボンディングを1
本ずつ行なうため、ボンディング作業に長時間を要す
る。従って、多ピンのチップ部品の接続には適さない。
The wire bonding method uses one bonding
Since it is performed one by one, the bonding work takes a long time. Therefore, it is not suitable for connecting multi-pin chip parts.

【0008】上述したこれらの接続方法欠点を解決する
方法として、配線パターンが形成されたテープキャリア
からなる基板と接続パッドに半田バンプが形成されたチ
ップ部品とを所定の位置決めを行なって重ね合わせ、半
田バンプを加熱溶融した後、チップ部品と基板との間の
間隙を調整し半田バンプに圧力がかからないように制御
することにより、半田バンプの形状が略鼓状となるよう
にして接続する方法が提案されている。
As a method for solving the above-mentioned drawbacks of the connection method, a substrate made of a tape carrier having a wiring pattern formed thereon and a chip component having a solder bump formed on a connection pad are aligned with each other at a predetermined position and superposed, After heating and melting the solder bumps, it is possible to adjust the gap between the chip component and the substrate and control so that pressure is not applied to the solder bumps, so that the solder bumps are connected in a substantially drum shape. Proposed.

【0009】この方法によると、半田バンプがチップ部
品と基板との間で溶融された後に鼓状をなして固化して
いるため、隣接する接続パッド間あるいは配線パターン
間で半田バンプ同士の接触による危険性が無くなるとと
もに、半田バンプを樽状に押しつぶして固化させた場合
に比べて半田の横断面積に対する接続高さ比が増大する
ので、熱疲労による導通不良の発生を抑制することがで
きる。
According to this method, since the solder bumps are melted between the chip component and the substrate and then solidify in a drum shape, the solder bumps may contact each other between adjacent connection pads or wiring patterns. In addition to eliminating the risk, the connection height ratio to the cross-sectional area of the solder is increased as compared with the case where the solder bump is crushed in a barrel shape and solidified, so that the occurrence of conduction failure due to thermal fatigue can be suppressed.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、上述の
接続方法においては、加圧加熱ツールにて半田バンプに
適度の荷重を与えるとともに半田バンプを溶融させる
が、この加圧加熱ツールが熱膨張することによりチップ
部品と基板との間の間隙が溶融時に設定した間隙よりも
小さくなり、これにより半田バンプの形状が樽状になる
ものがあり不良発生の要因となっている。さらに、冷却
時の半田バンプあるいはキャリアテープの収縮による応
力が発生し、圧力変動を生じ安定した接続構造が得られ
ないと言った不具合があった。
However, in the above-described connection method, the pressure heating tool applies an appropriate load to the solder bump and melts the solder bump, but the pressure heating tool thermally expands. As a result, the gap between the chip component and the substrate becomes smaller than the gap set at the time of melting, which causes the shape of the solder bump to be barrel-shaped, which is a cause of defectiveness. Further, there is a problem that stress due to contraction of the solder bumps or the carrier tape at the time of cooling causes pressure fluctuation and a stable connection structure cannot be obtained.

【0011】[0011]

【課題を解決するための手段】本発明は上述の課題を解
決するためになされたもので、チップ部品あるいは基板
上の配線パターン上に形成された金属バンプを介して前
記チップ部品と基板上の配線パターンとを当接させ、金
属バンプを加熱し溶融させた後に冷却・固化させること
によりチップ部品を基板上に接続するチップ部品の基板
上への接続方法であって、前記金属バンプを介したチッ
プ部品と前記配線パターンとの当接時に加圧部材にて所
定の加圧力を加え、該金属バンプの高さのばらつきを吸
収して前記配線パターンとの接触を確実に行なわせた
後、加熱して前記金属バンプを溶融させるとともにこの
溶融状態に合わせて前記加圧部材を制御して加圧力を弱
め、さらにその後該加圧部材の熱膨張による影響を除く
ために前記チップ部品と基板との間隙を広げるように制
御し、さらにその後加熱を停止し金属バンプを冷却・固
化させる際には冷却時の基板の収縮による圧力の変動の
影響を押さえるように前記チップ部品と基板との間隙を
制御することを特徴とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is achieved by means of metal bumps formed on a chip component or a wiring pattern on the substrate through the chip component and the substrate. A method for connecting a chip component onto a substrate by bringing the metal bump into contact with the metal bump, heating and melting the metal bump, and then cooling and solidifying the metal bump. When the chip component and the wiring pattern are brought into contact with each other, a predetermined pressing force is applied by the pressing member to absorb the variation in the height of the metal bump to ensure the contact with the wiring pattern, and then the heating. Then, the metal bump is melted, and the pressure member is controlled in accordance with the melted state so as to weaken the pressing force, and thereafter, the tip portion is removed in order to remove the influence of the thermal expansion of the pressure member. Control to widen the gap between the chip component and the substrate, and when the heating is stopped and the metal bumps are cooled and solidified, the influence of the pressure fluctuation due to the contraction of the substrate during cooling is suppressed. It is characterized by controlling the gap of.

【0012】[0012]

【作用】上述の手段は以下のように作用する。The above-mentioned means operates as follows.

【0013】加熱前から、半田バンプの溶融及び冷却・
固化されるまで熱膨張及び冷却時の収縮による影響を最
低限に押さえることで、チップ部品と基板との間隙を常
に一定の関係に保持できる。
Before heating, melting and cooling of solder bumps
By minimizing the effects of thermal expansion and contraction during cooling until solidified, the gap between the chip component and the substrate can always be maintained in a constant relationship.

【0014】[0014]

【実施例】以下に本発明の実施例であるチップ部品の接
続方法について、その手順に従って説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of connecting chip components according to an embodiment of the present invention will be described below in accordance with the procedure.

【0015】まず、受け側ステージ5の表面にチップ部
品1を半田バンプ3が形成された接続パッド(図示せ
ず)が上方を向くように、かつ、チップ部品1が動かな
いように吸着させて搭載し、その上に配線パターン(図
示せず)が接続パッドと対向するようにテープキャリア
2からなる基板を重ね、このテープキャリア2の配線パ
ターンが形成されていない背面側から加圧・加熱用のツ
ール4を下降させることで、テープキャリア2を所定圧
力で加圧する。
First, the chip component 1 is adsorbed on the surface of the receiving stage 5 so that the connection pads (not shown) on which the solder bumps 3 are formed face upward and the chip component 1 does not move. It is mounted, and a substrate composed of the tape carrier 2 is laid on it so that the wiring pattern (not shown) faces the connection pads, and the tape carrier 2 is for pressing and heating from the back side where the wiring pattern is not formed. The tape carrier 2 is pressed at a predetermined pressure by lowering the tool 4 of.

【0016】次いでチップ部品1を搭載した受け側ステ
ージ5を上昇させ、圧力センサ6で受け側ステージ5に
かかる圧力の増加を検知し、半田バンプ3がテープキャ
リア2の配線パターンに接触したことを確認した後、受
け側ステージ5の上昇を停止する(図2の状態)。
Next, the receiving stage 5 on which the chip component 1 is mounted is raised, the pressure sensor 6 detects an increase in the pressure applied to the receiving stage 5, and the solder bump 3 contacts the wiring pattern of the tape carrier 2. After checking, the ascending of the receiving stage 5 is stopped (state of FIG. 2).

【0017】次にツール4の温度を上昇させキャリアテ
ープ2側から半田バンプ3を加熱し溶融させる。この時
ツール4が加熱することによりツール4自体の熱膨張
と、テープキャリア3が加熱されることによるテープキ
ャリア3の熱膨張とが起こる。このうちテープキャリア
3の熱膨張によりツール4とテープキャリア2の間の荷
重バランスが崩れ、何も制御しないとツール4が5μm
程度下降するので、この分ツール4を上昇させてテープ
キャリア3とツール4との初期に設定した位置関係を維
持する。また、ツール4自体の熱膨張でツール4自体が
8μm程度下降するので、このツール4の下降分は受け
側ステージ5を下降させ吸収する。これらの制御により
ツール4及びテープキャリア3の熱膨張による影響は解
消され、溶融された半田バンプ3でできた間隙は、初期
の設定間隙に対し減少することが無く熱の供給がなされ
る。
Next, the temperature of the tool 4 is raised to heat and melt the solder bumps 3 from the side of the carrier tape 2. At this time, heating of the tool 4 causes thermal expansion of the tool 4 itself and heating of the tape carrier 3 causes thermal expansion of the tape carrier 3. Of these, the load balance between the tool 4 and the tape carrier 2 is lost due to the thermal expansion of the tape carrier 3, and if nothing is controlled, the tool 4 is 5 μm.
Since the tool 4 is lowered to some extent, the tool 4 is raised by this amount and the initial positional relationship between the tape carrier 3 and the tool 4 is maintained. Further, since the tool 4 itself descends by about 8 μm due to the thermal expansion of the tool 4 itself, the descending amount of this tool 4 descends and absorbs the receiving stage 5. By these controls, the influence of the thermal expansion of the tool 4 and the tape carrier 3 is eliminated, and the gap formed by the melted solder bumps 3 is supplied to the gap without decreasing to the initial set gap.

【0018】次に、溶融した半田バンプ3が略鼓状の形
状をなすように、チップ部品1とテープキャリア2との
間に間隙間もたせるために、所定位置までツール4及び
受け側ステージ5を移動させる(図3の状態)。
Next, the tool 4 and the receiving-side stage 5 are moved to a predetermined position in order to leave a gap between the chip component 1 and the tape carrier 2 so that the molten solder bump 3 has a substantially drum shape. Move (state of FIG. 3).

【0019】そして、溶融した半田バンプ3を冷却・固
化させるが、冷却時のテープキャリア2の収縮によりツ
ール4にかかる圧力が増加する。この圧力増加分を吸収
するため、圧力が変化しない速度で(ツール4にかかる
圧力を図示しない圧力センサで測定しながら)ゆっくり
と上昇させる。これと同時に、半田バンプ3の冷却によ
り半田バンプ3は収縮し、チップ部品1あるいはテープ
キャリア2から引きはがされる方向に応力がかかるが、
これを防止するために受け側ステージ5を上昇させ、収
縮時の圧力変化が生じないように制御する。
Then, the melted solder bumps 3 are cooled and solidified, but the pressure applied to the tool 4 increases due to the contraction of the tape carrier 2 during cooling. In order to absorb this increase in pressure, the pressure is slowly increased at a speed at which the pressure does not change (while measuring the pressure applied to the tool 4 by a pressure sensor (not shown)). At the same time, the solder bumps 3 contract due to the cooling of the solder bumps 3 and stress is applied in the direction of peeling from the chip component 1 or the tape carrier 2.
In order to prevent this, the receiving stage 5 is raised and controlled so that the pressure change during contraction does not occur.

【0020】最後に、冷却された半田バンプ3の凝固を
待ってツール4をテープキャリア2から解放し、またチ
ップ部品1を受け側ツール5から吸着解除し、接続が完
了する。
Finally, waiting for the solidification of the cooled solder bumps 3, the tool 4 is released from the tape carrier 2, and the chip component 1 is adsorbed and released from the receiving side tool 5 to complete the connection.

【0021】なお、上述の実施例においては、基板とし
てテープキャリアを用いたものについて説明したが、そ
の他の配線パターンが形成された基板を用いても、同様
の効果が得られることはもちろんである。
In the above embodiment, the tape carrier is used as the substrate, but the same effect can be obtained by using a substrate on which other wiring patterns are formed. .

【0022】[0022]

【効果】上述のように制御がなされることにより、溶融
された半田バンプ出てきた間隙が初期に設定した間隙に
対して変化せず、このため半田バンプが押しつぶされて
隣接するバンプ同士が接触しショートが発生する、とい
う不具合が防止でき、信頼性の高い接続が可能となる
(最近の狭ピッチ間隔での半田バンプはその高さが60
μm程度と低いのに対し、熱膨張により約13μmも狭
くなることは半田バンプがかなり押しつぶされることに
なり、膨らむことでショート発生の原因となる)。ま
た、安定した鼓状の形状が得られるため、強度的にも安
定した接続構造が得られる、という優れた効果を奏す
る。
[Effect] By performing the control as described above, the gap between the melted solder bumps does not change from the initially set gap, so that the solder bumps are crushed and adjacent bumps come into contact with each other. It is possible to prevent a short circuit from occurring and to achieve highly reliable connection (the recent solder bumps with a narrow pitch interval have a height of 60).
Although it is as low as approximately μm, the narrowing of approximately 13 μm due to thermal expansion causes the solder bumps to be considerably crushed and causes swelling, which causes a short circuit. Further, since a stable hourglass-like shape is obtained, an excellent effect that a connection structure that is stable in strength is also obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる実施例である接続方法の工程を
説明するための説明図である。
FIG. 1 is an explanatory diagram for explaining steps of a connection method that is an embodiment according to the present invention.

【図2】テープキャリアをチップ部品の半田バンプに接
触させた状態を示す説明図である。
FIG. 2 is an explanatory diagram showing a state in which a tape carrier is brought into contact with solder bumps of a chip component.

【図3】溶融した半田バンプの形状を鼓状になるように
ツール及び受け側ステージを制御した状態を示す説明図
である。
FIG. 3 is an explanatory diagram showing a state in which a tool and a receiving-side stage are controlled so that the shape of a molten solder bump becomes a drum shape.

【符号の説明】[Explanation of symbols]

1 チップ部品 2 テープキャリア 3 半田バンプ 4 ツール 5 受け側ステージ 1 chip part 2 tape carrier 3 solder bump 4 tool 5 receiving stage

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 チップ部品あるいは基板上の配線パター
ン上に形成された金属バンプを介して前記チップ部品と
基板上の配線パターンとを当接させ、金属バンプを加熱
し溶融させた後に冷却・固化させることによりチップ部
品を基板上に接続するチップ部品の基板上への接続方法
であって、 前記金属バンプを介したチップ部品と前記配線パターン
との当接時に加圧部材にて所定の加圧力を加え、該金属
バンプの高さのばらつきを吸収して前記配線パターンと
の接触を確実に行なわせた後、加熱して前記金属バンプ
を溶融させるとともにこの溶融状態に合わせて前記加圧
部材を制御して加圧力を弱め、さらにその後該加圧部材
の熱膨張による影響を除くために前記チップ部品と基板
との間隙を広げるように制御し、さらにその後加熱を停
止し金属バンプを冷却・固化させる際には冷却時の基板
の収縮による圧力の変動の影響を押さえるように前記チ
ップ部品と基板との間隙を制御することを特徴とするチ
ップ部品の基板上への接続方法。
1. A chip component or a wiring pattern on a substrate is brought into contact with the wiring pattern on the substrate via a metal bump formed on a wiring pattern on the chip component or the substrate, and the metal bump is heated and melted, and then cooled and solidified. A method of connecting a chip component to a substrate by connecting the chip component to the substrate by performing a predetermined pressing force by a pressure member when the chip component and the wiring pattern are brought into contact with each other via the metal bump. After absorbing the variation in height of the metal bumps and making sure contact with the wiring pattern, the metal bumps are heated to melt the metal bumps, and the pressure member is adjusted according to the melted state. The pressure is controlled to weaken the pressure, and then control is performed to widen the gap between the chip component and the substrate in order to eliminate the influence of the thermal expansion of the pressure member, and then the heating is stopped to stop the metal. When cooling and solidifying the bumps, the gap between the chip component and the substrate is controlled so as to suppress the influence of pressure fluctuation due to contraction of the substrate during cooling, and a method of connecting the chip component onto the substrate. .
JP06263088A 1994-10-03 1994-10-03 How to connect chip components to the board Expired - Fee Related JP3095959B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06263088A JP3095959B2 (en) 1994-10-03 1994-10-03 How to connect chip components to the board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06263088A JP3095959B2 (en) 1994-10-03 1994-10-03 How to connect chip components to the board

Publications (2)

Publication Number Publication Date
JPH08107133A true JPH08107133A (en) 1996-04-23
JP3095959B2 JP3095959B2 (en) 2000-10-10

Family

ID=17384668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06263088A Expired - Fee Related JP3095959B2 (en) 1994-10-03 1994-10-03 How to connect chip components to the board

Country Status (1)

Country Link
JP (1) JP3095959B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109786A (en) * 2005-10-12 2007-04-26 Nec Electronics Corp Method and apparatus for manufacturing semiconductor device
JP2007214241A (en) * 2006-02-08 2007-08-23 Sony Corp Method and device for mounting semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109786A (en) * 2005-10-12 2007-04-26 Nec Electronics Corp Method and apparatus for manufacturing semiconductor device
JP4669371B2 (en) * 2005-10-12 2011-04-13 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
JP2007214241A (en) * 2006-02-08 2007-08-23 Sony Corp Method and device for mounting semiconductor chip

Also Published As

Publication number Publication date
JP3095959B2 (en) 2000-10-10

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