CN117352401A - Fan-out chip packaging method and packaging structure - Google Patents
Fan-out chip packaging method and packaging structure Download PDFInfo
- Publication number
- CN117352401A CN117352401A CN202311474688.2A CN202311474688A CN117352401A CN 117352401 A CN117352401 A CN 117352401A CN 202311474688 A CN202311474688 A CN 202311474688A CN 117352401 A CN117352401 A CN 117352401A
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- Prior art keywords
- chip
- adhesive layer
- solder balls
- preset
- substrate
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 26
- 239000012790 adhesive layer Substances 0.000 claims abstract description 110
- 229910000679 solder Inorganic materials 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000002844 melting Methods 0.000 claims abstract description 17
- 230000008018 melting Effects 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 16
- 238000001816 cooling Methods 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims description 14
- 230000001070 adhesive effect Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 238000005476 soldering Methods 0.000 claims description 12
- 230000006835 compression Effects 0.000 claims description 5
- 238000007906 compression Methods 0.000 claims description 5
- 230000008646 thermal stress Effects 0.000 claims description 4
- 229920001567 vinyl ester resin Polymers 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 2
- 239000004593 Epoxy Substances 0.000 claims 1
- 229920000728 polyester Polymers 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 8
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920001225 polyester resin Polymers 0.000 description 3
- 239000004645 polyester resin Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
Abstract
The embodiment of the disclosure provides a fan-out chip packaging method and a packaging structure, wherein the method comprises the following steps: providing a substrate and a chip, wherein the chip is provided with solder balls, and the position of the substrate corresponding to the chip is provided with a preset mounting position; forming an adhesive layer in the edge area of the preset mounting position, wherein the adhesive layer has thermosetting property; mounting the chip at a preset mounting position; heating the chip subjected to mounting to a preset temperature, melting the solder balls and solidifying the adhesive layer, wherein the preset temperature is higher than the melting temperature of the solder balls; and cooling the mounted chip to fix the chip to the substrate through the solder balls and the adhesive layer respectively. Because the bonding adhesive layer has thermosetting property, when the chip is heated to a preset temperature, the solder balls are melted and the bonding adhesive layer is solidified, and the edge area of the chip cannot be stretched by the solidified bonding adhesive layer, so that the chip cannot warp during cooling, the solder balls are well protected from being broken due to stress, the electric property welding points of the solder balls are prevented from being in cold joint or bridging, and the yield of the chip is improved.
Description
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out type chip packaging method and a fan-out type chip packaging structure.
Background
With the development of advanced packaging technology, fan-out chips have become the mainstream of packaging in recent years. As shown in fig. 1, the fan-out chip is flip-chip mounted on the substrate 1, and after the fan-out chip is subjected to solder reflow and natural cooling, the substrate 1 material and the silicon chip 2 are in stress conflict, so that the chip 2 is warped, the solder joint stretching and breakage phenomenon is easy to occur on the edge solder balls 3 of the chip 2, and the solder joint electric property is in cold joint or bridging, so that the chip yield is low.
In view of the above, it is necessary to provide a fan-out chip packaging method and a packaging structure which are reasonable in design and effectively solve the above problems.
In order to solve the above problems, it is necessary to provide a method, a device, an electronic device and a storage medium for recording wind turbine data, which are reasonable in design and effectively solve the above problems.
Disclosure of Invention
The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a fan-out chip packaging method and a packaging structure.
An aspect of an embodiment of the present disclosure provides a fan-out chip packaging method, the method comprising
The method comprises the following steps:
providing a substrate and a chip, wherein one side of the chip facing the substrate is provided with a solder ball, and a preset mounting position is arranged at the position of the substrate corresponding to the chip;
forming an adhesive layer in the edge area of the preset mounting position, wherein the adhesive layer has thermosetting property;
mounting the chip at the preset mounting position;
heating the chip subjected to mounting to a preset temperature, melting the solder balls and solidifying the adhesive layer, wherein the preset temperature is higher than the melting temperature of the solder balls;
and cooling the chip subjected to the mounting, and fixing the chip on the substrate through the solder balls and the adhesive layer respectively.
Optionally, the forming an adhesive layer at the edge area of the preset mounting position includes:
after the adhesive is warmed, the adhesive is put into dispensing equipment;
placing the substrate on an operation platform of the dispensing equipment;
and spraying the adhesive on the edge area of the preset mounting position through the dispensing equipment to form the adhesive layer.
Optionally, the forming an adhesive layer at the edge area of the preset mounting position further includes:
and forming a plurality of point-shaped adhesive layers which are distributed at intervals in the edge area of the preset mounting position.
Optionally, the forming an adhesive layer at the edge area of the preset mounting position further includes:
and forming a strip-shaped adhesive layer in the edge area of the preset mounting position, wherein at least one opening is formed in the strip-shaped adhesive layer.
Optionally, the substrate is provided with a welding area, and the orthographic projection of the adhesive layer on the substrate falls outside the welding area.
Optionally, the material of the adhesive layer includes one of epoxy resin, polyester resin and vinyl ester.
Optionally, the heating the chip after the mounting to a preset temperature to melt the solder balls and solidify the adhesive layer includes:
heating the chip subjected to mounting to a melting temperature by adopting a reflow soldering process, so that the solder balls are melted;
and continuously heating the chip to the preset temperature to solidify the adhesive layer.
Optionally, the heating the chip after the mounting to a preset temperature to melt the solder balls and solidify the adhesive layer further includes:
applying thermal stress to the chip after the mounting by adopting a thermal compression bonding process to melt the solder balls;
and heating the chip to the preset temperature by adopting a reflow soldering process so as to solidify the adhesive layer.
Optionally, the mounting the chip at the preset mounting position includes:
attaching the central region of the chip to the central region of the attaching position through the solder ball;
and mounting the edge area of the chip on the edge area of the mounting position through the adhesive layer.
Another aspect of the disclosed embodiments provides a fan-out chip package structure, which is formed by packaging by the above-described packaging method, and includes a substrate, a chip, an adhesive layer, and solder balls, where the adhesive layer has thermosetting property, and the curing temperature of the adhesive layer is higher than the melting temperature of the solder balls;
the position of the substrate corresponding to the chip is provided with a preset mounting position;
the solder balls are clamped between the chip and the substrate and are positioned at the preset mounting position;
the bonding adhesive layer is arranged in the edge area of the preset mounting position, and the chip is fixed at the preset mounting position through the solder balls and the bonding adhesive layer.
According to the fan-out type chip packaging method and the fan-out type chip packaging structure, in the packaging method, the bonding adhesive layer is formed in the edge area of the preset mounting position of the chip corresponding to the substrate, and because the bonding adhesive layer has thermosetting property, the chip subjected to mounting is heated to the preset temperature, when the solder balls are melted and the bonding adhesive layer is solidified, the edge area of the chip cannot be stretched by the solidified bonding adhesive layer, so that the chip cannot warp during cooling, the solder balls are well protected from being broken due to stress, the electric welding points of the solder balls are prevented from being in cold joint or bridging, and the yield of the chip is improved.
Drawings
FIG. 1 is a schematic diagram of a fan-out chip package in the prior art;
FIG. 2 is a flow diagram of a fan-out chip packaging method according to one embodiment of the present disclosure;
fig. 3 is a schematic diagram of a preset mounting position on a substrate according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a bond line formed according to one embodiment of the present disclosure;
FIG. 5 is a schematic structural view of a bond line formed in accordance with another embodiment of the present disclosure;
FIG. 6 is a top view of a fan-out chip package structure in an embodiment of the present disclosure;
fig. 7 is a cross-sectional view of a fan-out chip package structure in an embodiment of the present disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.
As shown in fig. 2, an aspect of an embodiment of the present disclosure provides a fan-out chip packaging method S100, the method S100 including:
s110, providing a substrate and a chip, wherein a solder ball is arranged on one side of the chip, facing the substrate, and a preset mounting position is arranged at the position of the substrate corresponding to the chip.
As shown in fig. 3 to 7, a substrate 110 and a chip 120 are provided, and a solder ball 130 is provided on a side of the chip 120 facing the substrate 110, and in this embodiment, the solder ball 130 is provided on a functional surface of the chip 120. In the present embodiment, the material of the solder balls 130 is metallic tin, i.e. tin solder balls.
As shown in fig. 3, the substrate 110 has a predetermined mounting position 111 corresponding to the chip 120, that is, the chip 120 needs to be mounted on the substrate 110 at the predetermined mounting position 111.
S120, forming an adhesive layer in the edge area of the preset mounting position, wherein the adhesive layer has thermosetting property.
As shown in fig. 4 and 5, an adhesive layer 140 is formed at an edge region of the preset mounting position 111, wherein the adhesive layer 140 has thermosetting properties. That is, the adhesive layer 140 is cured and formed when heated to its curing temperature.
Specifically, in the present embodiment, the specific steps for forming the adhesive layer 140 are as follows:
firstly, the adhesive is heated to make the adhesive in a flowing state, and then the adhesive is put into the dispensing equipment.
Next, the substrate 110 is placed on an operation platform of the dispensing apparatus.
Finally, adhesive is sprayed on the edge area of the preset mounting position 111 by using the dispensing device, so as to form an adhesive layer 140.
Illustratively, forming the adhesive layer 140 at the edge area of the preset mounting position 111 further includes:
a plurality of spot adhesive layers 140 are formed at intervals at the edge regions of the predetermined mounting positions 111. Specifically, as shown in fig. 4, adhesive is intermittently sprayed along the edge area of the preset mounting position 111 by a dispensing device, so as to form a plurality of point adhesive layers 140 which are distributed at intervals.
Illustratively, forming the adhesive layer 140 at the edge area of the preset mounting position 111 further includes:
a strip-shaped adhesive layer 140 is formed at the edge area of the preset mounting position 111, wherein at least one opening 112 is formed in the strip-shaped adhesive layer 140 for exhausting air during welding. Specifically, as shown in fig. 5, adhesive is continuously sprayed along the edge area of the preset mounting position 111 by a dispensing device to form a strip-shaped adhesive layer 140, wherein at least one opening 112 is formed in the strip-shaped adhesive layer 140.
Illustratively, the substrate 110 is provided with a bonding region for bonding the die 120, and the orthographic projection of the adhesive layer 140 on the substrate 110 falls outside the bonding region. That is, the adhesive layer 140 is distributed on the outer sides of the plurality of pads in the soldering region, and the adhesive cannot be sprayed onto the pads of the substrate 110, so that the electrical connection and signal transmission between the chip 120 and the outside are ensured, and the reliability of the chip 120 is ensured.
Preferably, in the present embodiment, the distance between the adhesive layer 140 and the outermost pad on the substrate 110 is 400 μm-600 μm, and in this range, the adhesive is effectively prevented from contacting the outermost pad on the substrate 110, so as to ensure the reliability of the chip package structure.
It should be noted that the material of the adhesive layer 140 includes one of epoxy resin, polyester resin, and vinyl ester. Other materials are possible as long as the material of the adhesive layer 140 has thermosetting characteristics. Preferably, in the present embodiment, the material of the adhesive layer 140 is epoxy resin, which has excellent physical and mechanical and electrical insulation properties, adhesion properties with various materials, and flexibility of its use process, which are not possessed by other thermosetting plastics.
S130, mounting the chip at the preset mounting position.
As shown in fig. 6, the chip 120 is mounted on the substrate 110 at a predetermined mounting position.
In this embodiment, the chip 120 may be mounted at a predetermined mounting position using a flip chip mounting process. Specifically, the chip 120 is sucked from the wafer by using a chip bonding head, and after soldering flux is adhered to the solder balls 130 on the chip 120, the solder balls are optically aligned and then mounted on a preset mounting position on the substrate 110 to be vacuum-adsorbed.
In this embodiment, the chip 120 may also be mounted on the preset mounting position of the substrate 110 by using a thermal compression mounting process. Specifically, after the soldering area of the substrate 110 is coated with the flux, the soldering area is vacuum-sucked and fixed on a customized heating platform, the chip 120 is sucked up by the chip head and positioned with the aid of the optical camera, and then the chip head moves downward and stops when reaching a preset mounting position of the substrate 110.
Illustratively, mounting the chip 120 at the mounting location, specifically further includes:
the center region of the chip 120 is mounted to the center region of the mounting position by the solder balls 130. Meanwhile, the edge region of the chip 120 is attached to the edge region of the attachment location by the adhesive layer 140.
And S140, heating the chip subjected to the mounting to a preset temperature, melting the solder balls and solidifying the adhesive layer, wherein the preset temperature is higher than the melting temperature of the solder balls.
As shown in fig. 6, the mounted chip 120 is heated to a preset temperature to melt the solder balls 130 and solidify the adhesive layer 140, wherein the preset temperature is the solidification temperature of the adhesive layer 140, that is, the solidification temperature of the adhesive layer 140 is higher than the melting temperature of the solder balls 130, but the soldering effect is good, and the reliability of the chip 120 is increased. If the preset temperature is lower than the melting temperature of the solder balls 130, the adhesive layer 140 is cured during the heating process of the chip 120, resulting in the chip 120 being shifted, causing poor soldering and reducing the reliability of the chip 120.
As shown in fig. 7, the cured adhesive layer 140 supports the bottom wall and the side wall of the edge of the chip 120, and has a good fixing effect on the chip 120.
For example, in one embodiment, the chip 120 after being mounted is heated to a preset temperature, so that the solder balls 130 are melted and the adhesive layer 140 is cured, which may specifically include:
the die 120 after the mounting is heated to a melting temperature by a reflow process to melt the solder balls 130. The chip 120 is continuously heated to a preset temperature to cure the adhesive layer 140.
Specifically, the mounted chip 120 is placed in a reflow oven, the reflow oven is heated to a melting temperature to melt the solder balls 130, the reflow oven is continuously heated to a predetermined temperature, and the adhesive layer 140 begins to cure at the predetermined temperature.
Illustratively, in another embodiment, the chip 120 after being mounted is heated to a preset temperature, so that the solder balls 130 are melted and the adhesive layer 140 is cured, and specifically further includes:
the thermal compression bonding process is used to apply thermal stress to the completed chip 120 and to fuse the solder balls 130. The die 120 is heated to a predetermined temperature using a reflow process to cure the adhesive layer 140.
Specifically, after the chip 120 is mounted by the thermal compression mounting process, a thermal stress is applied to the chip 120, and the chip 120 is rapidly heated until the solder balls 130 are melted, and the chip head moves upwards. The chip 120 is then placed in a reflow oven to continue to reflow the chip 120 to a predetermined temperature, and the bond line 140 is cured at the predetermined temperature.
And S150, cooling the chip subjected to the mounting, and fixing the chip on the substrate through the solder balls and the adhesive layer respectively.
Specifically, after the adhesive layer 140 is cured, the mounted chip 120 is cooled to solidify the melted solder balls 130, so that the chip 120 is fixed on the substrate 110 through the solder balls 130 and the adhesive layer 140, and the package of the chip is completed, so as to form the fan-out chip package structure 100 shown in fig. 6 and 7.
According to the fan-out type chip packaging method, in the packaging method, the adhesive layer is formed in the edge area of the preset mounting position of the chip corresponding to the substrate, and because the adhesive layer has thermosetting property, the chip subjected to mounting is heated to the preset temperature, when the solder balls are melted and the adhesive layer is solidified, the edge area of the chip cannot be stretched by the solidified adhesive layer, so that the chip cannot warp during cooling, the solder balls are well protected from being broken due to the influence of stress, the electric welding points of the solder balls are prevented from being in cold joint or bridging, and the yield of the chip is improved.
As shown in fig. 7, another aspect of the disclosed embodiments provides a fan-out core package structure 100, where the package structure 100 is formed by the package method S100, and specific package steps of the package method S100 are described in detail above. And will not be described in detail herein.
The fan-out chip package structure 100 includes a substrate 110, a chip 120, solder balls 130 and an adhesive layer 140, wherein the adhesive layer 140 has thermosetting property, and the curing temperature of the adhesive layer 140 is higher than the melting temperature of the solder balls 130.
The substrate 110 has a preset mounting position 111 corresponding to the chip 120.
The solder balls 130 are sandwiched between the chip 120 and the substrate 110 and located at the predetermined mounting positions 111.
The adhesive layer 140 is disposed at an edge area of the preset mounting position 111, and the chip 120 is fixed at the preset mounting position 111 through the solder balls 130 and the adhesive layer 140.
According to the fan-out type chip packaging structure, the chip is fixed in the welding area of the substrate through the solder balls, the edge area of the chip is fixed in the edge area of the preset mounting position of the substrate through the adhesive layer, and the edge area of the chip cannot be stretched due to the thermosetting property of the adhesive layer, so that the chip cannot warp, the solder balls are well protected from being broken due to the stress, the electric welding points of the solder balls are prevented from being in cold joint or bridging, and the yield of the chip is improved.
As shown in fig. 4, the adhesive layer 140 is formed in a plurality of points spaced apart along the edge area of the predetermined mounting position.
As shown in fig. 5, the adhesive layer 140 is distributed in a band shape along an edge area of the preset mounting position, wherein the adhesive layer 140 in the band shape is provided with at least one opening 112 for exhausting air during die bonding.
As shown in fig. 7, the cured adhesive layer 140 supports the bottom wall and the side wall of the edge of the chip 120, and has a good fixing effect on the chip 120.
It should be noted that the material of the adhesive layer 140 includes one of epoxy resin, polyester resin, and vinyl ester. Other materials are possible as long as the material of the adhesive layer 140 has thermosetting characteristics. Preferably, in the present embodiment, the material of the adhesive layer 140 is epoxy resin, which has excellent physical and mechanical and electrical insulation properties, adhesion properties with various materials, and flexibility of its use process, which are not possessed by other thermosetting plastics.
It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.
Claims (10)
1. A fan-out chip packaging method, the method comprising:
providing a substrate and a chip, wherein one side of the chip facing the substrate is provided with a solder ball, and a preset mounting position is arranged at the position of the substrate corresponding to the chip;
forming an adhesive layer in the edge area of the preset mounting position, wherein the adhesive layer has thermosetting property;
mounting the chip at the preset mounting position;
heating the chip subjected to mounting to a preset temperature, melting the solder balls and solidifying the adhesive layer, wherein the preset temperature is higher than the melting temperature of the solder balls;
and cooling the chip subjected to the mounting, and fixing the chip on the substrate through the solder balls and the adhesive layer respectively.
2. The method of claim 1, wherein forming an adhesive layer at an edge region of the predetermined mounting location comprises:
after the adhesive is warmed, the adhesive is put into dispensing equipment;
placing the substrate on an operation platform of the dispensing equipment;
and spraying the adhesive on the edge area of the preset mounting position through the dispensing equipment to form the adhesive layer.
3. The method of claim 1, wherein forming an adhesive layer at an edge region of the predetermined mounting location, further comprises:
and forming a plurality of point-shaped adhesive layers which are distributed at intervals in the edge area of the preset mounting position.
4. The method of claim 1, wherein forming an adhesive layer at an edge region of the predetermined mounting location, further comprises:
and forming a strip-shaped adhesive layer in the edge area of the preset mounting position, wherein at least one opening is formed in the strip-shaped adhesive layer.
5. The method according to any one of claims 1 to 4, wherein the substrate is provided with a soldering zone, and the orthographic projection of the adhesive layer on the substrate falls outside the soldering zone.
6. The method of any one of claims 1 to 4, wherein the material of the bond line comprises one of epoxy, polyester, and vinyl ester.
7. The method of any one of claims 1 to 4, wherein heating the die to a predetermined temperature to melt the solder balls and cure the adhesive layer comprises:
heating the chip subjected to mounting to a melting temperature by adopting a reflow soldering process, so that the solder balls are melted;
and continuously heating the chip to the preset temperature to solidify the adhesive layer.
8. The method of any one of claims 1 to 4, wherein the heating the die to a predetermined temperature to melt the solder balls and cure the adhesive layer further comprises:
applying thermal stress to the chip after the mounting by adopting a thermal compression bonding process to melt the solder balls;
and heating the chip to the preset temperature by adopting a reflow soldering process so as to solidify the adhesive layer.
9. The method according to any one of claims 1 to 4, wherein the mounting the chip to the preset mounting position includes:
attaching the central region of the chip to the central region of the attaching position through the solder ball;
and mounting the edge area of the chip on the edge area of the mounting position through the adhesive layer.
10. A fan-out chip package structure, characterized in that the package structure is formed by adopting the package method of any one of claims 1 to 9, the package structure comprises a substrate, a chip, an adhesive layer and solder balls, wherein the adhesive layer has thermosetting property, and the curing temperature of the adhesive layer is higher than the melting temperature of the solder balls;
the position of the substrate corresponding to the chip is provided with a preset mounting position;
the solder balls are clamped between the chip and the substrate and are positioned at the preset mounting position;
the bonding adhesive layer is arranged in the edge area of the preset mounting position, and the chip is fixed at the preset mounting position through the solder balls and the bonding adhesive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311474688.2A CN117352401A (en) | 2023-11-07 | 2023-11-07 | Fan-out chip packaging method and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311474688.2A CN117352401A (en) | 2023-11-07 | 2023-11-07 | Fan-out chip packaging method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117352401A true CN117352401A (en) | 2024-01-05 |
Family
ID=89363136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311474688.2A Pending CN117352401A (en) | 2023-11-07 | 2023-11-07 | Fan-out chip packaging method and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117352401A (en) |
-
2023
- 2023-11-07 CN CN202311474688.2A patent/CN117352401A/en active Pending
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