JP2007214241A - Method and device for mounting semiconductor chip - Google Patents
Method and device for mounting semiconductor chip Download PDFInfo
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- JP2007214241A JP2007214241A JP2006030690A JP2006030690A JP2007214241A JP 2007214241 A JP2007214241 A JP 2007214241A JP 2006030690 A JP2006030690 A JP 2006030690A JP 2006030690 A JP2006030690 A JP 2006030690A JP 2007214241 A JP2007214241 A JP 2007214241A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
Abstract
Description
本発明は半導体チップの実装方法及び半導体チップの実装装置に関する。詳しくは、フリップチップ方式による半導体チップの実装方法及び半導体チップの実装装置に係るものである。 The present invention relates to a semiconductor chip mounting method and a semiconductor chip mounting apparatus. Specifically, the present invention relates to a semiconductor chip mounting method and a semiconductor chip mounting apparatus using a flip chip method.
近年、家庭用ゲーム機やノート型パソコン、携帯型電話機等の各種電化製品の小型化、高性能化に伴い、その内部に使用される半導体パッケージの高密度化が進み、半導体パッケージを高密度に回路基板に実装するための高密度技術も益々進歩している。その１つとして、半導体チップを回路基板に直接フェースダウンで電気的に接続するフリップチップ方式による実装技術がある（例えば、特許文献１参照。）。 In recent years, with the miniaturization and high performance of various electric appliances such as home game machines, notebook computers, and portable telephones, the density of semiconductor packages used therein has increased, and the semiconductor packages have become denser. High density technologies for mounting on circuit boards are also making progress. One of them is a flip-chip mounting technique in which a semiconductor chip is electrically connected directly to a circuit board face down (see, for example, Patent Document 1).
以下、フリップチップ方式によって実装する従来の半導体パッケージの製造方法について図面を用いて説明する。なお、ここでは従来の半導体パッケージの製造方法としてガラスエポキシ基板から成る回路基板に半導体チップを実装する場合を例に挙げるが、半導体チップ同士の組み合わせ、即ち、半導体チップ上に半導体チップを実装することで半導体パッケージを製造しても良い。 Hereinafter, a conventional method for manufacturing a semiconductor package mounted by a flip chip method will be described with reference to the drawings. Here, as an example of a conventional method for manufacturing a semiconductor package, a semiconductor chip is mounted on a circuit board made of a glass epoxy substrate. However, a combination of semiconductor chips, that is, mounting a semiconductor chip on a semiconductor chip. A semiconductor package may be manufactured.
従来のフリップチップ方式による実装では、先ず、図４（ａ）で示す様に、半導体チップ１０１の電極１０２に、はんだを主成分とし、一般的にバンプと称される例えば約１５μｍの高さを有する突起電極１０３（以下、チップ側バンプと称する。）を形成する。
In the conventional flip chip mounting, first, as shown in FIG. 4A, the
また、チップ側バンプの形成とは別に、図４（ｂ）で示す様に、半導体チップを実装する例えばガラスエポキシ基板から成る回路基板１０４の電極１０５に、はんだを主成分とし、約１５μｍの高さを有する突起電極１０６（以下、基板側バンプと称する。）を形成する。
In addition to the formation of the bumps on the chip side, as shown in FIG. 4B, the
次に、図４（ｃ）で示す様に、チップ側バンプが形成された半導体チップを反転して実装ノズル１０７で吸着固定を行い、半導体チップを吸着固定した状態の実装ノズルを回路基板の上方より下降させる。ここで、半導体チップに形成されたチップ側バンプと回路基板に形成された基板側バンプが接触した後も、実装ノズルを下降させる方向に荷重を印加して半導体チップに所定の荷重を印加する。なお、半導体チップに形成されたチップ側バンプと回路基板に形成された基板側バンプが接触し、チップ側バンプと基板側バンプとが突き合わせられた状態では、チップ側バンプ及び基板側バンプが潰れていないと仮定すると、図中符合Ａで示す半導体チップと回路基板との間隙（ギャップ）は約３０μｍである。
Next, as shown in FIG. 4C, the semiconductor chip on which the chip-side bumps are formed is reversed and suction-fixed by the
次に、図４（ｄ）で示す様に、加熱処理を行いながら半導体チップと回路基板とのギャップが例えば約２５μｍとなるまで実装ノズルを下降させ、即ち、チップ側バンプ及び基板側バンプを成すはんだを溶融させた状態で実装ノズルを約５μｍ下降させることによってチップ側バンプと基板側バンプとを一体化し、半導体チップと回路基板を電気的に接続する。 Next, as shown in FIG. 4D, the mounting nozzle is lowered while the heat treatment is performed until the gap between the semiconductor chip and the circuit board becomes, for example, about 25 μm, that is, the chip-side bump and the substrate-side bump are formed. With the solder melted, the mounting nozzle is lowered by about 5 μm to integrate the chip-side bump and the substrate-side bump, thereby electrically connecting the semiconductor chip and the circuit board.
その後、半導体チップと電気的に接続された回路基板間に、例えば注入性の良いエポキシ樹脂を注入し、接続部を封止することによって、図４（ｅ）で示す様な半導体パッケージを得ることができる。 Thereafter, for example, an epoxy resin with good injectability is injected between the circuit boards electrically connected to the semiconductor chip, and the connection portion is sealed to obtain a semiconductor package as shown in FIG. Can do.
ここで、上記した従来の半導体パッケージの製造方法では、チップ側バンプと基板側バンプとを一体化する際に、チップ側バンプ及び基板側バンプを成すはんだが溶融するのに充分な温度に達する熱量を与え、その後、凝固するまでに一定の時間放置し、若しくは強制的に冷却してはんだを凝固させる必要がある。 Here, in the above-described conventional semiconductor package manufacturing method, when the chip-side bump and the substrate-side bump are integrated, the amount of heat reaching a temperature sufficient to melt the solder that forms the chip-side bump and the substrate-side bump. After that, the solder must be solidified by allowing it to stand for a certain time until it solidifies or forcibly cooling it.
即ち、加熱処理によるチップ側バンプ及び基板側バンプを溶融させ、チップ側バンプと基板側バンプを一体化した後に冷却処理による凝固を行なうといった一連の流れを経ることによってチップ側バンプと基板側バンプの溶融接続が成立するのである。 In other words, the chip-side bump and the substrate-side bump are melted by the heat treatment, and the chip-side bump and the substrate-side bump are subjected to a series of processes such as solidification by cooling after the chip-side bump and the substrate-side bump are integrated. A melt connection is established.
しかしながら、チップ側バンプ及び基板側バンプを溶融するために必要となる「加熱処理」を行なった場合には実装ノズルが膨張し、溶融して一体化したチップ側バンプ及び基板側バンプを凝固させるために必要となる「冷却処理」を行なった場合には実装ノズルが収縮するといった熱変化が生じ、半導体チップと回路基板とのギャップを高精度に制御することが困難であった。以下、この点について説明する。 However, when the “heating process” necessary for melting the chip-side bump and the substrate-side bump is performed, the mounting nozzle expands to melt and fuse the integrated chip-side bump and substrate-side bump. When the “cooling process” required for the heat treatment is performed, a thermal change occurs such that the mounting nozzle contracts, and it is difficult to control the gap between the semiconductor chip and the circuit board with high accuracy. Hereinafter, this point will be described.
先ず、加熱処理によって実装ノズルが膨張しないと仮定すると、チップ側バンプと基板側バンプを突き合わせた状態の半導体チップと回路基板とのギャップと、半導体チップの実装後に求める半導体チップと回路基板とのギャップとの差分（上記した従来の半導体パッケージの製造方法の例の場合には、チップ側バンプと基板側バンプと突き合わせた状態の半導体チップと回路基板とのギャップである３０μｍと、半導体チップの実装後に求める半導体チップと回路基板とのギャップである２５μｍとの差分である５μｍ）だけ実装ノズルを下降させることによって、半導体チップと回路基板とのギャップが所望の値になると考えられる。
しかし、現実的には加熱処理により実装ノズルが膨張するために、実装ノズルを一切移動させなかったとしても、実装ノズルの膨張量だけ半導体チップと回路基板とのギャップが小さくなってしまい、チップ側バンプと基板側バンプを突き合わせた状態の半導体チップと回路基板とのギャップと、半導体チップの実装後に求める半導体チップと回路基板とのギャップとの差分だけ実装ノズルを下降させた場合には、必要以上に実装ノズルを下降させることとなり、結果として半導体チップと回路基板とのギャップが所望の値よりも小さな値となってしまう。
First, assuming that the mounting nozzle does not expand due to the heat treatment, the gap between the semiconductor chip and the circuit board in a state where the chip-side bump and the substrate-side bump are abutted, and the gap between the semiconductor chip and the circuit board obtained after mounting the semiconductor chip (In the case of the above-described conventional method of manufacturing a semiconductor package, the gap between the semiconductor chip and the circuit board in a state of being in contact with the chip-side bump and the substrate-side bump is 30 μm, and after the semiconductor chip is mounted) It is considered that the gap between the semiconductor chip and the circuit board becomes a desired value by lowering the mounting nozzle by 5 μm which is a difference between 25 μm which is the gap between the desired semiconductor chip and the circuit board.
However, because the mounting nozzle actually expands due to the heat treatment, even if the mounting nozzle is not moved at all, the gap between the semiconductor chip and the circuit board is reduced by the expansion amount of the mounting nozzle, and the chip side If the mounting nozzle is lowered by the difference between the gap between the semiconductor chip and the circuit board with the bumps and the board-side bumps butted and the gap between the semiconductor chip and the circuit board obtained after mounting the semiconductor chip, it is more than necessary. As a result, the gap between the semiconductor chip and the circuit board becomes smaller than a desired value.
また、冷却処理によって実装ノズルが膨張しないと仮定すると、冷却処理の前後で半導体チップと回路基板とのギャップに変動が生じないと考えられるために、冷却処理前（バンプの凝固前）に半導体チップと回路基板とのギャップが所望の値になっている場合には、実装ノズルを移動させることなくそのままの状態で冷却処理を行なうことで、冷却処理後（バンプの凝固後）において半導体チップと回路基板とのギャップが所望の値になると考えられる。
しかし、現実的には冷却処理により実装ノズルが収縮するために、実装ノズルを一切移動させなかったとしても、実装ノズルの収縮量だけ半導体チップと回路基板とのギャップが大きくなってしまい、結果として冷却処理後（バンプの凝固後）において半導体チップと回路基板とのギャップが所望の値よりも大きな値となってしまう。
Also, if it is assumed that the mounting nozzle does not expand due to the cooling process, it is considered that the gap between the semiconductor chip and the circuit board does not change before and after the cooling process, so the semiconductor chip before the cooling process (before the bumps are solidified). When the gap between the semiconductor chip and the circuit board is a desired value, the cooling process is performed without moving the mounting nozzle, so that the semiconductor chip and the circuit are formed after the cooling process (after the solidification of the bumps). It is considered that the gap with the substrate becomes a desired value.
However, because the mounting nozzle actually contracts due to the cooling process, even if the mounting nozzle is not moved at all, the gap between the semiconductor chip and the circuit board increases by the amount of contraction of the mounting nozzle. After the cooling process (after the solidification of the bumps), the gap between the semiconductor chip and the circuit board becomes a value larger than a desired value.
従って、上記した従来の半導体パッケージの製造方法の様に、加熱処理時には実装ノズルを５μｍだけ下降させ、冷却処理時には実装ノズルは移動させないといった方式だと、加熱処理によって実装ノズルが膨張し、冷却処理により実装ノズルが収縮することに起因して半導体チップと回路基板とのギャップを高精度に制御できないこととなる。 Therefore, as in the conventional semiconductor package manufacturing method described above, when the mounting nozzle is lowered by 5 μm during the heat treatment and the mounting nozzle is not moved during the cooling processing, the mounting nozzle expands due to the heat treatment, and the cooling processing is performed. Due to the shrinkage of the mounting nozzle, the gap between the semiconductor chip and the circuit board cannot be controlled with high accuracy.
本発明は以上の点に鑑みて創案されたものであって、半導体チップと回路基板とのギャップを高精度に制御することができる半導体チップの実装方法及び半導体チップの実装装置を提供することを目的とするものである。 The present invention has been made in view of the above points, and provides a semiconductor chip mounting method and a semiconductor chip mounting apparatus capable of controlling the gap between the semiconductor chip and the circuit board with high accuracy. It is the purpose.
上記の目的を達成するために、本発明に係る半導体チップの実装方法は、第１の突起電極が形成された基板上に第２の突起電極が形成された半導体チップを、前記第１の突起電極と前記第２の突起電極とを接触させて配置する工程と、前記第１の突起電極及び前記第２の突起電極に加熱処理を施し、前記第１の突起電極及び前記第２の突起電極を一体化する工程と、一体化した前記第１の突起電極及び前記第２の突起電極に冷却処理を施す工程とを備える半導体チップの実装方法において、前記加熱処理時または前記加熱処理前に前記基板と前記半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させる工程、若しくは、前記冷却処理時に前記基板と前記半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる工程を備える。 In order to achieve the above object, a semiconductor chip mounting method according to the present invention includes a semiconductor chip on which a second protruding electrode is formed on a substrate on which a first protruding electrode is formed. A step of placing the electrode and the second protruding electrode in contact with each other; heat-treating the first protruding electrode and the second protruding electrode; and the first protruding electrode and the second protruding electrode And a step of performing a cooling process on the integrated first protruding electrode and the second protruding electrode, in the semiconductor chip mounting method, in the heat treatment or before the heat treatment, A step of moving the pressing jig in a direction in which the gap between the substrate and the semiconductor chip is increased, or a step of moving the pressing jig in a direction in which the gap between the substrate and the semiconductor chip is reduced during the cooling process. The Obtain.
ここで、加熱処理時または加熱処理前に基板と半導体チップとの間隙が大きくなる方向に押圧治具を移動させることによって、加熱処理により基板と半導体チップとの間隙が小さくなってしまう現象を抑制することができる。
詳しくは、加熱処理を施すことで押圧治具は膨張するために、加熱処理前（膨張前）は基板と半導体チップとの間隙が所望の距離（以下、「設定距離」と称する）であったとしても、加熱処理に起因して基板と半導体チップとの間隙が設定距離よりも小さくなってしまうと考えられるのであるが、加熱処理時または加熱処理前に基板と半導体チップとの間隙が大きくなる方向に押圧治具を移動することによって、即ち、加熱処理による膨張量を考慮した上で、押圧治具の膨張後における基板と半導体チップとの間隙が設定距離となる様に押圧治具を移動することによって、加熱処理を施すことで押圧治具が膨張したとしても基板と半導体チップとの間隙を概ね設定距離に保つことができるのである。
Here, the phenomenon that the gap between the substrate and the semiconductor chip is reduced by the heat treatment is suppressed by moving the pressing jig in the direction in which the gap between the substrate and the semiconductor chip is enlarged during or before the heat treatment. can do.
Specifically, since the pressing jig expands when heat treatment is performed, the gap between the substrate and the semiconductor chip is a desired distance (hereinafter referred to as “set distance”) before the heat treatment (before expansion). However, it is considered that the gap between the substrate and the semiconductor chip becomes smaller than the set distance due to the heat treatment, but the gap between the substrate and the semiconductor chip becomes large during or before the heat treatment. By moving the pressing jig in the direction, that is, taking into account the amount of expansion due to heat treatment, the pressing jig is moved so that the gap between the substrate and the semiconductor chip after the expansion of the pressing jig is a set distance. By doing so, even if the pressing jig expands due to the heat treatment, the gap between the substrate and the semiconductor chip can be maintained at a set distance.
また、冷却処理時に基板と半導体チップとの間隙が小さくなる方向に押圧治具を移動させることによって、冷却処理により基板と半導体チップとの間隙が大きくなってしまう現象を抑制することができる。
詳しくは、冷却処理を施すことで押圧治具は収縮するために、冷却処理前（収縮前）は基板と半導体チップとの間隙が設定距離であったとしても、冷却処理に起因して基板と半導体チップとの間隙が設定距離よりも大きくなってしまうと考えられるのであるが、冷却処理時に基板と半導体チップとの間隙が小さくなる方向に押圧治具を移動することによって、即ち、冷却処理による収縮量を考慮した上で、押圧治具の収縮後における基板と半導体チップとの間隙が設定距離となる様に押圧治具を移動することによって、冷却処理を施すことで押圧治具が収縮したとしても基板と半導体チップとの間隙を概ね設定距離に保つことができるのである。
Further, by moving the pressing jig in a direction in which the gap between the substrate and the semiconductor chip is reduced during the cooling process, a phenomenon in which the gap between the substrate and the semiconductor chip is increased due to the cooling process can be suppressed.
Specifically, since the pressing jig contracts when the cooling process is performed, even if the gap between the substrate and the semiconductor chip is a set distance before the cooling process (before the contraction), It is considered that the gap between the semiconductor chip and the semiconductor chip becomes larger than the set distance, but by moving the pressing jig in the direction in which the gap between the substrate and the semiconductor chip is reduced during the cooling process, that is, due to the cooling process. Considering the amount of shrinkage, the pressing jig shrunk by applying a cooling process by moving the pressing jig so that the gap between the substrate and the semiconductor chip after shrinkage of the pressing jig is a set distance. However, the gap between the substrate and the semiconductor chip can be kept at a set distance.
また、本発明に係る半導体チップの実装方法は、第１の突起電極が形成された第１の半導体チップ上に第２の突起電極が形成された第２の半導体チップを、前記第１の突起電極と前記第２の突起電極とを接触させて配置する工程と、前記第１の突起電極及び前記第２の突起電極に加熱処理を施し、押圧治具により前記第２の半導体チップに荷重を印加して、前記第１の突起電極及び前記第２の突起電極を一体化する工程と、一体化した前記第１の突起電極及び前記第２の突起電極に冷却処理を施す工程とを備える半導体チップの実装方法において、前記加熱処理時または前記加熱処理前に前記第１の半導体チップと前記第２の半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させる工程、若しくは、前記冷却処理時に前記第１の半導体チップと前記第２の半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる工程を備える。 According to another aspect of the present invention, there is provided a method for mounting a semiconductor chip comprising: a second semiconductor chip having a second protruding electrode formed on a first semiconductor chip having a first protruding electrode; A step of placing the electrode and the second protruding electrode in contact with each other, heat-treating the first protruding electrode and the second protruding electrode, and applying a load to the second semiconductor chip by a pressing jig A semiconductor comprising: applying and integrating the first protruding electrode and the second protruding electrode; and subjecting the integrated first protruding electrode and second protruding electrode to a cooling process In the chip mounting method, the step of moving the pressing jig in a direction in which a gap between the first semiconductor chip and the second semiconductor chip is increased during the heat treatment or before the heat treatment, or the cooling Said first during processing Comprising a step of moving the pressing tool in a direction gap between the conductor chip and the second semiconductor chip is reduced.
ここで、加熱処理時または加熱処理前に第１の半導体チップと第２の半導体チップとの間隙が大きくなる方向に押圧治具を移動させることによって、加熱処理により第１の半導体チップと第２の半導体チップとの間隙が小さくなってしまう現象を抑制することができる。
また、冷却処理時に第１の半導体チップと第２の半導体チップとの間隙が小さくなる方向に押圧治具を移動させることによって、冷却処理により第１の半導体チップと第２の半導体チップとの間隙が大きくなってしまう現象を抑制することができる。
Here, by moving the pressing jig in the direction in which the gap between the first semiconductor chip and the second semiconductor chip is increased during the heat treatment or before the heat treatment, the first semiconductor chip and the second semiconductor chip are subjected to the heat treatment. The phenomenon that the gap with the semiconductor chip becomes small can be suppressed.
Further, by moving the pressing jig in a direction in which the gap between the first semiconductor chip and the second semiconductor chip is reduced during the cooling process, the gap between the first semiconductor chip and the second semiconductor chip is obtained by the cooling process. Can be suppressed.
また、上記の目的を達成するために、本発明に係る半導体チップの実装装置は、第１の突起電極が形成された基板上に第２の突起電極が形成された半導体チップを、前記第１の突起電極と前記第２の突起電極とを接触させて配置して前記第１の突起電極及び前記第２の突起電極に加熱処理を施し、前記第１の突起電極及び前記第２の突起電極を一体化した後に、一体化した前記第１の突起電極及び前記第２の突起電極に冷却処理を施す半導体チップの実装装置において、前記加熱処理時または前記加熱処理前に前記基板と前記半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させると共に、前記冷却処理時に前記基板と前記半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる押圧治具制御手段を備える。 In order to achieve the above object, a semiconductor chip mounting apparatus according to the present invention includes a semiconductor chip having a second protruding electrode formed on a substrate on which a first protruding electrode is formed. The protruding electrode and the second protruding electrode are placed in contact with each other, and the first protruding electrode and the second protruding electrode are subjected to heat treatment, and the first protruding electrode and the second protruding electrode In the semiconductor chip mounting apparatus that performs a cooling process on the integrated first protruding electrode and the second protruding electrode after integrating the substrate and the semiconductor chip during or before the heat treatment And a pressing jig control means for moving the pressing jig in a direction in which the gap between the substrate and the semiconductor chip is reduced during the cooling process.
ここで、加熱処理時または加熱処理前に基板と半導体チップとの間隙が大きくなる方向に押圧治具を移動させると共に、冷却処理時に基板と半導体チップとの間隙が小さくなる方向に押圧治具を移動させる押圧治具制御手段によって、加熱処理により基板と半導体チップとの間隙が小さくなってしまう現象を抑制することができると共に、冷却処理により基板と半導体チップとの間隙が大きくなってしまう現象を抑制することができる。 Here, during the heat treatment or before the heat treatment, the pressing jig is moved in a direction in which the gap between the substrate and the semiconductor chip is increased, and the pressing jig is moved in a direction in which the gap between the substrate and the semiconductor chip is reduced during the cooling process. By the pressing jig control means to be moved, the phenomenon that the gap between the substrate and the semiconductor chip is reduced by the heat treatment can be suppressed, and the phenomenon that the gap between the substrate and the semiconductor chip is enlarged by the cooling treatment. Can be suppressed.
また、本発明に係る半導体チップの実装装置は、第１の突起電極が形成された第１の半導体チップ上に第２の突起電極が形成された第２の半導体チップを、前記第１の突起電極と前記第２の突起電極とを接触させて配置して前記第１の突起電極及び前記第２の突起電極に加熱処理を施し、押圧治具により前記第２の半導体チップに荷重を印加して前記第１の突起電極及び前記第２の突起電極を一体化した後に、一体化した前記第１の突起電極及び前記第２の突起電極に冷却処理を施す半導体チップの実装装置において、前記加熱処理時または前記加熱処理前に前記第１の半導体チップと前記第２の半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させると共に、前記冷却処理時に前記第１の半導体チップと前記第２の半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる押圧治具制御手段を備える。 According to another aspect of the present invention, there is provided a semiconductor chip mounting apparatus comprising: a second semiconductor chip having a second protruding electrode formed on a first semiconductor chip having a first protruding electrode; An electrode is placed in contact with the second protruding electrode, the first protruding electrode and the second protruding electrode are heated, and a load is applied to the second semiconductor chip by a pressing jig. In the semiconductor chip mounting apparatus, after the first protruding electrode and the second protruding electrode are integrated, the integrated first protruding electrode and second protruding electrode are cooled. The pressing jig is moved in the direction in which the gap between the first semiconductor chip and the second semiconductor chip is increased during the processing or before the heat treatment, and the first semiconductor chip and the Second semiconductor chip Comprising a pressing jig control means for moving the pressing jig in a direction in which the gap decreases with.
ここで、加熱処理時または加熱処理前に第１の半導体チップと第２の半導体チップとの間隙が大きくなる方向に押圧治具を移動させると共に、冷却処理時に第１の半導体チップと第２の半導体チップとの間隙が小さくなる方向に押圧治具を移動させる押圧治具制御手段によって、加熱処理により第１の半導体チップと第２の半導体チップとの間隙が小さくなってしまう現象を抑制することができると共に、冷却処理により第１の半導体チップと第２の半導体チップとの間隙が大きくなってしまう現象を抑制することができる。 Here, during the heat treatment or before the heat treatment, the pressing jig is moved in a direction in which the gap between the first semiconductor chip and the second semiconductor chip is increased, and at the time of the cooling treatment, the first semiconductor chip and the second semiconductor chip are moved. Suppressing the phenomenon that the gap between the first semiconductor chip and the second semiconductor chip is reduced by the heat treatment by the pressing jig control means that moves the pressing jig in the direction in which the gap with the semiconductor chip is reduced. In addition, the phenomenon in which the gap between the first semiconductor chip and the second semiconductor chip becomes large due to the cooling process can be suppressed.
上記した本発明の半導体チップの実装方法及び半導体チップの実装装置では、加熱処理により基板と半導体チップとの間隙が小さくなってしまう現象を抑制することができると共に、冷却処理により基板と半導体チップとの間隙が大きくなってしまう現象を抑制することができるために、基板と半導体チップとの間隙（ギャップ）を高精度に制御することが可能となる。 In the semiconductor chip mounting method and the semiconductor chip mounting apparatus of the present invention described above, the phenomenon that the gap between the substrate and the semiconductor chip is reduced by the heat treatment can be suppressed, and the substrate and the semiconductor chip are cooled by the cooling treatment. As a result, it is possible to control the gap between the substrate and the semiconductor chip with high accuracy.
以下、本発明の実施の形態について図面を参照しながら説明し、本発明の理解に供する。
なお、以下では回路基板と半導体チップとのギャップが例えば２５μｍとなる様に半導体チップを回路基板に実装する場合を例に挙げて説明を行う。また、以下ではガラスエポキシ基板から成る回路基板に半導体チップを実装する場合を例に挙げるが、半導体チップ同士の組み合わせ、即ち、半導体チップ上に半導体チップを実装することで半導体パッケージを製造しても良い。
Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
In the following description, a case where the semiconductor chip is mounted on the circuit board so that the gap between the circuit board and the semiconductor chip is, for example, 25 μm will be described. Moreover, although the case where a semiconductor chip is mounted on the circuit board which consists of a glass epoxy board | substrate is mentioned as an example below, even if a semiconductor package is manufactured by mounting a semiconductor chip on the combination of semiconductor chips, ie, a semiconductor chip. good.
図１は半導体チップを回路基板に実装する際の押圧治具である実装ノズルの位置及び温度、並びに半導体チップに印加される荷重値の時間的変化を示したグラフの一例である。 FIG. 1 is an example of a graph showing a temporal change in the position and temperature of a mounting nozzle, which is a pressing jig when a semiconductor chip is mounted on a circuit board, and a load value applied to the semiconductor chip.
本発明を適用した半導体チップの実装方法の一例では、上記した従来の半導体チップの実装方法と同様に、先ず、半導体チップの電極に、はんだを主成分とする約１５μｍの高さを有するチップ側バンプを形成すると共に（図４（ａ）参照。）、半導体チップを実装するガラスエポキシ基板から成る回路基板の電極に、はんだを主成分とする例えば約１５μｍの高さを有する基板側バンプを形成する（図４（ｂ）参照。）。 In an example of a semiconductor chip mounting method to which the present invention is applied, as in the conventional semiconductor chip mounting method described above, first, a chip side having a height of about 15 μm mainly composed of solder is formed on the electrodes of the semiconductor chip. A bump is formed (see FIG. 4A), and a substrate-side bump having a height of, for example, about 15 μm mainly composed of solder is formed on an electrode of a circuit board made of a glass epoxy substrate on which a semiconductor chip is mounted. (See FIG. 4B.)
次に、チップ側バンプが形成された半導体チップを反転して実装ノズルで吸着固定を行い、半導体チップを吸着固定した状態の実装ノズルを回路基板の上方より下降させる（図４（ｃ）参照。）。なお、実装ノズルを回路基板の上方より下降させる動作は図１中符合ａで示す期間である。 Next, the semiconductor chip on which the chip-side bumps are formed is inverted and suction-fixed by the mounting nozzle, and the mounting nozzle in a state where the semiconductor chip is suction-fixed is lowered from above the circuit board (see FIG. 4C). ). Note that the operation of lowering the mounting nozzle from above the circuit board is the period indicated by the symbol a in FIG.
ところで、半導体チップに形成されたチップ側バンプと回路基板に形成された基板側バンプが接触した後も実装ノズルの下降動作を停止させずに、実装ノズルにより半導体チップに印加される荷重値が設定値に達した際に実装ノズルの下降を停止する。また、実装ノズルの下降動作の停止と共に、実装ノズルの温度を上昇させて半導体チップの加熱処理を開始する。なお、半導体チップの加熱処理は図１中符合ｂで示す期間である。 By the way, the load value applied to the semiconductor chip by the mounting nozzle is set without stopping the lowering operation of the mounting nozzle even after the chip-side bump formed on the semiconductor chip contacts the substrate-side bump formed on the circuit board. When the value is reached, the descent of the mounting nozzle is stopped. In addition, when the lowering operation of the mounting nozzle is stopped, the temperature of the mounting nozzle is increased to start the heat treatment of the semiconductor chip. Note that the heat treatment of the semiconductor chip is a period indicated by a symbol b in FIG.
次に、半導体チップの加熱処理によってバンプ（チップ側バンプ及び基板側バンプ）が溶融し、半導体チップに印加される荷重値が０となった後に、時間の経過に伴って徐々に実装ノズルを上昇させる。即ち、回路基板と半導体チップとのギャップが２５μｍとなる様に、時間の経過に伴って徐々に実装ノズルを上昇させる。ここで、実装ノズルの動作制御（上昇動作及び下降動作の制御）については、実装ノズル制御手段で行なっているのであるが、実装ノズル制御手段での動作制御については、予めメモリされた通りに制御を行なっても良いし、例えばレーザ変位計等を用いて回路基板と半導体チップとのギャップを計測し、こうした計測結果に基づいて制御を行なっても良い。なお、回路基板と半導体チップとのギャップが２５μｍとなる様に、実装ノズルを上昇させているのは、図１中符合ｃで示す期間である。
尚、バンプの接続信頼性を確保するために、実装ノズルの上昇動作は、加熱処理による実装ノズルの膨張スピードよりも確実に遅いスピードで行なうことが好ましい。
以下、ギャップを２５μｍにすべく実装ノズルを上昇させる必要性について詳細に説明を行う。
Next, after the bumps (chip-side bump and substrate-side bump) are melted by the heat treatment of the semiconductor chip and the load value applied to the semiconductor chip becomes 0, the mounting nozzle is gradually raised as time passes. Let That is, the mounting nozzle is gradually raised as time passes so that the gap between the circuit board and the semiconductor chip becomes 25 μm. Here, the operation control of the mounting nozzle (control of the ascending operation and the descending operation) is performed by the mounting nozzle control means, but the operation control by the mounting nozzle control means is controlled as previously stored. For example, the gap between the circuit board and the semiconductor chip may be measured using a laser displacement meter or the like, and control may be performed based on the measurement result. Note that the mounting nozzle is raised so that the gap between the circuit board and the semiconductor chip is 25 μm during a period indicated by a symbol c in FIG.
In order to ensure the connection reliability of the bumps, it is preferable that the ascending operation of the mounting nozzle is performed at a speed that is surely slower than the expansion speed of the mounting nozzle by heat treatment.
Hereinafter, the necessity of raising the mounting nozzle to make the gap 25 μm will be described in detail.
先ず、約１５μｍの高さを有するチップ側バンプと約１５μｍの高さを有する基板側バンプとを突き合わせた状態（バンプの溶融前の状態）では、回路基板と半導体チップとのギャップは約３０μｍであり、バンプを一体化した後に回路基板と半導体チップとのギャップを２５μｍとするためには、半導体チップを回路基板側に５μｍだけ近づける必要がある。即ち、加熱処理によって実装ノズルが膨張しないと仮定した場合には、実装ノズルを５μｍだけ下降させれば良いということになる。
しかし、実際には加熱処理によって実装ノズルが膨張し、実装ノズルの膨張量は実装ノズルを下降させたものと実質的に同一視できるために、加熱処理によって実装ノズルが膨張しないと仮定した場合と同様に実装ノズルを下降させたのでは、回路基板と半導体チップとのギャップは２５μｍよりも小さくなってしまう。
そこで、（１）（加熱処理によって実装ノズルが膨張しないと仮定した場合と同様に）実装ノズルを５μｍ下降させるという制御を行ないつつ、（２）加熱処理による実装ノズルの膨張量を相殺すべく膨張量だけ実装ノズルを上昇させるという制御を行なうことによって、加熱処理により実装ノズルが膨張したとしても、回路基板と半導体チップとの間隙を２５μｍとすることができるのである。
なお、図１中符合Ｚ１は、加熱処理による実装ノズルの膨張を考慮した上で、半導体チップを回路基板側に５μｍだけ近づけるための実装ノズルの移動距離（上昇距離）である。例えば、加熱処理により実装ノズルが半導体チップを回路基板に近づける方向に１０μｍだけ膨張するとした場合には、実装ノズルを５μｍだけ上昇することで（Ｚ１＝５μｍとすることで）、結果的に半導体チップを回路基板側に５μｍだけ近づけることができる。
First, in a state where a chip side bump having a height of about 15 μm and a substrate side bump having a height of about 15 μm are abutted (before the bump is melted), the gap between the circuit board and the semiconductor chip is about 30 μm. In order to make the gap between the circuit board and the semiconductor chip 25 μm after the bumps are integrated, it is necessary to bring the semiconductor chip closer to the circuit board by 5 μm. That is, when it is assumed that the mounting nozzle does not expand due to the heat treatment, the mounting nozzle may be lowered by 5 μm.
However, in actuality, the mounting nozzle expands due to the heat treatment, and the amount of expansion of the mounting nozzle can be substantially the same as that when the mounting nozzle is lowered. Similarly, when the mounting nozzle is lowered, the gap between the circuit board and the semiconductor chip becomes smaller than 25 μm.
Therefore, (1) while controlling the lowering of the mounting nozzle by 5 μm (similar to the assumption that the mounting nozzle does not expand due to heat treatment), (2) expansion to offset the expansion amount of the mounting nozzle by heat treatment By performing control to raise the mounting nozzle by an amount, even if the mounting nozzle expands due to the heat treatment, the gap between the circuit board and the semiconductor chip can be set to 25 μm.
In FIG. 1, reference numeral Z <b> 1 is a mounting nozzle moving distance (rising distance) for bringing the semiconductor chip closer to the circuit board side by 5 μm in consideration of the expansion of the mounting nozzle due to heat treatment. For example, when the mounting nozzle expands by 10 μm in the direction to bring the semiconductor chip closer to the circuit board by heat treatment, the mounting nozzle is raised by 5 μm (by setting Z1 = 5 μm), and as a result, the semiconductor chip Can be brought closer to the circuit board side by 5 μm.
続いて、回路基板と半導体チップとの間隙を２５μｍに保ちながら、一体化したバンプを凝固させるべく、時間の経過に伴って実装ノズルを下降させながら冷却処理を行なう。なお、冷却期間は図１中符合ｄで示す期間である。 Subsequently, in order to solidify the integrated bump while keeping the gap between the circuit board and the semiconductor chip at 25 μm, a cooling process is performed while lowering the mounting nozzle as time passes. The cooling period is a period indicated by a symbol d in FIG.
ここで、加熱処理の段階で回路基板と半導体チップとのギャップは２５μｍに保たれているとすると、そのままの状態（回路基板と半導体チップとのギャップが２５μｍの状態）で一体化したバンプを凝固させれば良いことになる。即ち、冷却処理によって実装ノズルが収縮しないと仮定した場合には、実装ノズルを移動させる必要はないということになる。
しかし、実際には冷却処理によって実装ノズルが収縮し、実装ノズルの収縮量は実装ノズルを上昇させたものと実質的に同一視できるために、冷却処理によって実装ノズルが収縮しないと仮定した場合と同様に実装ノズルを移動させなかったのでは、回路基板と半導体チップとのギャップが２５μｍよりも大きくなってしまう。
そこで、（１）（冷却処理によって実装ノズルが収縮しないと仮定した場合と同様に）実装ノズルの移動を行なわないという制御を行いつつ、（２）冷却処理による実装ノズルの収縮量を相殺すべく収縮量だけ実装ノズルを下降させるという制御を行なうことによって、冷却処理により実装ノズルが収縮したとしても、回路基板と半導体チップとの間隙を２５μｍとすることができるのである。
なお、図１中符合Ｚ２は、冷却処理による実装ノズルの収縮を考慮した上で、回路基板と半導体チップとのギャップに変更を加えないための実装ノズルの移動距離（下降距離）である。即ち、冷却処理による実装ノズルの収縮を相殺するために必要な実装ノズルの移動距離（下降距離）である。例えば、冷却処理により実装ノズルが半導体チップを回路基板から遠ざける方向に１０μｍだけ収縮するとした場合には、実装ノズルを１０μｍだけ下降させることで（Ｚ２＝１０μｍとすることで）、冷却処理による実装ノズルの収縮を相殺することができる。
Here, assuming that the gap between the circuit board and the semiconductor chip is kept at 25 μm at the stage of the heat treatment, the integrated bump is solidified as it is (the gap between the circuit board and the semiconductor chip is 25 μm). If you let it. That is, when it is assumed that the mounting nozzle does not contract due to the cooling process, it is not necessary to move the mounting nozzle.
However, in actuality, the mounting nozzle contracts due to the cooling process, and the amount of contraction of the mounting nozzle can be substantially the same as that when the mounting nozzle is raised, so it is assumed that the mounting nozzle does not contract due to the cooling process. Similarly, if the mounting nozzle is not moved, the gap between the circuit board and the semiconductor chip becomes larger than 25 μm.
Therefore, (1) while controlling the mounting nozzle not to be moved (as in the case where the mounting nozzle does not contract due to the cooling process), (2) to cancel the contraction amount of the mounting nozzle due to the cooling process. By performing the control of lowering the mounting nozzle by the contraction amount, the gap between the circuit board and the semiconductor chip can be set to 25 μm even if the mounting nozzle is contracted by the cooling process.
In FIG. 1, reference symbol Z <b> 2 is a movement distance (downward distance) of the mounting nozzle so as not to change the gap between the circuit board and the semiconductor chip in consideration of the shrinkage of the mounting nozzle due to the cooling process. That is, it is the movement distance (downward distance) of the mounting nozzle that is necessary to cancel out the shrinkage of the mounting nozzle due to the cooling process. For example, if the mounting nozzle shrinks by 10 μm in the direction away from the circuit board by the cooling process, the mounting nozzle is lowered by 10 μm (by setting Z2 = 10 μm), and the mounting nozzle by the cooling process Can cancel out the shrinkage.
上記した様に、冷却処理による実装ノズルの収縮が回路基板と半導体チップとのギャップである２５μｍを変動させないように、時間の経過に伴って徐々に実装ノズルを下降させるのであるが、バンプが凝固しているときに瞬間的に実装ノズルの収縮が生じることも充分に考えられる。
このような場合には実装ノズルを下降させる動作が実装ノズルの瞬間的な収縮動作に追随できずに、結果的にバンプにストレスを与えることとなり、図２（ａ）や図２（ｂ）で示す様に、電極（半導体チップの電極１０ａ、回路基板の電極１０ｂ）とバンプ２０との接続部にクラックが生じたり、電極とバンプとの接続部から引きちぎれが生じたりする原因となり、接続信頼性が著しく低下する一因となってしまう。
従って、バンプの接続信頼性を確保するために、実装ノズルの下降動作は、冷却処理による実装ノズルの収縮スピードよりも確実に早いスピードで行なうことが好ましい。
As described above, the mounting nozzle is gradually lowered over time so that the shrinkage of the mounting nozzle due to the cooling process does not change the 25 μm gap between the circuit board and the semiconductor chip. It is fully conceivable that the mounting nozzle contracts instantaneously during the operation.
In such a case, the operation of lowering the mounting nozzle cannot follow the instantaneous contraction operation of the mounting nozzle, resulting in stress on the bumps, and as shown in FIGS. 2 (a) and 2 (b). As shown in the figure, the connection between the electrode (
Therefore, in order to ensure the connection reliability of the bump, it is preferable that the mounting nozzle descending operation is performed at a speed that is surely faster than the contraction speed of the mounting nozzle by the cooling process.
なお、半導体チップを回路基板に実装した後に、半導体チップと電気的に接続された回路基板間に、例えば注入性の良いエポキシ樹脂を注入し、接続部を封止することによって、図４（ｅ）で示す様な半導体パッケージを得ることができる。 After mounting the semiconductor chip on the circuit board, for example, an epoxy resin having good injectability is injected between the circuit boards electrically connected to the semiconductor chip, and the connection portion is sealed, thereby FIG. A semiconductor package as shown in FIG.
上記した本発明を適用した半導体チップの実装方法の一例では、加熱処理時に実装ノズルを徐々に上昇させることによって、加熱処理で実装ノズルが膨張することによる回路基板と半導体チップとのギャップへの悪影響を抑制し、冷却処理時に実装ノズルを徐々に下降させることによって、冷却処理で実装ノズルが収縮することによる回路基板と半導体チップとのギャップへの悪影響を抑制することができ、回路基板と半導体チップとのギャップを高精度にコントロールすることができる。 In an example of the semiconductor chip mounting method to which the present invention is applied, the mounting nozzle is gradually raised during the heat treatment, and the mounting nozzle expands during the heat treatment, thereby adversely affecting the gap between the circuit board and the semiconductor chip. By suppressing the mounting nozzle gradually during the cooling process, the adverse effect on the gap between the circuit board and the semiconductor chip due to the shrinking of the mounting nozzle during the cooling process can be suppressed. Can be controlled with high accuracy.
図３は半導体チップを回路基板に実装する際の押圧治具である実装ノズルの位置及び温度、並びに半導体チップに印加される荷重値の時間的変化を示したグラフの他の一例である。 FIG. 3 is another example of a graph showing temporal changes in the position and temperature of a mounting nozzle, which is a pressing jig when a semiconductor chip is mounted on a circuit board, and the load value applied to the semiconductor chip.
本発明を適用した半導体チップの実装方法の他の一例では、上記した本発明を適用した半導体チップの実装方法の一例と同様に、先ず、半導体チップの電極に、はんだを主成分とする約１５μｍの高さを有するチップ側バンプを形成すると共に、半導体チップを実装するガラスエポキシ基板から成る回路基板の電極に、はんだを主成分とする約１５μｍの高さを有する基板側バンプを形成する。 In another example of the mounting method of the semiconductor chip to which the present invention is applied, as in the above-described example of the mounting method of the semiconductor chip to which the present invention is applied, first, the electrode of the semiconductor chip is about 15 μm mainly composed of solder. A chip-side bump having a height of about 15 μm mainly composed of solder is formed on an electrode of a circuit board made of a glass epoxy substrate on which a semiconductor chip is mounted.
次に、チップ側バンプが形成された半導体チップを反転して実装ノズルで吸着固定を行い、半導体チップを吸着固定した状態の実装ノズルを回路基板の上方より下降させる。なお、実装ノズルを回路基板の上方より下降させる動作は図３中符合ｅで示す期間である。 Next, the semiconductor chip on which the chip-side bumps are formed is reversed and suction-fixed by the mounting nozzle, and the mounting nozzle in a state where the semiconductor chip is suction-fixed is lowered from above the circuit board. The operation of lowering the mounting nozzle from above the circuit board is a period indicated by a symbol e in FIG.
ところで、半導体チップに形成されたチップ側バンプと回路基板に形成された基板側バンプが接触した後に、加熱処理による実装ノズルの膨張量よりも５μｍを減じた距離（図２中符合Ｚ１で示す距離）だけ実装ノズルを上昇させる。即ち、加熱処理を施した後の回路基板と半導体チップをのギャップが２５μｍとなる様に、加熱処理による実装ノズルの膨張量よりも５μｍを減じた距離だけ実装ノズルを上昇させる。なお、加熱処理により実装ノズルが膨張した場合に、回路基板と半導体チップとのギャップが２５μｍとなる様に、実装ノズルを上昇させるのは図３中符合ｆで示すタイミングである。
以下、この点について詳しく説明を行う。
By the way, after the chip-side bump formed on the semiconductor chip and the substrate-side bump formed on the circuit board come into contact with each other, a distance obtained by subtracting 5 μm from the expansion amount of the mounting nozzle by the heat treatment (the distance indicated by reference numeral Z1 in FIG. 2). ) Raise the mounting nozzle only. That is, the mounting nozzle is raised by a distance obtained by subtracting 5 μm from the expansion amount of the mounting nozzle by the heat treatment so that the gap between the circuit board after the heat treatment and the semiconductor chip is 25 μm. When the mounting nozzle expands due to the heat treatment, the mounting nozzle is raised at a timing indicated by a symbol f in FIG. 3 so that the gap between the circuit board and the semiconductor chip becomes 25 μm.
Hereinafter, this point will be described in detail.
先ず、約１５μｍの高さを有するチップ側バンプと約１５μｍの高さを有する基板側バンプとを突き合わせた状態（バンプの溶融前の状態）では、回路基板と半導体チップとのギャップは約３０μｍであり、バンプを一体化した後に回路基板と半導体チップとのギャップを２５μｍとするためには、半導体チップを回路基板側に５μｍだけ近づける必要がある。即ち、加熱処理によって実装ノズルが膨張しないと仮定した場合には、実装ノズルを５μｍだけ下降させれば良いということになる。
しかし、実際には加熱処理によって実装ノズルが膨張し、実装ノズルの膨張量は実装ノズルを下降させたものと同一視できるために、加熱処理によって実装ノズルが膨張しないと仮定した場合と同様に実装ノズルを下降させたのでは、回路基板と半導体チップとのギャップは２５μｍよりも小さくなってしまう。
そこで、加熱処理による実装ノズルの膨張量から５μｍを減じた距離だけ実装ノズルを上昇させておくことによって、加熱処理により実装ノズルが膨張した場合に、回路基板と半導体チップとのギャップを２５μｍとすることができるのである。
First, in a state where a chip side bump having a height of about 15 μm and a substrate side bump having a height of about 15 μm are abutted (before the bump is melted), the gap between the circuit board and the semiconductor chip is about 30 μm. In order to make the gap between the circuit board and the semiconductor chip 25 μm after the bumps are integrated, it is necessary to bring the semiconductor chip closer to the circuit board by 5 μm. That is, when it is assumed that the mounting nozzle does not expand due to the heat treatment, the mounting nozzle may be lowered by 5 μm.
However, since the mounting nozzle actually expands due to the heat treatment, and the amount of expansion of the mounting nozzle can be equated with the lowering of the mounting nozzle, it is mounted in the same way as if the mounting nozzle does not expand due to the heat treatment. When the nozzle is lowered, the gap between the circuit board and the semiconductor chip becomes smaller than 25 μm.
Therefore, by raising the mounting nozzle by a distance obtained by subtracting 5 μm from the expansion amount of the mounting nozzle by the heat treatment, when the mounting nozzle expands by the heat treatment, the gap between the circuit board and the semiconductor chip is set to 25 μm. It can be done.
ここで、本実施例では、半導体チップの加熱処理によってバンプが溶融した後に時間の経過に伴って徐々に実装ノズルを上昇させる方法（本発明を適用した半導体チップの実装方法の一例で採用している実装ノズルの制御方法）ではなく、加熱処理を行なう前に実装ノズルを上昇させており、こうした方法を採用することによって、バンプの接続信頼性を確保することができる。
即ち、加熱処理によってバンプが溶融した後に時間の経過に伴って徐々に実装ノズルを上昇させる方法も加熱処理前に実装ノズルを上昇させる方法も、加熱処理による実装ノズルの膨張が回路基板と半導体チップとのギャップである２５μｍを変動させないように実装ノズルを制御する方法であるが、バンプを溶融しているときに瞬間的に実装ノズルの膨張が生じることも考えられる。
このような場合に、時間の経過に伴って徐々に実装ノズルを上昇させる方法を採用していたのでは、実装ノズルを上昇させる動作が実装ノズルの瞬間的な膨張動作に追従できずに、結果的にバンプにストレスを与えることとなり、図２（ａ）や図２（ｂ）で示す様に、電極（半導体チップの電極、回路基板の電極）とバンプの接続部にクラックが生じたり、電極とバンプとの接続部から引きちぎれが生じたりする原因となり、接続信頼性が低下する一因となるとも考えられる。
従って、上記した通り、加熱処理を行なう前に実装ノズルを上昇させるといった実装ノズルの制御方法を採用することによって、バンプの接続信頼性を確保することができるのである。
Here, in this embodiment, the bump is melted by the heat treatment of the semiconductor chip, and then the mounting nozzle is gradually raised as time passes (an example of a semiconductor chip mounting method to which the present invention is applied). The mounting nozzle is raised before performing the heat treatment instead of the mounting nozzle control method), and by adopting such a method, it is possible to ensure the connection reliability of the bumps.
That is, both the method of gradually raising the mounting nozzle as time elapses after the bumps are melted by the heat treatment, and the method of raising the mounting nozzle before the heat treatment, the expansion of the mounting nozzle by the heat treatment is caused by the circuit board and the semiconductor chip. In this method, the mounting nozzle is controlled so that the gap of 25 μm is not changed. However, it is conceivable that the mounting nozzle instantaneously expands when the bump is melted.
In such a case, if the method of gradually raising the mounting nozzle with the passage of time was adopted, the operation of raising the mounting nozzle could not follow the instantaneous expansion operation of the mounting nozzle, resulting in a result Stress is applied to the bumps, and as shown in FIGS. 2 (a) and 2 (b), a crack is generated at the connection portion between the electrode (semiconductor chip electrode, circuit board electrode) and the bump, or the electrode. It may be a cause of tearing from the connection portion between the bump and the bump, and may be a cause of a decrease in connection reliability.
Therefore, as described above, the bump connection reliability can be ensured by adopting the mounting nozzle control method in which the mounting nozzle is raised before the heat treatment.
続いて、半導体チップの加熱処理によってバンプ（チップ側バンプ及び基板側バンプ）を溶融し、チップ側バンプと基板側バンプとを一体化する。上記した様に、加熱処理を行う前に、加熱処理による実装ノズルの膨張量よりも５μｍを減じた距離だけ実装ノズルを上昇させているために、加熱処理を行なうことによって回路基板と半導体チップとのギャップが２５μｍとなっている。なお、加熱処理を施すことにより実装ノズルが膨張している期間は図３中符合ｇで示す期間である。 Subsequently, the bumps (chip side bumps and substrate side bumps) are melted by heat treatment of the semiconductor chip, and the chip side bumps and the substrate side bumps are integrated. As described above, since the mounting nozzle is raised by a distance obtained by subtracting 5 μm from the expansion amount of the mounting nozzle due to the heat treatment before the heat treatment, the circuit board and the semiconductor chip are formed by performing the heat treatment. The gap is 25 μm. Note that the period during which the mounting nozzle is expanded by performing the heat treatment is a period indicated by the symbol g in FIG.
その後、回路基板と半導体チップとの間隙の２５μｍを確保しながら、一体化したバンプを凝固させるべく、時間の経過に伴って実装ノズルを下降させながら冷却処理を行なう。なお、冷却期間は図３中符合ｈで示す期間である。 Thereafter, in order to solidify the integrated bumps while securing a gap of 25 μm between the circuit board and the semiconductor chip, a cooling process is performed while lowering the mounting nozzle as time passes. The cooling period is a period indicated by a symbol h in FIG.
なお、半導体チップを回路基板に実装した後は、半導体チップと電気的に接続された回路基板間に、例えば注入性の良いエポキシ樹脂を注入し、接続部を封止することによって、図４（ｅ）で示す様な半導体パッケージを得ることができる。 Note that after the semiconductor chip is mounted on the circuit board, for example, an epoxy resin with good injectability is injected between the circuit boards electrically connected to the semiconductor chip, and the connection portion is sealed, so that FIG. A semiconductor package as shown in e) can be obtained.
上記した本発明を適用した半導体チップの実装方法の他の一例では、加熱処理前に実装ノズルを上昇させることによって、加熱処理で実装ノズルが膨張することによる回路基板と半導体チップとのギャップへの悪影響を抑制し、冷却処理時に実装ノズルを徐々に下降させることによって、冷却処理で実装ノズルが収縮することによる回路基板と半導体チップとのギャップへの悪影響を抑制することができ、回路基板と半導体チップとのギャップを高精度にコントロールすることができる。 In another example of the semiconductor chip mounting method to which the present invention is applied, by raising the mounting nozzle before the heat treatment, the gap between the circuit board and the semiconductor chip due to the expansion of the mounting nozzle by the heat treatment is reduced. By suppressing the adverse effect and gradually lowering the mounting nozzle during the cooling process, the adverse effect on the gap between the circuit board and the semiconductor chip due to the shrinking of the mounting nozzle by the cooling process can be suppressed. The gap with the tip can be controlled with high accuracy.
ここで、表１に従来のフリップチップ方式による半導体チップの実装におけるバンプの剥れ発生数及び剥れ発生率と、本発明を適用したフリップチップ方式による半導体チップの実装におけるバンプの剥れ発生数及び剥れ発生率とを示している。なお、表１は半導体チップ上に半導体チップをフリップチップ方式により実装した場合についてのバンプの剥れ発生数及び剥れ発生率を示している。 Here, Table 1 shows the number of bumps peeled off and the rate of peeling in the conventional flip chip mounting of the semiconductor chip, and the number of bumps peeling off in the flip chip mounting of the semiconductor chip to which the present invention is applied. And the occurrence rate of peeling. Table 1 shows the number of occurrences of bump peeling and the rate of peeling when a semiconductor chip is mounted on a semiconductor chip by a flip chip method.
表１からも明らかな様に、本発明を適用したフリップチップ方式による半導体チップの実装においては半導体チップと半導体チップとのギャップを高精度にコントロールすることができるために、従来のフリップチップ方式による半導体チップの実装方法と比較すると剥れ発生率が低減している。 As is apparent from Table 1, in the mounting of the semiconductor chip by the flip chip method to which the present invention is applied, the gap between the semiconductor chip and the semiconductor chip can be controlled with high accuracy. Compared with the mounting method of the semiconductor chip, the peeling occurrence rate is reduced.
１０ａ 半導体チップの電極
１０ｂ 回路基板の電極
２０ バンプ
10a
Claims (7)
前記第１の突起電極及び前記第２の突起電極に加熱処理を施し、押圧治具により前記半導体チップに荷重を印加して、前記第１の突起電極及び前記第２の突起電極を一体化する工程と、
一体化した前記第１の突起電極及び前記第２の突起電極に冷却処理を施す工程とを備える半導体チップの実装方法において、
前記加熱処理時または前記加熱処理前に前記基板と前記半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させる工程、若しくは、前記冷却処理時に前記基板と前記半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる工程を備える
ことを特徴とする半導体チップの実装方法。 Placing a semiconductor chip on which a second protruding electrode is formed on a substrate on which the first protruding electrode is formed in contact with the first protruding electrode and the second protruding electrode;
The first protruding electrode and the second protruding electrode are integrated by applying heat treatment to the first protruding electrode and the second protruding electrode, and applying a load to the semiconductor chip with a pressing jig. Process,
A method of mounting a semiconductor chip comprising: a step of performing a cooling process on the integrated first protruding electrode and the second protruding electrode;
The step of moving the pressing jig in the direction in which the gap between the substrate and the semiconductor chip is increased during the heat treatment or before the heat treatment, or the gap between the substrate and the semiconductor chip is reduced during the cooling process. A method of mounting a semiconductor chip, comprising: moving the pressing jig in a direction.
前記冷却処理時に前記基板と前記半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる工程とを備える
ことを特徴とする請求項１に記載の半導体チップの実装方法。 Moving the pressing jig in a direction in which a gap between the substrate and the semiconductor chip is increased during the heat treatment or before the heat treatment;
The semiconductor chip mounting method according to claim 1, further comprising a step of moving the pressing jig in a direction in which a gap between the substrate and the semiconductor chip is reduced during the cooling process.
ことを特徴とする請求項２に記載の半導体チップの実装方法。 The semiconductor chip mounting method according to claim 2, wherein the pressing jig is moved at a speed faster than a contraction speed of the pressing jig by the cooling process.
ことを特徴とする請求項２に記載の半導体チップの実装方法。 At the time of the heat treatment, the pressing jig is moved at a speed slower than the expansion speed of the pressing jig by the heat treatment, and at the time of the cooling processing, the speed is faster than the contraction speed of the pressing jig by the cooling processing. The semiconductor chip mounting method according to claim 2, wherein the pressing jig is moved.
前記第１の突起電極及び前記第２の突起電極に加熱処理を施し、押圧治具により前記第２の半導体チップに荷重を印加して、前記第１の突起電極及び前記第２の突起電極を一体化する工程と、
一体化した前記第１の突起電極及び前記第２の突起電極に冷却処理を施す工程とを備える半導体チップの実装方法において、
前記加熱処理時または前記加熱処理前に前記第１の半導体チップと前記第２の半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させる工程、若しくは、前記冷却処理時に前記第１の半導体チップと前記第２の半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる工程を備える
ことを特徴とする半導体チップの実装方法。 A second semiconductor chip on which a second protruding electrode is formed on a first semiconductor chip on which the first protruding electrode is formed is brought into contact with the first protruding electrode and the second protruding electrode. Arranging, and
The first protruding electrode and the second protruding electrode are subjected to heat treatment, a load is applied to the second semiconductor chip by a pressing jig, and the first protruding electrode and the second protruding electrode are moved. The process of integrating;
A method of mounting a semiconductor chip comprising: a step of performing a cooling process on the integrated first protruding electrode and the second protruding electrode;
The step of moving the pressing jig in the direction in which the gap between the first semiconductor chip and the second semiconductor chip is increased during the heat treatment or before the heat treatment, or during the cooling treatment A method of mounting a semiconductor chip, comprising a step of moving the pressing jig in a direction in which a gap between the semiconductor chip and the second semiconductor chip is reduced.
前記加熱処理時または前記加熱処理前に前記基板と前記半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させると共に、前記冷却処理時に前記基板と前記半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる押圧治具制御手段を備える
ことを特徴とする半導体チップの実装装置。 A semiconductor chip on which a second protruding electrode is formed on a substrate on which the first protruding electrode is formed is disposed with the first protruding electrode and the second protruding electrode being in contact with each other. The projecting electrode and the second projecting electrode are subjected to heat treatment, and a load is applied to the semiconductor chip with a pressing jig to integrate the first projecting electrode and the second projecting electrode, and then the two are integrated. In a semiconductor chip mounting apparatus that performs a cooling process on the first protruding electrode and the second protruding electrode,
The pressing jig is moved in a direction in which the gap between the substrate and the semiconductor chip is increased during the heat treatment or before the heat treatment, and the gap between the substrate and the semiconductor chip is reduced in the cooling process. A semiconductor chip mounting apparatus comprising: a pressing jig control means for moving the pressing jig.
前記加熱処理時または前記加熱処理前に前記第１の半導体チップと前記第２の半導体チップとの間隙が大きくなる方向に前記押圧治具を移動させると共に、前記冷却処理時に前記第１の半導体チップと前記第２の半導体チップとの間隙が小さくなる方向に前記押圧治具を移動させる押圧治具制御手段を備える
ことを特徴とする半導体チップの実装装置。 A second semiconductor chip on which a second protruding electrode is formed on a first semiconductor chip on which the first protruding electrode is formed is brought into contact with the first protruding electrode and the second protruding electrode. The first protruding electrode and the second protruding electrode are disposed and subjected to a heat treatment on the first protruding electrode and the second protruding electrode, and a load is applied to the second semiconductor chip by a pressing jig. In the semiconductor chip mounting apparatus that performs cooling treatment on the integrated first protruding electrode and the second protruding electrode after integrating the electrodes,
The pressing jig is moved in a direction in which a gap between the first semiconductor chip and the second semiconductor chip is enlarged during the heat treatment or before the heat treatment, and the first semiconductor chip is used during the cooling treatment. And a pressing jig control means for moving the pressing jig in a direction in which a gap between the second semiconductor chip and the second semiconductor chip is reduced.
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| JP2006030690A JP2007214241A (en) | 2006-02-08 | 2006-02-08 | Method and device for mounting semiconductor chip |
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| JP2006030690A JP2007214241A (en) | 2006-02-08 | 2006-02-08 | Method and device for mounting semiconductor chip |
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| JP2016009763A (en) * | 2014-06-24 | 2016-01-18 | イビデン株式会社 | Multilayer printed wiring board and method of manufacturing the same |
| CN113675125A (en) * | 2020-05-15 | 2021-11-19 | 台湾爱司帝科技股份有限公司 | Chip bearing structure, chip placing system and chip placing method |
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