JPH1123656A - Method and board for inspecting flip-chip ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure electrical connection of a flip-chip IC and a board by forming solder bump connection pad parts on a board in same pattern as the solder bumps of a semiconductor device while projecting above the surface of a thin film on the board. SOLUTION: Solder bump connection pad parts 7 of a conductive metal material are formed on the ceramic multilayer wiring board of an inspection board 3 in same pattern as the solder bumps 2 formed on a semiconductor TC 1 while projecting about 30 μm above an insulating organic thin film 6. The semiconductor IC 1 is positioned on the inspection board 3 and mounted thereon in the atmosphere of inert gas, or the like, by IR reflow, or the like. The solder bump 2 on the semiconductor IC 1 is wetted surely to the connection pad part 7 to form an intermetallic compound thus providing a stabilized electric connection between the semiconductor IC 1 and the inspection board 3. Subsequently, an inspection probe 5 touches a probe contact inspection pad 4b to inspect the electrical characteristics of the semiconductor IC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip semiconductor device, and more particularly to an electrical inspection method and an inspection substrate used for the method.

[0002]

2. Description of the Related Art Due to the miniaturization in the manufacturing technology of semiconductor ICs (hereinafter referred to as "ICs") and the accompanying trend of high integration, high functionality, and multi-terminals, the connection terminals of these ICs and the circuit board have to be increased. The connection between the connection terminals has also been miniaturized,
There is a demand for multiple terminals. For the connection method between the IC and the circuit board, wire bonding method, TAB (tape automatedb)
Onding) method, flip chip method and the like are known, but flip chip method is suitable as a high-density mounting method of an IC having multiple terminals. The reason is that in the flip chip method, connection terminals can be provided on the entire surface of the IC surface, and the number of terminals can be easily increased as compared with the wire bonding method in which connection terminals are provided on the periphery of the IC surface and the TAB method. It depends. In addition, since the flip-chip method has a short wiring length for connection, it has excellent electrical characteristics.

[0003] For these reasons, the flip-chip method has been studied or put into practical use as one of the mounting methods, especially as a mounting method for a large computer. Recently, the mounting method for electronic parts for liquid crystal display has been studied. It is also being considered.

In the conventional flip chip method, for example, a solder bump is formed on a pad portion formed on an IC surface by a plating method or a solder ball supply method. Various researches and experiments have been conducted, for example, adoption of gold bumps, copper bumps, or gold ball bumps by a wire bonding method, and changes in the shape of solder bumps from spherical to drum-like.

[0005] Conventionally, flip-chip type semiconductor elements have been used in a wafer state before cutting into chips.
Electrical evaluation of (DC) characteristics etc. is performed. For electrical evaluation of AC (AC) characteristics, etc., flip chip bonding is performed on the package or circuit board on which the chip is mounted, and finished in the form of the final product It has been done since. However, after the flip-chip bonding is performed, the characteristics of the mounting substrate are evaluated, and if a defect is detected, it is very difficult to remove (repair) the chip.

As described above, in the flip-chip method, the final evaluation of the electrical characteristics is performed after the flip-chip bonding, so that if there is an abnormality in the chip, the loss in the manufacturing process is large. There was a problem.

The main reason for this is that it is difficult to fully evaluate the final electrical characteristics in a chip state before performing flip chip bonding.

For example, as shown in FIG. 3, an anisotropic conductive sheet 10 is interposed between the semiconductor IC 1 and the inspection substrate 3, and the back surface of the semiconductor IC 1 is pressed by a metal plate 9, so that the semiconductor IC 1 Solder bump 2 formed
And an inspection pad 4a formed in the inspection substrate 3.
A method is known in which an electrical connection between the semiconductor IC 1 and the semiconductor IC 1 is made by bringing the test probe into contact with a probe contacting test pad 4 b formed in the test substrate 3. .

In this method, slight variations in the height direction of the solder bumps 2 of the semiconductor IC 1 can be absorbed by the anisotropic conductive sheet 10, and the solder bumps 2 and the inspection pads 4 can be absorbed.
It is also possible that contact a is completely obtained.

[0010] However, the conduction resistance of the anisotropic conductive sheet 10 is as large as, for example, several hundred mΩ to several Ω.

When the semiconductor IC 1 is a power IC or the like, a large current at the time of inspection generates heat in the anisotropic conductive sheet 10 and its physical property value is deteriorated. Due to the difference in height, a difference occurs in the contact resistance between each solder bump 2 and the anisotropic conductive sheet 10,
Therefore, there is also a problem that a stable electrical characteristic test cannot be performed.

In the case of a multi-terminal (multi-pin) IC, a large pressure, for example, a 300-pin IC is required to obtain perfect contact.
In C, a pressure of about 4.5 kg to 6 kg is required,
Due to this pressure, the multilayer wiring portion of the semiconductor IC 1 formed below the solder bumps 2 of the semiconductor IC 4, the circuit formation portion thereunder, and the inspection substrate 3 may be broken (dangerous). There were various problems.

As shown in FIG. 4, in order to obtain stable electrical connection between the semiconductor IC 1 and the inspection substrate 3, the semiconductor IC 1 is directly connected to the inspection substrate 3 by a reflow furnace using an inert gas. For example, a method of electrically connecting the semiconductor IC 1 and the test board 3 by soldering the solder bumps 2 to the test pads 4a formed on the test board 3 is also known. However, when the diameter of the inspection pad 4a of the inspection substrate 3 is the same as the land diameter of the solder bump 2 formed on the semiconductor IC 1, the predetermined inspection is completed after mounting the semiconductor IC 1 on the inspection substrate 3. After doing
When the semiconductor IC 1 is detached from the inspection substrate 3, damage such as a change in the shape of the solder bump 2 and a decrease in the amount of solder is large.
Before mounting on a final circuit board, it is necessary to re-form solder bumps and the like, which is not suitable for practical use.

Further, for example, Japanese Patent Application Laid-Open No. 7-12892 discloses that in a test of a semiconductor element to be flip-chip mounted, the semiconductor element is connected so as not to apply a mechanical pressure to the semiconductor element, and the semiconductor element may be broken during the inspection. An inspection jig for a semiconductor element and an inspection method thereof have been proposed. FIG. 5 is a sectional view showing a method of connecting a test jig and a semiconductor element described in the above-mentioned Japanese Patent Application Laid-Open No. 7-12892 in the order of steps.

Referring to FIG. 5, the inspection jig 16 of the semiconductor IC 1 is provided with a circuit board in which the electrodes 14 are formed of a metal having poor solder wettability, such as Cr, Ti or W, in order to obtain electrical continuity with the semiconductor IC 1. 11 and a part of the electrode 14, and
Insulator 1 formed so as to provide a hollow portion on electrode 14
The test jig 16 and the semiconductor IC 1 are heated to a temperature at which the solder bumps 2 are softened, and the semiconductor IC 1 is brought into contact with the test jig 16 (see FIG. 5B). Is filled by the plastic deformation of the solder bump 2 (see FIG. 5C), the inspection jig 16 and the semiconductor IC
1 is cooled, and then the semiconductor element is pressed to obtain stable electrical conduction.

However, in this conventional inspection method, since the electrode portion 14 is made of a metal having poor solder wettability, such as Cr, Ti, or W, Cr, Ti, and the like are required to be temporarily connected to the solder bumps 2. , W or the like, an insulating oxide film of a metal having poor solder wettability may be formed, and stable electrical conduction may not be obtained.

In addition, no intermetallic compound is formed between the solder bump 2 and the electrode portion 14. In order to obtain stable electrical conduction, it is necessary to press the semiconductor IC 1 so that the solder bump is plastically deformed. Although the load can be reduced because of this, an external stress must be applied to the semiconductor IC 1, and there is a possibility that the semiconductor IC may eventually be destroyed.

After the inspection, the semiconductor IC 1 needs to be removed.
Since the solder bumps 2 enter the hollow portions, there is a possibility that the solder bumps 2 may be destroyed when the semiconductor IC 1 is removed, and this inspection method is implemented in order to ensure the quality of the semiconductor IC 1 in practical use. It is extremely difficult to do.

Further, as shown in a sectional view of FIG. 6, an electrical conduction state between the solder bumps 2 formed on the semiconductor IC 1 and the inspection substrate 3 can be ensured, and the semiconductor IC 1
There is known a method of reducing damage to the solder bumps 2 formed on the semiconductor IC 1 in a removal step after the completion of the electrical characteristic test. FIG. 6B shows FIG.
FIG. 6A is a partially enlarged cross-sectional view of a portion B of FIG. 6A (that is, a portion of the inspection pad 4 a and the solder ball 2), and is a diagram showing a state before solder reflow; FIG. Of B
FIG. 5 is a partially enlarged cross-sectional view of a portion, showing a state after solder reflow.

Referring to FIG. 6, in the conventional inspection method, the structure of the inspection pad 4a of the inspection substrate 3 is changed to Cu,
A first metal layer 19 made of Ni or the like having excellent solder wettability is provided, and a second metal layer 18 made of Ti, Cr or the like having poor solder wettability is provided thereon, and Au or the like is provided thereon. An inspection substrate dedicated to a flip-chip IC having a third metal layer 17 having a high solder solid solubility is used.

In this conventional method, in order to inspect the electrical characteristics of the flip chip IC, the electrical connection between the solder bumps 2 and the inspection substrate 3 is performed by soldering the flip chip IC 1 and the inspection substrate 3. However, at this time, the third metal layer 17 made of Au or the like and having a high solder solid solubility on the inspection pads 4a of the inspection substrate 3 is provided.
Is dissolved in most of the solder bump 2, but the second metal layer 18, which is lower than the third metal layer 17 and has poor solder wettability made of Ti, Cr, or the like, is wet with the solder bump 2. There is no.

That is, at the time of the electrical characteristic inspection, only a small part of the Au existing at the interface between the solder bump 2 and the pad 4a is used.
Only the presence of the -Sn-based intermetallic compound ensures the electrical continuity between the solder bump 2 and the test substrate 3.

Also, in the removal step after the completion of the electrical characteristic inspection, the electrical conduction between the solder bump 2 and the inspection substrate 3 is a small part of the Au-Sn-based material existing at the interface between the solder bump 2 and the pad. Since only the intermetallic compound is used, it is easy to minimize damage to the solder bumps during the removal process.

However, in the above-described conventional method shown in FIG. 6, at the time of inspection, an electrical conduction portion between the solder bump 2 and the inspection substrate 3 has a small portion of Au existing at the interface between the solder bump 2 and the pad. Since only the Sn-based intermetallic compound and the Au-Sn-based intermetallic compound are very fragile substances against external stress, the solder bumps 2 are required at the time of handling work at the time of electrical characteristic inspection and at the time of inserting the sorting socket. There is a possibility that the pad interface will peel off.

At the end of the electrical characteristic inspection, the third metal layer 17 made of Au or the like and having a high solder solid solubility is hardly present. The third metal layer 17 made of Au or the like and having a high solder solid solubility needs to be formed again on the pad portion 4a of the substrate 3, and there is a problem in the recyclability of the inspection substrate 3.

[0026]

The problems of the prior art described above in detail are summarized as follows.

(1) In the flip-chip method, the final evaluation of the electrical characteristics is performed after the flip-chip bonding, so that if there is an abnormality in the chip, the loss in the manufacturing process is large. Has problems.

The reason is that it is difficult to sufficiently evaluate the final electrical characteristics in a chip state before performing flip chip bonding.

Further, regarding the quality assurance method of the flip-chip IC, when the semiconductor IC is temporarily housed in an inspection package and the flip-chip IC is removed from the inspection substrate in the flip-chip IC inspection process, This is because a technique that does not damage the flip chip IC, such as deformation of the solder bumps and a decrease in the amount of solder, and that has excellent mass productivity such as reuse of an inspection substrate has not been realized.

(2) More specifically, in the conventional pressing contact method, a load variation per solder bump occurs due to the presence of a variation in the height of the solder bumps and the presence of a warp on the back surface of the semiconductor IC when pressed. As a result, there is a problem that stable conduction between the solder bumps and the inspection substrate cannot be obtained.

The concentration of local stress on the solder bumps existing in the semiconductor IC causes a multilayer wiring portion of the semiconductor IC formed below the solder bumps of the semiconductor IC and a circuit forming portion thereunder. There is also a problem that the inspection substrate may be destroyed.

(3) In the conventional soldering method, after the semiconductor IC is mounted on the inspection board, when the semiconductor IC is removed from the inspection board after a predetermined inspection, the shape of the solder bumps and the amount of solder are removed. There is a problem that damage such as reduction is large, and it is necessary to re-form solder bumps before mounting on a final circuit board.

Therefore, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to ensure that the electrical connection between the flip-chip IC and the inspection substrate is ensured and that the electrical characteristics are improved. Flip chip IC after test
An object of the present invention is to provide an inspection method and an inspection substrate that greatly reduce damage (damage) to solder bumps formed in a flip-chip IC even in the removal.

Another object of the present invention is to reduce the shear stress on the solder bumps caused by the thermal stress during the electrical characteristic test, and to improve the connection reliability between the solder bumps and the test board during the inspection. An object of the present invention is to provide an improved inspection substrate and an inspection substrate that can be easily reused.

[0035]

In order to achieve the above object, the present invention relates to a dedicated inspection board used in an electrical selection process of a semiconductor device with solder bumps (referred to as "flip chip IC"). On the top, an organic multilayer wiring using an insulating organic thin film material has a solder bump connection pad portion made of a conductive metal material excellent in solder wettability having the same pattern as the solder bump formation pattern of the semiconductor device. A diameter of the solder bump connection pad portion is formed to protrude above a surface of the insulating organic thin film, and a diameter of the solder bump is smaller than a diameter of the solder bump; It is characterized by being formed with a ratio dimensional value.

[0036]

Embodiments of the present invention will be described. In a preferred embodiment of the present invention, a semiconductor IC with solder bumps (referred to as “flip chip IC”)
In the electrical sorting process, a special test substrate is used, and the test substrate is made of aluminum oxide,
A flip-chip IC-side solder bump formation pattern is formed on a ceramic multilayer wiring substrate made of a high-performance inorganic ceramic material such as mullite or aluminum nitride by organic multilayer wiring using an insulating organic thin film material made of PI (polyimide) or the like. A solder bump connection pad portion made of a conductive metal material such as Cu or Ni having the same pattern and excellent solder wettability is formed so as to protrude upward from an organic insulating layer made of PI or the like, and The diameter of the solder bump connection pad portion made of the conductive metal material is preferably formed with a dimension value in the range of 1/3 to 1/6 with respect to the diameter of the solder bump. It is characterized by using a flip-chip IC inspection substrate.

In the embodiment of the present invention, in order to secure a stable electrical connection between the flip-chip IC and the test substrate, the flip-chip IC is positioned on the test substrate and mounted, and then the inert gas is removed. (Infrared) reflow method in an atmosphere such as
The flip-chip IC is mounted on an inspection substrate by a Phase Soldering method or the like. At this time, the bumps formed on the flip-chip IC are higher than the organic insulating layer made of PI (polyimide) or the like formed on the inspection substrate due to plastic deformation at the time of soldering and liquefaction. The solder bump connection pad portion, which protrudes by about 10 to 30 μm and is made of a conductive metal material such as Cu or Ni and has excellent solder wettability, is surely wetted. Once formed, it is easy to make a stable electrical connection between the flip-chip IC and the test substrate.

Further, in the embodiment of the present invention, the solder bump connection pad portion protrudes upward from the organic insulating layer made of PI or the like by about 10 to 30 μm, so that the solder bump on the flip chip IC can be formed. Even if there is some variation in height, the plastic bumps during soldering and the liquefaction make it easier for the solder bumps and the solder bump connection pad parts to come into contact, and a stable connection between the flip chip IC and the inspection board is obtained. It is easy to make an electrical connection state.

Further, in the embodiment of the present invention, in the flip chip IC removing step after the completion of the electrical characteristic inspection step, it is necessary to minimize the damage to the solder bumps formed on the flip chip IC. In order to facilitate the reuse and reuse of the inspection substrate, the diameter of the solder bump connection pad portion (7 in FIG. 1) made of a conductive metal material is preferably 1 to the diameter of the solder bump.
Since the dimensional value is formed in the range of to １ ／, the solder loss of the solder bump (2 in FIG. 1) on the semiconductor IC (1 in FIG. 1) is reduced, and the shape of the solder bump after removal is reduced. The above can be minimized, and since only a small amount of solder remains on the solder bump connection pad portion (7 in FIG. 1) on the removal inspection board, the solder bump connection pad portion 7 This eliminates the need for the solder removing step, and facilitates reuse of the inspection substrate.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing a configuration and an inspection process according to an embodiment of the present invention. In FIG. 1, 1 is a semiconductor I
C, 2 are solder bumps formed on the semiconductor IC, 3
Denotes an inspection substrate, 4a denotes an inspection pad, 4b denotes a probe contact inspection pad, 5 denotes an inspection probe, 6 denotes an insulating organic thin film, and 7 denotes a solder bump connection pad portion.

In the electrical selection process of the semiconductor IC 1 with solder bumps (referred to as “flip-chip IC”), the inspection substrate 3 mounted exclusively for inspection is made of aluminum oxide,
The solder existing on the semiconductor IC 1 is formed on a ceramic multilayer wiring board made of a high-performance inorganic ceramic material such as mullite or aluminum nitride by an organic multilayer wiring technique using an insulating organic thin film material made of PI (polyimide) or the like. The solder bump connecting pad portion 7 made of a conductive metal material made of Cu, Ni or the like having the same pattern as the bump 2 forming pattern and having excellent solder wettability is positioned from above the organic insulating layer 6 made of PI or the like. It is formed so as to protrude by about 30 μm.

At this time, an Au plating layer may be formed on the solder bump connection pad portion 7 made of a conductive metal material such as Cu or Ni for the purpose of preventing metal oxidation and improving solder wettability.

After the semiconductor IC 1 is positioned and mounted on the inspection substrate 3, the semiconductor IC 1 is placed in an atmosphere of an inert gas or the like.
IR reflow method and VPS (Vapor Phase)
The semiconductor IC 1 is mounted on the inspection substrate 3 by a Soldering method or the like (see FIG. 1B).

At this time, the solder bump 2 formed on the semiconductor IC 1 is subjected to plastic deformation and liquefaction at the time of soldering, so that the insulating organic thin film 6 made of PI or the like formed on the inspection substrate 3 is formed. The solder bump connection pad portion 7 (made of a conductive metal material such as Cu, Ni or the like) that protrudes from the upper side by about 10 μm from the upper side 10 is surely wet, and the solder bump connection pad portion 7 and the intermetallic compound Is formed, and a stable electrical connection state between the semiconductor IC 1 and the inspection substrate 3 can be easily obtained.

Further, the pad portion 7 for connecting the solder bump is PI
10 to 30 μm above the organic insulating layer composed of
Because of the protrusion, the solder bumps 2 and the pad portions 7 for connecting the solder bumps are deformed due to plastic deformation and liquefaction at the time of soldering, even if the height of the solder bumps 2 on the semiconductor IC 1 slightly varies. The contact becomes easy, and a stable electrical connection state between the semiconductor IC 1 and the inspection substrate 3 can be obtained.

Thereafter, the inspection probe 5 is connected to the inspection substrate 3
(See FIG. 1 (b)), and contact the semiconductor I under predetermined conditions.
An electrical characteristic test of C is performed.

At this time, the coefficient of linear expansion of the insulating organic thin film 6 made of PI or the like on the inspection substrate 3 is calculated by
Aluminum oxide present under the insulating organic thin film 6,
By adopting an intermediate value between high performance inorganic ceramic materials such as mullite and aluminum nitride,
1 caused by a bimetallic effect caused by a difference in linear expansion coefficient between a high-performance inorganic ceramic material and a high-performance inorganic ceramic material.
The shear stress to the solder bump 2 on C1 can be reduced, and the connection reliability at the time of an electrical characteristic test can be improved.

After completion of the electrical characteristic test, the semiconductor IC
The substrate 3 on which the semiconductor chip 1 is mounted is heated again, and the back surface of the semiconductor IC 1 is vacuum-sucked near the melting temperature of the solder bumps and removed from the substrate 3 for inspection (see FIG. 1C).

At this time, since the diameter of the solder bump connecting pad portion 7 made of a conductive metal material is formed in a dimension value within the range of １ ／ to １ ／ of the diameter of the solder bump 2. In addition, it is possible to reduce the solder loss of the solder bump 2 on the semiconductor IC 1 and minimize the shape abnormality of the solder bump 2 after removal.

Further, since only a small amount of solder remains in the solder bump connecting pad portion 7 on the inspection board 2 after removal, there is no need for a solder removing step on the solder bump connecting pad portion 7. The inspection substrate 3 can be reused.

One embodiment of the present invention will be further described below based on experimental data.

FIG. 2 is an enlarged view showing a cross section of the mounted state of the semiconductor IC 1 and the inspection substrate 3 in one embodiment of the present invention.

Referring to FIG. 2, the diameter X of the solder bump 2 of the flip-chip IC is set to a fixed value of 180 μm, and the diameter Y of the solder bump connecting pad portion 7 of the inspection board 3 is set to 30 μm.
Table 1 shows the evaluation results when the levels of m, 50 μm, and 70 μm were provided.

The following processing was performed on the evaluation sample.

The flip chip IC 1 is mounted on the inspection board 3.

The inspection substrate 3 and the flip chip IC 1 are removed.

Table 1 shows the results of an electrical continuity test (the number of pads in the electrically open state) performed on about 2,500 solder bumps as an evaluation of the stability of substrate mounting.

The flip-chip IC thus removed is subjected to re-bump wet-back processing.

The sample subjected to the re-soldering bump wet-back process is compared with the solder bump height before mounting the inspection board, and the effect of the difference in the diameter Y of the solder bump connection pad portion 7 (bump height displacement). Average). Table 2 shows the results.

[0061]

[Table 1]

[0062]

[Table 2]

According to the evaluation results shown in Tables 1 and 2, the diameter Y of the solder bump connection pad portion 7 of the inspection board with respect to the diameter X of the solder bump 2 is in the range of 1/6 to 1/3. The inspection substrate 3 of the flip-chip IC 1
It is possible to secure a stable electrical conduction state in the mountability to the device and the removability, and to reduce the damage to the solder bumps after the removal, and to secure a level at which there is no problem in practical use. You can see that.

[0064]

As described above, according to the present invention,
The following effects are obtained.

(1) The first effect of the present invention is that the electrical continuity between the flip-chip IC and the inspection substrate used in the electrical characteristic inspection process can be easily secured with a low load and a stable electrical continuity state. That you can do it.

The reason for this is that, in the present invention, in the electrical inspection process of the flip-chip IC, as a means for establishing conduction between the inspection substrate and the solder bump portion of the flip-chip IC, it is necessary to use an inert gas atmosphere or the like. Reflow method and VPS (VaporPhase Solder)
ing) method or the like, the semiconductor IC is mounted on the inspection substrate, so that the solder bumps formed on the semiconductor IC
Due to plastic deformation and liquefaction at the time of soldering, a conductive material that protrudes a predetermined height above the organic insulating layer made of PI or the like formed on the inspection substrate and has excellent solder wettability The solder bump connection pad portion made of a metal material is reliably wetted, the solder bump connection pad portion and the intermetallic compound are formed, and a stable electrical connection state between the semiconductor IC and the inspection substrate can be obtained. That's why.

(2) The second effect of the present invention is that, in the flip chip IC removal step after the completion of the electrical characteristic inspection step, damage to the solder bumps formed on the flip chip IC can be suppressed to a minimum. ,That's what it means.

The reason for this is that, in the present invention, the diameter of the solder bump connection pad portion made of a conductive metal material is formed at a dimensional value within a predetermined ratio with respect to the diameter of the solder bump. This is because it is possible to reduce the solder loss of the solder bumps on the semiconductor IC and minimize the solder bump shape after removal.

(3) The third effect of the present invention is that the inspection substrate can be reused.

The reason for this is that, together with the reason for the second effect, only a small amount of solder remains on the solder bump connection pad portion on the inspection board after removal, so that the solder bump connection pad This is because there is no need for a solder removal step, and the inspection substrate can be reused.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of an embodiment of the present invention;
(A) is a diagram showing the semiconductor IC before mounting, (b) is after mounting, and (c) is a diagram showing the semiconductor IC after removal.

FIG. 2 is an enlarged cross-sectional view of an enlarged cross-sectional view showing a mounted state of a semiconductor IC and an inspection board according to one embodiment of the present invention, and is a partial enlarged view of a portion A in FIG. .

FIG. 3 is a cross-sectional view illustrating a configuration of a conventional technique.

FIG. 4 is a cross-sectional view illustrating a configuration of a second conventional technique.

FIG. 5 is a sectional view showing a method of connecting an inspection jig and a semiconductor element according to a third conventional technique in the order of steps.

FIG. 6 is a cross-sectional view illustrating a configuration of a fourth conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor IC 2 Solder bump 3 Inspection board 4a Inspection pad 4b Inspection pad for probe contact 5 Inspection probe 6 Insulating organic thin film 7 Solder bump connection pad part 8 Screw 9 Metal plate 10 Anisotropic conductive sheet 11 Circuit board 12 Seal 13 Insulator 14 Electrode 15 Heater 16 Inspection jig 17 Au thin film layer 18 Metal thin film layer with poor solder wettability 19 Metal layer with excellent solder wettability

Claims (9)

[Claims] 1. A test board for exclusive use used in an electrical selection step of a semiconductor device with solder bumps (referred to as "flip chip IC"), wherein an organic multilayer wiring using an insulating organic thin film material is provided on the substrate. Accordingly, the solder bump connection pad portion having the same pattern as the solder bump formation pattern of the semiconductor device and made of a conductive metal material having excellent solder wettability projects above the surface of the insulating organic thin film. And the diameter of the solder bump connection pad portion is smaller than the diameter of the solder bump and is formed at a dimension value of a predetermined ratio of the diameter of the solder bump. Inspection board for flip chip IC. 2. The inspection board for a flip-chip IC according to claim 1, wherein said board is made of a ceramic multilayer wiring board made of an inorganic ceramic material. 3. The inspection substrate according to claim 1, wherein the insulating organic thin film material is made of PI (polyimide). 4. The solder bump connection pad part has a diameter of:
2. The solder bump according to claim 1, wherein said solder bump has a dimension value within a range of 1/3 to 1/6 of a diameter of said solder bump.
Inspection substrate for flip-chip IC according to the above. 5. The method according to claim 1, wherein the conductive metal material is Cu or N.
2. The inspection substrate for a flip-chip IC according to claim 1, wherein the substrate comprises i. 6. The flip-chip IC inspection substrate according to claim 1, wherein an Au plating is provided on a surface of the conductive metal material as means for securing solder wettability and preventing oxidation. 7. The flip-chip IC test board according to claim 1, wherein the insulating organic thin film material has a linear expansion coefficient having an intermediate value between the semiconductor device and the test board. 8. A test board for exclusive use used in an electrical selection process of a semiconductor device with solder bumps (referred to as “flip chip IC”), wherein a predetermined height is higher than an organic insulating layer formed on the substrate. A solder bump connection pad portion made of a conductive metal material having excellent solder wettability, wherein the diameter of the solder bump connection pad portion is smaller than the diameter of the solder bump of the semiconductor device. Wherein the solder bumps are formed at a predetermined ratio of the diameter of the solder bumps. 9. An inspection substrate for a flip-chip IC used in an electric selection process for a semiconductor device with solder bumps (referred to as “flip-chip IC”), wherein an insulating organic thin film material is used on the substrate. Due to the organic multilayer wiring, a solder bump connection pad portion having the same pattern as the solder bump formation pattern of the semiconductor device and made of a conductive metal material having excellent solder wettability protrudes upward from the organic insulating layer. And the diameter of the solder bump connection pad portion is smaller than the diameter of the solder bump, and is formed at a predetermined ratio of the diameter of the solder bump. A flip-chip IC is temporarily mounted on a substrate by soldering, and an electrical inspection of the semiconductor device is performed.査用 removing the flip chip IC from the substrate, an electrical test method for flip chip IC, characterized in that.