JPH08102453A - Manufacture of semiconductor element and structure of wafer dicing part - Google Patents

Manufacture of semiconductor element and structure of wafer dicing part

Info

Publication number
JPH08102453A
JPH08102453A JP26174894A JP26174894A JPH08102453A JP H08102453 A JPH08102453 A JP H08102453A JP 26174894 A JP26174894 A JP 26174894A JP 26174894 A JP26174894 A JP 26174894A JP H08102453 A JPH08102453 A JP H08102453A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor element
dicing
passivation film
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26174894A
Other languages
Japanese (ja)
Inventor
Tatsuya Kishimoto
達也 岸本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP26174894A priority Critical patent/JPH08102453A/en
Publication of JPH08102453A publication Critical patent/JPH08102453A/en
Pending legal-status Critical Current

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  • Dicing (AREA)

Abstract

PURPOSE: To make it possible to inhibit not only the generation of large cracks but also the generation of small cracks on a wafer by a method wherein members with a hardness smaller than that of a passivation film on semiconductor element main bodies are provided along dicing parts on the side of the surface, which are formed with the semiconductor element main bodies, of the wafer and after that, the wafer is diced into the semiconductor element main bodies. CONSTITUTION: A wafer 1 is diced between semiconductor light-emitting elements 2 by a high-speed rotation diamond blade and is split into a plurality of the semiconductor light-emitting elements 2 by the dicing. Members 10 with a hardness smaller than that of a passivation film 9 on the side of the surface of the wafer 1 are provided along dicing parts on the passivation film 9. When the wafer 1 is diced, vibrations, which are generated on a substrate 4, are absorbed by the metal members 10 and the generation of cracks on the substrate 4 can be inhibited. Thereby, the elements 2 are prevented from being produced as a defective by the crack and the dimensional accuracy of the elements 2 can be prevented from being reduced by the crack.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ダイシングによりウエ
ハーを複数の半導体素子に分割する工程を有する半導体
素子の製造方法と、そのウエハーのダイシング部構造に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of dividing a wafer into a plurality of semiconductor devices by dicing, and a dicing structure of the wafer.

【0002】[0002]

【従来の技術】一枚のウエハーをダイシングにより複数
の半導体素子に分割する際、その半導体素子に欠けが発
生するのを防止する必要がある。そこで、図6に示すよ
うに、そのウエハー101に形成される各半導体素子1
03のパッシベーション膜104を、ダイシング部に沿
ってエッチングにより除去することで、溝状のダイシン
グライン105を形成している。そのダイシングライン
105に沿ってウエハー101をダイシングすると、図
7の(1)に示すように、そのパッシベーション膜10
4を除去した領域では欠け106が発生するが、その欠
けの伸びはダイシングライン105の縁105′におい
て阻止される。これは、ダイシングの際に欠けが発生す
るのは、そのウエハー101を構成する硬度の大きなシ
リコン(Si)等の基板102を削るように切断するこ
とで振動が生じ、その振動が衝撃として作用して生じる
ストレスに起因するが、その基板102と異質の窒化珪
素(SiN)等のパッシベーション膜104が存在する
ことで、その振動を吸収して欠けの伸びを阻止するため
と考えられている。
2. Description of the Related Art When a single wafer is divided into a plurality of semiconductor elements by dicing, it is necessary to prevent chipping of the semiconductor elements. Therefore, as shown in FIG. 6, each semiconductor element 1 formed on the wafer 101
The passivation film 104 of No. 03 is removed by etching along the dicing portion to form the groove-shaped dicing line 105. When the wafer 101 is diced along the dicing line 105, the passivation film 10 is diced as shown in (1) of FIG.
A chip 106 is generated in the area where 4 is removed, but the elongation of the chip is blocked at the edge 105 ′ of the dicing line 105. This is because chipping occurs during dicing because vibration is generated by cutting the substrate 102 such as silicon (Si) having a high hardness that constitutes the wafer 101 so as to cut, and the vibration acts as a shock. It is considered that, due to the stress generated as a result, the presence of the passivation film 104 of silicon nitride (SiN) or the like, which is different from the substrate 102, absorbs the vibration and prevents the elongation of the chip.

【0003】[0003]

【発明が解決しようとする課題】しかし、そのダイシン
グライン105による欠けの発生防止効果は充分ではな
く、図7の(2)に示すように、そのダイシングライン
105を超えて欠け106が発生して半導体素子103
が不良品となることがあった。また、半導体素子103
の寸法精度を厳しく要求され、大きな欠けだけでなく小
さな欠けの発生も抑制する必要がある場合には、そのよ
うなダイシングライン105では対応できなかった。
However, the dicing line 105 does not have a sufficient effect of preventing the chipping, and as shown in FIG. 7B, the chipping 106 occurs beyond the dicing line 105. Semiconductor element 103
Was sometimes defective. In addition, the semiconductor element 103
In the case where the dimensional accuracy of No. 2 is strictly required and it is necessary to suppress not only a large chipping but also a small chipping, such a dicing line 105 cannot handle it.

【0004】本発明は、上記課題を解決することのでき
る半導体素子の製造方法およびウエハーのダイシング部
構造を提供することを目的とする。
It is an object of the present invention to provide a method of manufacturing a semiconductor device and a wafer dicing structure which can solve the above problems.

【0005】[0005]

【課題を解決するための手段】本件発明方法は、ダイシ
ングによりウエハーを複数の半導体素子に分割する工程
を有する半導体素子の製造方法において、そのウエハー
における半導体素子本体が形成される表面側に、その半
導体素子のパッシベーション膜よりも硬度の小さい部材
をダイシング部に沿って設け、しかる後にそのウエハー
をダイシングすることを特徴とする。そのダイシング部
に沿って設けられる部材を、その半導体素子の電極と同
一の金属材料により同時に形成するのが好ましい。
The method of the present invention is a method of manufacturing a semiconductor device, which comprises a step of dividing a wafer into a plurality of semiconductor devices by dicing, and the semiconductor device body is formed on the front surface side of the wafer. It is characterized in that a member having a hardness smaller than that of the passivation film of the semiconductor element is provided along the dicing portion, and then the wafer is diced. It is preferable that the members provided along the dicing portion are simultaneously formed of the same metal material as the electrodes of the semiconductor element.

【0006】本件発明は、ダイシングにより複数の半導
体素子に分割されるウエハーにおいて、そのウエハーに
おける半導体素子本体が形成される表面側に、その半導
体素子のパッシベーション膜よりも硬度の小さい部材が
ダイシング部に沿って設けられていることを特徴とす
る。
According to the present invention, in a wafer divided into a plurality of semiconductor elements by dicing, a member having a hardness smaller than that of the passivation film of the semiconductor element is formed in the dicing portion on the surface side of the wafer on which the semiconductor element body is formed. It is characterized in that it is provided along.

【0007】[0007]

【本発明の作用および効果】本発明によれば、ウエハー
の表面側に半導体素子のパッシベーション膜よりも硬度
の小さい部材をダイシング部に沿って設けるので、その
部材により、そのウエハーを構成する基板にダイシング
の際に生じる振動を吸収して欠けの発生を抑制できる。
これにより、各半導体素子が欠けにより不良品となるの
が防止され、また、欠けにより寸法精度が低下するのも
防止できる。さらに、そのダイシング部に沿い設けられ
る部材を、その半導体素子の電極と同一の金属材料によ
り同時に形成することで、製造工程が多くなるのを防止
できる。
According to the present invention, since a member having a hardness smaller than that of the passivation film of the semiconductor element is provided along the dicing portion on the front surface side of the wafer, the member constitutes a substrate forming the wafer. Vibration generated during dicing can be absorbed to suppress the occurrence of chipping.
As a result, it is possible to prevent each semiconductor element from being defective due to chipping, and it is also possible to prevent deterioration of dimensional accuracy due to chipping. Further, by simultaneously forming the members provided along the dicing portion with the same metal material as the electrodes of the semiconductor element, it is possible to prevent the number of manufacturing processes from increasing.

【0008】[0008]

【実施例】以下、図面を参照して本発明の実施例を説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0009】図1に示すウエハー1は、1枚のn型Si
基板に複数の半導体発光素子2を作り込むことで製造さ
れたものである。各半導体発光素子2は、図2、図3に
示すように、そのn型Si基板4と、そのウエハー1の
表面側に形成される複数のLED(半導体素子本体)5
と、各LED5に接続される個別電極6と、その基板4
の裏面4bに接続される共通電極7と、各LED5と基
板4の表面4aとを覆うパッシベーション膜9とを有
し、例えばページプリンタの感光ドラムの露光用光源と
して用いられる。
The wafer 1 shown in FIG. 1 has one n-type Si.
It is manufactured by forming a plurality of semiconductor light emitting elements 2 on a substrate. As shown in FIGS. 2 and 3, each semiconductor light emitting element 2 includes an n-type Si substrate 4 and a plurality of LEDs (semiconductor element body) 5 formed on the front surface side of the wafer 1.
An individual electrode 6 connected to each LED 5 and its substrate 4
It has a common electrode 7 connected to the back surface 4b thereof and a passivation film 9 covering each LED 5 and the surface 4a of the substrate 4, and is used as, for example, a light source for exposure of a photosensitive drum of a page printer.

【0010】各LED5は、その基板4の表面4aに半
導体結晶を有機金属気相エピタキシー(MOCVD)や
分子線エピタキシー(MBE)等により成長させ、その
成長層をLED5となる部分を残してエッチングするこ
とで形成できる。例えば、ガリウム砒素(GaAs)、
ガリウム砒素リン(GaAsP)、ガリウムリン(Ga
P)等の成長層であるバッファー層5aと、アルミニウ
ムガリウム砒素(AlGaAs)の成長層であるn形半
導体層5b、p形半導体層5cおよびp+ 形半導体層5
dとで構成できる。そのパッシベーション膜9は、プラ
ズマCVD等により形成される窒化珪素(SiNX )や
酸化珪素(SiO2 )等を成長させることで形成され
る。各個別電極6は、そのパッシベーション膜9の一部
をエッチングにより除去して開口9aを形成することで
前記p+ 型半導体層5dを露出させた後に、そのp+
半導体層5dに接続される金属層を蒸着によって成長さ
せてパターニングすることで形成される。その個別電極
6の材料としては、p+ 型半導体層5dにオーミック接
触する例えば金(Au)が用いられる。各共通電極7
は、蒸着によって成長させた金属層により基板4の裏面
4bを覆うことで形成される。その共通電極7の材料と
しては、基板4にオーミック接触する例えばクロム‐ア
ンチモン‐金(Cr‐Sb‐Au)の3層金属材料が用
いられる。
In each LED 5, a semiconductor crystal is grown on the surface 4a of the substrate 4 by metalorganic vapor phase epitaxy (MOCVD), molecular beam epitaxy (MBE) or the like, and the growth layer is etched leaving a portion to become the LED 5. It can be formed. For example, gallium arsenide (GaAs),
Gallium arsenide phosphide (GaAsP), gallium phosphide (Ga)
Buffer layer 5a which is a growth layer of P) and the like, and n-type semiconductor layer 5b, p-type semiconductor layer 5c and p + -type semiconductor layer 5 which are growth layers of aluminum gallium arsenide (AlGaAs).
and d. The passivation film 9 is formed by growing silicon nitride (SiN x ) or silicon oxide (SiO 2 ) formed by plasma CVD or the like. Each individual electrode 6 is connected to the p + type semiconductor layer 5d after exposing the p + type semiconductor layer 5d by removing a part of the passivation film 9 by etching to form an opening 9a. It is formed by growing a metal layer by vapor deposition and patterning it. As the material of the individual electrode 6, for example, gold (Au) that makes ohmic contact with the p + type semiconductor layer 5d is used. Each common electrode 7
Is formed by covering the back surface 4b of the substrate 4 with a metal layer grown by vapor deposition. As a material of the common electrode 7, a three-layer metal material of, for example, chromium-antimony-gold (Cr-Sb-Au) that makes ohmic contact with the substrate 4 is used.

【0011】そのウエハー1は、高速回転するダイヤモ
ンドブレードにより各半導体発光素子2の間においてダ
イシングされ、そのダイシングにより複数の半導体発光
素子2に分割される。そのウエハー1の表面側のパッシ
ベーション膜9上に、そのパッシベーション膜9よりも
硬度の小さい部材10がダイシング部に沿い設けられて
いる。そのダイシング部に沿い設けられる部材10は、
金属層を蒸着によって成長させてパターニングすること
で形成され、その材料は前記各個別電極6と同一材料と
され、その形成は各個別電極6を形成するための金属層
の蒸着およびパターニングと同時になされる。
The wafer 1 is diced between the semiconductor light emitting elements 2 by a diamond blade that rotates at a high speed, and divided into a plurality of semiconductor light emitting elements 2 by the dicing. On the passivation film 9 on the front surface side of the wafer 1, a member 10 having a hardness lower than that of the passivation film 9 is provided along the dicing portion. The member 10 provided along the dicing part is
It is formed by growing a metal layer by vapor deposition and patterning the same, and its material is the same as that of each individual electrode 6, and its formation is performed simultaneously with vapor deposition and patterning of the metal layer for forming each individual electrode 6. It

【0012】図4は、その分割された半導体発光素子2
のダイシング部の縁2′を示し、従来に比べ欠けの発生
が抑制されている。
FIG. 4 shows the divided semiconductor light emitting device 2
The edge 2'of the dicing part is shown, and the occurrence of chipping is suppressed as compared with the conventional case.

【0013】上記構成によれば、ウエハー1の表面側
に、各半導体発光素子2のパッシベーション膜9よりも
硬度の小さい金属部材10をダイシング部に沿って設け
るので、その金属部材10により、そのウエハー1をダ
イシングする際に基板4に生じる振動を吸収して欠けの
発生を抑制できる。これにより、各半導体発光素子2が
欠けにより不良品となるのが防止され、また、欠けによ
り寸法精度が低下するのも防止できる。さらに、そのダ
イシング部に沿い設けられる金属部材10を、各LED
5に接続される個別電極6と同一の金属材料により同時
に形成することで、製造工程が多くなるのを防止でき
る。
According to the above structure, since the metal member 10 having a hardness smaller than that of the passivation film 9 of each semiconductor light emitting element 2 is provided along the dicing portion on the front surface side of the wafer 1, the metal member 10 allows the wafer to be formed. It is possible to absorb the vibration generated in the substrate 4 when dicing 1 and suppress the occurrence of chipping. As a result, it is possible to prevent each semiconductor light emitting element 2 from being defective due to chipping, and it is also possible to prevent deterioration in dimensional accuracy due to chipping. Further, the metal member 10 provided along the dicing part is attached to each LED.
By simultaneously forming the individual electrodes 6 connected to 5 with the same metal material, it is possible to prevent the number of manufacturing processes from increasing.

【0014】なお、本発明は上記実施例に限定されるも
のではない。例えば、図5の変形例に示すように、パッ
シベーション膜9をエッチングにより除去してp+ 型半
導体層5dを露出させる開口9aを形成する際に、同時
にダイシング部に沿ってエッチングして溝11を形成
し、その溝11内にパッシベーション膜よりも硬度の小
さい部材10を設けてもよい。また、ダイシング部に沿
って設ける部材は、パッシベーション膜よりも硬度が小
さければ流動的なものを除いては特にAuに限定され
ず、例えば銀(Ag)、アルミニウム(Al)、チタン
(Ti)等であってもよく、また、金属である必要はな
く例えば樹脂であってもよい。また、基板の材料はダイ
シング部に沿って設ける部材よりも硬度が大きければ特
にSiに限定されず、例えばGaAs、GaP、アルミ
ナ(Al2 3 )等でもよい。さらに、その基板に作り
込まれる半導体素子であれば本発明を適用できるので半
導体発光素子に限定されない。
The present invention is not limited to the above embodiment. For example, as shown in the modified example of FIG. 5, when the passivation film 9 is removed by etching to form the opening 9a exposing the p + type semiconductor layer 5d, at the same time, the groove 11 is etched along the dicing portion. The member 10 having a hardness smaller than that of the passivation film may be provided in the groove 11 formed. Further, the members provided along the dicing portion are not particularly limited to Au except those which are fluid as long as the hardness is smaller than that of the passivation film, and for example, silver (Ag), aluminum (Al), titanium (Ti), etc. May be used, and need not be metal, and may be resin, for example. The material of the substrate is not particularly limited to Si as long as it has a hardness higher than that of the member provided along the dicing portion, and may be GaAs, GaP, alumina (Al 2 O 3 ) or the like. Further, the present invention can be applied to any semiconductor device built into the substrate, and is not limited to the semiconductor light emitting device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例のウエハーの平面図FIG. 1 is a plan view of a wafer according to an embodiment of the present invention.

【図2】そのウエハーの部分拡大平面図FIG. 2 is a partially enlarged plan view of the wafer.

【図3】そのウエハーの部分拡大断面図FIG. 3 is a partially enlarged sectional view of the wafer.

【図4】本発明の実施例のダイシング部の切り口の状態
を示す拡大平面図
FIG. 4 is an enlarged plan view showing a state of a cut end of a dicing portion according to an embodiment of the present invention.

【図5】本発明の変形例のウエハーの部分拡大断面図FIG. 5 is a partially enlarged sectional view of a wafer according to a modified example of the present invention.

【図6】従来例のウエハーの部分拡大断面図FIG. 6 is a partially enlarged sectional view of a conventional wafer.

【図7】従来例のダイシング部の(1)は切り口の状態
を示す拡大平面図、(2)は欠けの発生状態を示す拡大
平面図
7A and 7B are enlarged plan views showing a state of a cut, and FIG. 7B is an enlarged plan view showing a state where a chip is generated.

【符号の説明】[Explanation of symbols]

1 ウエハー 2 半導体発光素子 4 基板 5 LED(半導体素子本体) 6 個別電極 9 パッシベーション膜 1 Wafer 2 Semiconductor Light-Emitting Element 4 Substrate 5 LED (Semiconductor Element Main Body) 6 Individual Electrode 9 Passivation Film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 ダイシングによりウエハーを複数の半導
体素子に分割する工程を有する半導体素子の製造方法に
おいて、そのウエハーにおける半導体素子本体が形成さ
れる表面側に、その半導体素子のパッシベーション膜よ
りも硬度の小さい部材をダイシング部に沿って設け、し
かる後にそのウエハーをダイシングすることを特徴とす
る半導体素子の製造方法。
1. A method of manufacturing a semiconductor element, which comprises a step of dividing a wafer into a plurality of semiconductor elements by dicing, wherein a hardness of a semiconductor element main body formed on the surface of the wafer is higher than that of a passivation film of the semiconductor element. A method of manufacturing a semiconductor device, characterized in that a small member is provided along a dicing portion, and then the wafer is diced.
【請求項2】 そのダイシング部に沿って設けられる部
材を、その半導体素子の電極と同一の金属材料により同
時に形成することを特徴とする請求項2に記載の半導体
素子の製造方法。
2. The method of manufacturing a semiconductor element according to claim 2, wherein the members provided along the dicing portion are simultaneously formed of the same metal material as the electrodes of the semiconductor element.
【請求項3】 ダイシングにより複数の半導体素子に分
割されるウエハーにおいて、そのウエハーにおける半導
体素子本体が形成される表面側に、その半導体素子のパ
ッシベーション膜よりも硬度の小さい部材がダイシング
部に沿って設けられていることを特徴とするウエハーの
ダイシング部構造。
3. In a wafer divided into a plurality of semiconductor elements by dicing, a member having a hardness smaller than that of a passivation film of the semiconductor element is provided along a dicing portion on the surface side of the wafer on which the semiconductor element body is formed. A wafer dicing unit structure characterized by being provided.
JP26174894A 1994-09-30 1994-09-30 Manufacture of semiconductor element and structure of wafer dicing part Pending JPH08102453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26174894A JPH08102453A (en) 1994-09-30 1994-09-30 Manufacture of semiconductor element and structure of wafer dicing part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26174894A JPH08102453A (en) 1994-09-30 1994-09-30 Manufacture of semiconductor element and structure of wafer dicing part

Publications (1)

Publication Number Publication Date
JPH08102453A true JPH08102453A (en) 1996-04-16

Family

ID=17366167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26174894A Pending JPH08102453A (en) 1994-09-30 1994-09-30 Manufacture of semiconductor element and structure of wafer dicing part

Country Status (1)

Country Link
JP (1) JPH08102453A (en)

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