JPH0685319A - Manufacture of light emitting diode array chip - Google Patents

Abstract

PURPOSE:To provide a light emitting diode array chip capable of high-density integration of light emitting elements without light emitting property dropping even in an endmost light emitting part by suppressing the separation of an insulating film at dicing. CONSTITUTION:An insulating film 12, which has a projection 12 extending outward of a chip in the vicinity of an endmost light emitting part 23, is made on an epitaxial wafer where an epitaxial layer is grown on a substrate 1. A p-type region to serve as a light emitting part is formed by diffusing p-type impurities into the epitaxial layer through the window of the insulating film 12. The projection is diced precedently in the opposite direction, and then it is diced into individual chips. Hereby, the force of seeking to strip off the insulating film 12 by precedent dicing becomes residual stress, and lightens the reverse force of seeking to strip off the insulating film 12 generated at dicing of a chip. Therefore, in individual chips being cut out, the separation of the insulating film 12 is restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a high resolution light emitting diode array chip used for an LED plotter or the like.

[0002]

2. Description of the Related Art An electrophotographic plotter uses, as a light source, a light emitting diode array having a plurality of light emitting elements formed on a substrate at a constant pitch. A conventional light emitting diode array chip has a substrate 1 as shown in FIG.
An epitaxial wafer 10 having an n-type GaAsP epitaxial layer 11b grown on the surface 1a is used. A p-type semiconductor region is formed on the epitaxial layer 11b by a thermal diffusion method using the insulating film 12 as a selective diffusion mask to form a light emitting portion 13. After the electrode portion 14 is provided on each light emitting portion 13, the epitaxial wafer 10 is cut into each chip by dicing.

A typical light emitting diode array has a resolution of 2
Light emitting diode 64-2 of 00-400 dots / inch
56 pieces are integrated in one chip. Recently, in order to improve print quality, a light emitting diode array having further improved resolution is required. From this point, there is a need for a technique capable of manufacturing a light emitting diode having a high resolution of 400 dots / inch or more with a high yield.

[0004]

In the light emitting diode having a high resolution of 400 dots / inch or more manufactured by the conventional method, the light emitting output is remarkably lowered at the light emitting portion at the end of the array as shown in FIG. 2 (a). Seen. In this regard, in a light emitting diode having a low resolution of less than 400 dots / inch, which has a relatively large distance between adjacent light emitting portions,
As shown in (b), the individual light emitting units do not decrease at the end of the array, and all the light emitting units have the same light emission output.

The emission output characteristic of the light emitting portion at the end of the array is shown in FIG.
If the light emitting diode array chip, which has deteriorated as shown in (a), is used in a printer or the like, it causes deterioration of print quality. The decrease in the light emission output at the light emitting portion at the end of the array becomes more remarkable as a large number of light emitting portions are arranged at a small pitch in order to improve the resolution. Therefore, the defective product generation rate is high, which causes an increase in the production cost of the light emitting diode array chip. The decrease in the light emission output at the light emitting portion at the end of the array results in formation of a p-type semiconductor region at the outer peripheral edge of the chip, and this p-type semiconductor region is conducted to the substrate 11a via a crystal defect portion introduced into the chip end face during dicing. It is presumed that there is a cause. The present inventors, as shown in FIG.
Japanese Patent Application No. 4-1016 using an insulating film 12 having
Proposed in No. 53. This insulating film 12 prevents the formation of the p-type semiconductor region at the outer peripheral edge of the chip, and produces a light emitting diode array in which the emission output characteristics of the light emitting portion at the end of the array are not deteriorated.

However, when the light emitting diode array chip provided with the insulating film 12 having the overhanging portion 21 is cut out from the epitaxial wafer 10 as individual chips,
The peeling of the insulating film 12 starting from the overhanging portion 21 occurs frequently. When the peeling of the insulating film 12 reaches the outermost light emitting portion 23, the junction interface of the diffusion region is exposed, and the reliability as a light emitting diode decreases. In addition, the emission shape may change due to the peeling of the insulating film 12, and the resolution as a printer decreases. The present invention has been devised to solve such a problem, and by performing dicing on the overhanging portion of the insulating film in advance, peeling of the insulating film, which causes exposure of the light emitting portion, is prevented, and the array end portion is prevented. It is an object of the present invention to manufacture a light emitting diode array chip that does not cause a decrease in light emission output at high yield.

[0007]

In order to achieve the object, the method of manufacturing a light-emitting diode array chip of the present invention provides an insulating film having an overhanging portion directed to the outside of the chip in the vicinity of the most end light-emitting portion in the chip end face direction. After forming on the mold substrate and diffusing p-type impurities from the window provided in the insulating film to form the light emitting portion, the substrate is diced and cut into individual light emitting diode array chips. It is characterized in that the overhang portion is subjected to preceding dicing in a direction opposite to the dicing direction of the chip.

[0008]

[Operation] When the light emitting diode array chip is cut out by normal dicing, the dicing blade 22 rotating at high speed is brought into contact with the wafer as shown in FIG.
Grind the outer periphery of the chip. At this time, the protruding portion 21 of the insulating film 12 is also cut at the same time. As a result, due to the rotational force of the dicing blade 22, a force to peel off the insulating film 12 is generated in the rotating / advancing direction of the dicing blade 22. When the peeling force exceeds the adhesion of the insulating film 12 to the wafer, the insulating film 12 peels off. Therefore, in the present invention, prior to dicing the chip, the overhanging portion 21 is subjected to preceding dicing in the direction opposite to the dicing direction of the chip. The force for peeling off the insulating film 12 remains as residual stress due to the preceding dicing. When the chip is diced in this state, the force for peeling the insulating film 12 is relaxed by the residual stress introduced by the preceding dicing. Therefore, the effective peeling force acting on the insulating film 12 becomes small, and it becomes possible to perform dicing into individual chips without peeling off the insulating film 12.

[0009]

EXAMPLES Example 1: Epitaxial layer 1 on substrate 11a
Silicon nitride to be the insulating film 12 was formed by plasma CVD on the epitaxial wafer 10 on which 1b was grown, and then the light emitting portion 13 and the chip outer peripheral portion 15 were formed by a conventional method. In order to obtain a light-emitting diode array chip with a resolution of 400 dots / inch, one light-emitting unit 13 is provided on each side 3
The square shape was set to 0 μm, and the pitch between adjacent light emitting portions 13 was set to 63.5 μm. Further, as the chip, a rectangular piece cut out from the epitaxial wafer 10 and having a length of 8 mm and a width of 0.5 mm was used. When the insulating film 12 is formed, the overhanging portion 21 extending to the outside of the chip is attached to the end light emitting portion 23.
It was provided on the insulating film 12 in the vicinity. After forming the electrode portion 14 on each light emitting portion 13 including the endmost light emitting portion 23, the wafer 10 was cut into individual chips by dicing. For the dicing, the conventional method of directly dicing the chip and the method of the present invention in which the dicing of the chip is performed after the preceding dicing of the overhanging portion 21 are adopted. The preceding dicing was performed in the direction shown in FIG. 5A, and the chip dicing was performed in the direction shown in FIG.

The state of occurrence of peeling of the insulating film was investigated for each of the diced chips. For the peeling of the insulating film, the state of peeling of the insulating film is investigated by observing using a metallurgical microscope.
When the peeling of the insulating film was within 5 μm from the outermost light emitting portion, it was determined as a defective product, and the occurrence rate of defective products in the total number of diced chips was determined. As is clear from Table 1 showing the survey results, the insulating film peeling rate of the conventional method is 27-
Although it was as high as 42%, it was a very low incidence of 1-3% in the method of the present invention. From this, it is understood that the residual stress introduced into the chip by the preceding dicing effectively acts to prevent the peeling of the insulating film during dicing of the chip.

[0011]

[Table 1]

Example 2: Overhang 2 extending outside the chip
The light emitting diode array chip in which the connecting portion 24 is formed between the insulating films 12 adjacent to each other by 1 was diced in the same manner as in Example 1. The dicing according to the present invention was performed by performing the preceding dicing in the direction shown in FIG. 6A and dicing the chip in the direction shown in FIG. 6B. The peeling condition of the insulating film 12 was investigated for each of the diced chips. As is clear from Table 2 showing the investigation results, the incidence rate of the insulating film peeling is as high as 22 to 44% in the conventional method, but 0 to 4% of the chips diced by the method of the present invention have the insulating film peeled. And is very low. Also in this case, the effect of the preceding dicing was confirmed as in Example 1.

[0013]

[Table 2]

[0014]

As described above, in the present invention, the chip is diced after the protruding portion of the insulating film is cut by the preceding dicing in the opposite direction. The force for peeling off the insulating film by the preceding dicing remains in the insulating film as residual stress, and the force in the opposite direction for peeling off the insulating film generated during dicing of the chip is relaxed. As a result, the insulating film is in good contact with the substrate,
The outermost light emitting portion is not exposed due to the peeling of the insulating film. Therefore, even in a high-resolution light-emitting diode array chip in which light-emitting portions are arranged at a fine pitch of 400 dots / inch or more, the light-emission output characteristics at the endmost light-emitting portion of the array are not deteriorated, and a high-performance light-emitting diode array chip is obtained. Can be manufactured with a high yield.

[Brief description of drawings]

FIG. 1 is a plan view (a) and a sectional view (b) of a conventional light emitting diode array chip.

FIG. 2 Light emission output characteristics of a conventional light emitting diode array chip

FIG. 3 is a light-emitting diode array chip using an insulating film having a protruding portion.

FIG. 4 Conventional dicing method

FIG. 5: Preceding dicing (a) and chip dicing (b) in Example 1 of the present invention.

FIG. 6 shows the preceding dicing (a) and the chip dicing (b) in the second embodiment of the present invention.

[Explanation of symbols]

10 Epitaxial Wafer 11a Substrate 11b Epitaxial Layer 12 Insulating Film
13 Light emitting part 14 Electrode 15 Chip outer peripheral part 21 Overhanging part of edge film 22 Dicing blade 23 Endmost light emitting part 24 Overhanging connecting part

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location B43L 13/00 J 8705-2C H01L 21/78 L 8617-4M Q 8617-4M

Claims (1)

[Claims] 1. An insulating film having an overhanging portion facing the outside of the chip in the vicinity of the most end light emitting portion in the chip end face direction is formed on an n-type substrate, and p-type impurities are diffused from a window provided in the insulating film. After forming the light emitting portion by dicing, the substrate is diced to cut into individual light emitting diode array chips, the protruding portion of the insulating film is pre-diced in a direction opposite to the dicing direction of the chip. Chip manufacturing method.