JP4026998B2 - LED array and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an LED array suitable for a writing light source such as an electrostatic exposure printer, and a manufacturing method thereof.
[0002]
[Prior art]
In an LED array that can be used as a light source for writing such as an electrostatic exposure printer, for example, an LED printer, a compound semiconductor substrate is formed by growing an n-type GaAsP layer on an upper surface of a substrate such as n-type GaAs. The p layer is formed by selectively diffusing p-type impurities such as Zn into the p-type GaAsP layer through a diffusion mask (see Japanese Utility Model Publication No. 3-19236).
[0003]
The film used as the diffusion mask is required to have a high impurity diffusion preventing ability and good workability, and a SiN film, a SiO ₂ film or the like is generally used. However, these films have a large true stress (intrinsic stress) of about 10 ⁹ Pa, and are easily distorted in the PN junction due to a difference in thermal expansion coefficient from the substrate. And this distortion has become one factor of deterioration of energization. In particular, as the resolution of the printer is increased and the current density is increased, the rate at which energization deterioration occurs at a specific point in a part of the LED array increases, resulting in a problem that the print quality is remarkably lowered.
[0004]
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to provide an LED array that can cope with higher resolution and higher speed of a printer.
[0005]
[Means for Solving the Problems]
The LED array of the present invention, as described in claim 1, in the LED array comprising a plurality of light emitting portions formed by PN junction on one surface of the semiconductor substrate, a first film for a diffusion mask on one surface of the substrate, a second coating was laminated to the first coating, the first coating, the than the second film is a true stress coating small alumina, the second coating the first coating It is characterized by being a silicon nitride thin film thinner than this film thickness.
[0006]
According to a second aspect of the present invention, there is provided an LED array manufacturing method comprising: forming a first film made of alumina on one surface of a semiconductor substrate; and forming the first film made of a silicon nitride thin film on the first film. A step of forming a second film for a mask of the first film, a step of selectively opening an etching hole only in the second film, and diffusion in the first film through the etching hole And a step of diffusing impurities into the semiconductor substrate through the diffusion hole, the first film is a film having a smaller true stress than the second film, The second film is formed thinner than the film thickness of the first film .
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to cross-sectional views of FIGS.
[0012]
First, as a first step, as shown in FIG. 1A, a compound semiconductor substrate 3 having an n-type GaAsP layer 2 grown on an n-type GaAs substrate 1 is prepared. Usually, the substrate 3 is prepared in a wafer state having a thickness of 400 to 600 μm and a diameter of several inches.
[0013]
As the next step, as shown in FIG. 1B, a first film 4 is formed on one surface of the substrate 3, in this example, the n-type GaAsP layer 2, and a second film 5 is formed thereon. . The first coating 4 is used as a mask for diffusing impurities in the n-type GaAsP layer 2, and has the same thermal expansion coefficient as that of the substrate 3 and an alumina (Al ₂ O ₃ ) (true stress is about 10 ⁸ Pa).
[0014]
Here, true stress refers to the stress generated during film formation among the stress remaining in the film (generally divided into tensile stress and compressive stress), and is distinguished from thermal stress generated after film formation. Is done. Moreover, since the true stress is not an absolute value, the true stress described in this specification indicates a measurement result under conditions other than the type of film, for example, a common condition in which the thickness and shape are unified. .
[0015]
The first coating 4 is optically transparent with respect to the emission wavelength (600 to 800 nm), and is formed to a thickness of about 0.1 to 0.15 μm by using a sputtering method or an ion plating method. Is done. The second film 5 is used as a mask for forming a diffusion hole in the first film 4, has good adhesion to the first film 4, and is etched by the etching material of the first film 4. For example, a silicon nitride (SiN) thin film, a silicon oxide (SiO ₂ ) thin film, a phosphide glass (PSG) thin film, or the like is selectively used. The second coating 5 is optically transparent with respect to the emission wavelength (600 to 800 nm), and is thinner than the first coating 4 by using a sputtering method or an ion plating method. The film is formed to a thickness of about 05 μm. The second film 5 is conventionally disposed at the position of the first film 4 as a diffusion mask, but the true stress is about 10 ⁹ Pa, which is larger than the true stress 10 ⁸ Pa of the first film 4. Therefore, stress strain was easily applied to the substrate 3. However, since the first film 4 is disposed under the second film 5, stress strain applied to the substrate 3 can be reduced.
[0016]
As the next step, as shown in FIG. 1 (c), a resist pattern 7 having a hole pattern 6 corresponding to the planar shape of the light emitting portion is formed on the laminated first and second films 4 and 5. Form. The resist pattern 7 is formed by exposing a pattern corresponding to the planar shape of the light emitting portion to the resist film using a photolithography technique and developing the resist film.
[0017]
As the next step, as shown in FIG. 1 (d), the second coating 5 is etched. Etching of the second film 5 is performed by dry etching using an etchant having selectivity with respect to the second film, in this example, CF4 (Freon) gas as an etchant. By this etching process, a plurality of holes 8 for etching are formed in the second film 5. At this time, since the alumina formed as the first coating 4 is not dry-etched, only the second coating 5 is selectively etched.
[0018]
As the next step, as shown in FIG. 1E, the first coating 4 is etched. This etching is performed by wet etching using the second film 5 as a mask and an etchant having selectivity for the first film 4, in this example, hot phosphoric acid as an etchant. By this etching, a plurality of holes 9 for diffusion are formed in the first coating 4. At this time, since the n-type GaAsP layer 2 and the second coating 5 are not wet-etched or are very small, only the first coating 4 is selectively etched.
[0019]
Here, if there is no 2nd film 5, the adhesiveness of the 1st film 4 and the resist pattern 7 is bad, and the side etching of the 1st film 4 advances from the boundary part. By this side etching, it becomes difficult to finely process the first coating 4, and patterning corresponding to high resolution cannot be performed. On the other hand, in the present invention, the second coating 5 having excellent adhesion to the coating is formed on the first coating 4, and the etching of the first coating 4 is performed using the second coating 5 as a mask. Therefore, the side etching can be prevented from occurring, and the fine workability of the first coating 4 can be improved.
[0020]
As the next step, impurity diffusion is performed as shown in FIG. The resist pattern 7 is removed before or after the impurity diffusion treatment. In the impurity diffusion treatment, an impurity such as a p-type impurity such as Zn is selectively applied to the n-type GaAsP layer 2 from above the first and second films 4 and 5 by using thermal diffusion or ion implantation. This is performed by diffusing, whereby the P layer 10 is formed. A PN junction is formed along the boundary between the P layer 10 and the surrounding N layer, and this PN junction portion becomes the LED light emitting unit 11.
[0021]
As the next step, as shown in FIG. 1G, a P-type electrode (for example, aluminum) 12 connected to the P layer 10 and an N-type electrode (for example, gold) 13 connected to the back surface of the substrate 1 are formed in a predetermined shape. To form.
[0022]
Through these processing steps, a wafer-like substrate having a plurality of LED arrays is manufactured.
[0023]
Next, the wafer-like substrate on which the electrodes are formed is divided into individual chip-like LED arrays using a scribing device or a dicing device. The divided chip is an LED array having a strip shape with a short side length of about 1 mm and a long side length of several mm.
[0024]
FIG. 2A shows a cross-sectional view of the LED array 14 along the short direction, and FIG. 2B shows a partial cross-sectional view in the longitudinal direction.
[0025]
As described above, the LED array 14 has the laminated structure of the first and second coatings 4 and 5 for the mask on one surface of the substrate 3, so that the side etching of the first coating 4 progresses in the first direction. It can be suppressed by the second coating 5. As a result, fine processing corresponding to high resolution can be performed, and high resolution higher than 400 DPI (dot / inch) can be easily handled.
[0026]
Further, since the first coating 4 uses a coating having a smaller true stress than the silicon coating (SiN or SiO 2) used for the second coating 5, the strain applied to the substrate 3, particularly the layer 2. Can be reduced. Further, since the first coating 4 uses a coating having a smaller difference in thermal expansion coefficient from the substrate 3 than the silicon-based coating (SiN or SiO2) used for the second coating 5, the substrate 3, in particular, the strain applied to the layer 2 can be reduced.
[0027]
Further, by using a composite film including the first and second different films 4 and 5 as the diffusion mask, the alteration of the films 4 and 5 at the time of forming the P layer can be suppressed. As a result, it is possible to suppress the dielectric breakdown voltage degradation of the films 4 and 5 due to the wire bonding impact on the P-type electrode 12 and to suppress the occurrence of cracks in the films 4 and 5, thereby causing problems in the wire bonding operation. Can be suppressed.
[0028]
In the above embodiment, the example in which alumina is used as the first coating 4 has been shown. However, the present invention is not limited to this, and aluminum nitride (AlN) or its oxide (AlON) is used instead of alumina. Can also be used. However, it is preferable to use alumina because aluminum nitride and its oxide have poor etching processability compared to alumina. In the above embodiment, the case where GaAsP / GaAs is used as the substrate 3 is shown. However, the present invention is not limited to this, and an AlGaAs / GaAs, GaAs / GaAs or similar semiconductor substrate is used as the substrate 3. It can be applied to the case of using as.
[0029]
Moreover, in the said Example, PN polarity can also be reversed.
[0030]
【The invention's effect】
As described above, according to the present invention, an LED array corresponding to high resolution can be provided. Moreover, the LED array which reduced generation | occurrence | production of electricity supply degradation can be provided. Further, it is possible to provide an LED array that is hardly affected by wire bonding.
[Brief description of the drawings]
FIGS. 1A to 1G are cross-sectional views showing a manufacturing process of an LED array of the present invention.
FIGS. 2A and 2B are cross-sectional views of the LED array of the present invention, in which FIG.
[Explanation of symbols]
3 Substrate 4 First coating 5 Second coating 7 Resist pattern 10 P layer 11 LED light emitting unit 14 LED array

Claims (2)

In an LED array having a plurality of light emitting portions formed by PN junction on one surface of a semiconductor substrate, a first coating for a diffusion mask and a second coating laminated on the first coating are provided on one surface of the substrate, The first coating is an alumina coating having a true stress smaller than that of the second coating, and the second coating is a silicon nitride thin film having a thickness smaller than that of the first coating. LED array. Forming a first film made of alumina on one surface of a semiconductor substrate; forming a second film for masking the first film made of a silicon nitride thin film on the first film; A step of selectively opening an etching hole only in the second coating; a step of opening a diffusion hole in the first coating through the etching hole; and a semiconductor substrate through the diffusion hole. A step of diffusing impurities, wherein the first coating is a coating having a true stress smaller than that of the second coating, and the second coating is formed thinner than the thickness of the first coating. A method for manufacturing an LED array .

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