JP3421523B2 - Wafer splitting method - Google Patents

Wafer splitting method

Info

Publication number
JP3421523B2
JP3421523B2 JP1684197A JP1684197A JP3421523B2 JP 3421523 B2 JP3421523 B2 JP 3421523B2 JP 1684197 A JP1684197 A JP 1684197A JP 1684197 A JP1684197 A JP 1684197A JP 3421523 B2 JP3421523 B2 JP 3421523B2
Authority
JP
Japan
Prior art keywords
wafer
groove
scribe
substrate
gallium nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1684197A
Other languages
Japanese (ja)
Other versions
JPH10214997A (en
Inventor
隆稔 薮内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tottori Sanyo Electric Co Ltd
Priority to JP1684197A priority Critical patent/JP3421523B2/en
Publication of JPH10214997A publication Critical patent/JPH10214997A/en
Application granted granted Critical
Publication of JP3421523B2 publication Critical patent/JP3421523B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は窒化ガリウム系半導
体発光ダイオードに好適なウエハーの分割方法に関す
る。 【0002】 【従来の技術】従来より半導体素子は、ウエハーの状態
で半導体層を積層し、その後スクライブ法とかダイシン
グ法などによってウエハーをいわゆるチップ(個別素
子)の状態に分割していた。ところが単波長の発光ダイ
オードなどにおいては直接同じ結晶系の半導体層を同一
結晶系の基板に積層するのではなく、異なる結晶系の基
板に半導体層を積層している。例えば紫、青乃至は緑の
発光ダイオードを窒化ガリウム系の結晶で得る場合、窒
化ガリウム系半導体層をサファイア基板上に積層させて
おり、このような場合、サファイア基板は六方晶系であ
って劈開性をもっていない。 【0003】 【発明が解決しようとする課題】このような結晶系の異
なる基板に半導体層を成長させた場合、このウエハーを
分割する場合には、特開平5−315646号公報など
に示されるように、ダイシング法で切断しても、スクラ
イブ法で割っても、そのままでは切断面のクラックやチ
ッピングが発生しやすく、チップの形状もいびつになり
易い。特に半導体層が発光ダイオードである場合には、
漏れ電流の発生などによる発光効率の低下を生じたり、
発光層の変形により光の放出分布がいびつになることな
ど、不都合であった。 【0004】 【課題を解決するための手段】本発明は、このような点
を考慮して、とりわけ素子分割の初期作業において直交
する二つの線引きが交点で素子分割を疎外していること
に着目して成されたものである。 【0005】 【0006】本発明は、基板上にその基板と異なる結晶
系の窒化ガリウム系半導体が積層されたウエハーを分割
する方法において、前記窒化ガリウム系半導体の積層側
から第1の方向にスクライブまたは溝形成を行った後、
その第1の方向に直交する第2の方向に第1のスクライ
ブ線または溝を確実に横断する該スクライブ線または溝
よりも幅広で深さの深い溝を形成した後、ウエハーを分
割するものである。 【0007】 【発明の実施の形態】図1は、本発明の第1の実施例に
用いる窒化ガリウム系半導体が積層されたウエハーの斜
視図で、1は厚さ100〜500μmのサファイア基板
1である。このサファイア基板1の表面に、n型Gaa
Al1-aN(0≦a≦1)バッファー層2、n型Gab
1-bN(0≦b≦1)クラッド層3、i型GaxAl
1-xN(0≦x≦1)発光層4、p型GacAl1-c
(0≦c≦1)クラッド層5、キャップ層6が順次積層
され、更に電極7、8が設けられている。係る半導体層
は高々十数μmである。 【0008】このようなウエハーにおいて、積層された
半導体層側から、第1の方向にスクライブが行われてい
る。スクライブとは、ダイヤモンド針などによりケガキ
線を入れることである。次いでその第1の方向と直交す
る第2の方向にスクライブを行う。このようにして設け
られた第1、第2のスクライブ線11、12は、浅いも
のであるが、この状態では、概ね後にスクライブした方
のスクライブ線12が先に設けたスクライブ線11によ
って針飛びによる途切れを生じるか、または先に設けた
スクライブ線11が後で行うスクライブにより引っ張ら
れ、交点部分で半導体被膜などがめくれ上がったように
なっている。そこでレーザービームなどにより、スクラ
イブ線11、12の交点にサファイア基板1を略貫通す
る孔13を設ける。その後サファイア基板1側(裏面)
からローラーなどで加圧して、ウエハーを分割する。こ
のようにすることで、例えば交点に孔を設けない場合に
35%程度のチッピングが生じていたが、15%程度に
減少した。 【0009】係る分割は、クラックやチッピングが、例
えばチップの右肩に突出する様な形で発生するウエハー
では、他の形状の割れ方が少ないというように、ウエハ
ー内でチップの角にほぼ同じ傾向で発生していることか
ら、スクライブ等の仕方によって、いわゆる割れ易い
(欠け易い)方向性があるものと考えて成されたもので
ある。そして、上述した分割方法は、サファイア基板が
100〜300μmと比較的薄い場合に好適である。サ
ファイア基板が厚い場合にはダイシング法にしたがっ
て、スクライブ線11、12に変わる溝を設けるのがよ
く、ウエハーの表面からと裏面からでスクライブ線とダ
イシングによる溝を使い分けてもよい。このような方法
により、交点を改めて分割し易くすることで歩留まりが
上がったが、交点に設ける溝や孔は、分離のために設け
たスクライブ線やダイシング溝よりも深いほうが好まし
い結果が得られた。また交点においては、レーザー加工
器でなくともキリのようなもので孔や溝を設けてもよ
い。溝を設ける場合には、溝そのものは浅くとも、サフ
ァイヤ基板側から十文字の溝を形成するのが最も好まし
かった。 【0010】図2は本発明の他の実施例を示すウエハー
の斜視図で、ウエハーの各層は第1図のものと同じ、基
板上にその基板と異なる結晶系の窒化ガリウム系半導体
が積層されたウエハーを例示してある。この例におい
て、第1の方向にエッチングやダイシングにより溝14
の形成を行った後、その第1の方向の溝14に直交する
第2の方向に第1の溝14を、別の幅の広い鋭利なダイ
シングブレードにより、図2に示すように確実に横断す
る第1の溝14よりも幅広で深さの深い溝15を形成し
た後、ウエハーを分割する様子を示している。この方法
も先の例と同様に、溝14、15の交点で基板1などに
特異な割れやすい方向が生じるのを防ぎ、交点で所望の
方向に割れるようにしたものである。この場合もサファ
イア基板1が薄いときには溝14、15に変わってスク
ライブ線でもよいが、後の溝を設けるときにスクライブ
線によって半導体薄膜が剥離しないように留意を要す
る。 【0011】 【発明の効果】以上の如くにより、ケガキや溝切りによ
る交点での特異な割れやすい方向が生じるのを防ぐこと
ができたので、不所望のチッピングなどは生じないし、
溝の中でチッピングなどが生じても発光特性に悪影響を
及ぼすことはなかった。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dividing a wafer suitable for a gallium nitride semiconductor light emitting diode. 2. Description of the Related Art Conventionally, semiconductor elements have been formed by laminating semiconductor layers in a wafer state, and thereafter dividing the wafer into so-called chips (individual elements) by a scribe method or a dicing method. However, in a single-wavelength light emitting diode or the like, a semiconductor layer of the same crystal system is not directly stacked on a substrate of the same crystal system, but semiconductor layers are stacked on substrates of different crystal systems. For example, when a violet, blue or green light-emitting diode is obtained with a gallium nitride-based crystal, a gallium nitride-based semiconductor layer is laminated on a sapphire substrate. In such a case, the sapphire substrate is hexagonal and is cleaved. Have no sex. [0003] When a semiconductor layer is grown on a substrate having such a different crystal system, and when the wafer is divided, as disclosed in Japanese Patent Application Laid-Open No. Hei 5-315646, for example. In addition, even if it is cut by the dicing method or split by the scribe method, cracks and chipping of the cut surface are liable to occur as it is, and the shape of the chip tends to be distorted. Especially when the semiconductor layer is a light emitting diode,
Luminous efficiency may be reduced due to leakage current, etc.
This is disadvantageous, for example, in that the light emission distribution becomes irregular due to deformation of the light emitting layer. [0004] In view of the above, the present invention pays particular attention to the fact that in the initial operation of element division, two orthogonal lines draw the element division at the intersection. It was made. According to the present invention, there is provided a method of dividing a wafer in which a crystalline gallium nitride based semiconductor different from the substrate is laminated on the substrate, wherein the scribing is performed in a first direction from the lamination side of the gallium nitride based semiconductor. Or after forming the groove,
After forming a groove wider and deeper than the scribe line or groove that surely crosses the first scribe line or groove in a second direction orthogonal to the first direction, the wafer is divided. is there. FIG. 1 is a perspective view of a wafer on which a gallium nitride based semiconductor used in a first embodiment of the present invention is laminated, and 1 is a sapphire substrate 1 having a thickness of 100 to 500 μm. is there. On the surface of the sapphire substrate 1, n-type Ga a
Al 1-a N (0 ≦ a ≦ 1) buffer layer 2, n-type Ga b A
l 1-b N (0 ≦ b ≦ 1) cladding layer 3, i-type Ga x Al
1-x N (0 ≦ x ≦ 1) light emitting layer 4, p-type Ga c Al 1-c N
(0 ≦ c ≦ 1) A clad layer 5 and a cap layer 6 are sequentially laminated, and electrodes 7 and 8 are further provided. Such a semiconductor layer is at most dozens of micrometers. In such a wafer, scribing is performed in the first direction from the side of the stacked semiconductor layers. Scribing is to insert a marking line with a diamond needle or the like. Next, scribing is performed in a second direction orthogonal to the first direction. Although the first and second scribe lines 11 and 12 provided in this manner are shallow, in this state, the scribe line 12 which has been scribed later is generally a needle jump by the scribe line 11 provided earlier. Or the scribe line 11 provided earlier is pulled by the scribe performed later, and the semiconductor film or the like is turned up at the intersection. Therefore, a hole 13 is formed through the sapphire substrate 1 at the intersection of the scribe lines 11 and 12 with a laser beam or the like. Then the sapphire substrate 1 side (back side)
Then, the wafer is divided by pressing with a roller or the like. By doing so, for example, when no hole was provided at the intersection, chipping of about 35% occurred, but it was reduced to about 15%. [0009] Such division is substantially the same as the corner of the chip in the wafer, such that cracks and chipping occur in the form of, for example, projecting to the right shoulder of the chip, so that the other shapes are less likely to crack. Since it is generated with a tendency, it is considered that there is a so-called easy-to-break (easily chipped) directionality depending on how to scribe or the like. The above-described dividing method is suitable for a case where the sapphire substrate is relatively thin, such as 100 to 300 μm. When the sapphire substrate is thick, it is preferable to provide a groove instead of the scribe lines 11 and 12 in accordance with the dicing method, and the scribe line and the dicing groove may be selectively used from the front surface and the back surface of the wafer. By such a method, the yield was increased by making it easier to divide the intersection again, but the grooves and holes provided at the intersection were more preferably deeper than the scribe lines and dicing grooves provided for separation. . Further, at the intersection, holes or grooves may be provided with a tool like a drill without using a laser beam machine. In the case of providing a groove, it is most preferable to form a cross-shaped groove from the sapphire substrate side even if the groove itself is shallow. FIG. 2 is a perspective view of a wafer showing another embodiment of the present invention. Each layer of the wafer is the same as that of FIG. 1, and a crystalline gallium nitride based semiconductor different from the substrate is laminated on the substrate. FIG. In this example, the grooves 14 are formed by etching or dicing in the first direction.
Is formed, the first groove 14 is securely traversed in a second direction orthogonal to the groove 14 in the first direction by another wide and sharp dicing blade as shown in FIG. After forming the groove 15 wider and deeper than the first groove 14 to be formed, the wafer is divided. In this method, as in the previous example, the occurrence of a peculiar easily crackable direction in the substrate 1 or the like at the intersection of the grooves 14 and 15 is prevented, and the crack is made in the desired direction at the intersection. Also in this case, when the sapphire substrate 1 is thin, scribe lines may be used instead of the grooves 14 and 15, but care must be taken so that the semiconductor thin film is not peeled off by the scribe lines when the later grooves are provided. As described above, it is possible to prevent the occurrence of a peculiar easily crackable direction at the intersection due to marking or groove cutting, so that undesired chipping does not occur.
Even if chipping or the like occurs in the groove, the light emission characteristics were not adversely affected.

【図面の簡単な説明】 【図1】本発明の実施例を説明するウエハーの要部斜視
図である。 【図2】本発明の第2の実施例を説明するウエハーの要
部斜視図である。 【符号の説明】 1 サファイヤ基板 11 スクライブ線 12 スクライブ線 13 孔 14 溝 15 溝
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a main part of a wafer for explaining an embodiment of the present invention. FIG. 2 is a perspective view of a main part of a wafer for explaining a second embodiment of the present invention. [Description of Signs] 1 sapphire substrate 11 scribe line 12 scribe line 13 hole 14 groove 15 groove

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−166933(JP,A) 特開 平7−131069(JP,A) 特開 平5−343742(JP,A) 特開 平6−283758(JP,A) 特開 平4−312955(JP,A) 特開 平7−273069(JP,A) 特開 昭51−118187(JP,A) 特開 昭53−237909(JP,A) 特開 昭56−169347(JP,A) 特開 平9−298339(JP,A) 特開 昭61−131583(JP,A) 特開 平8−153931(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 H01L 21/301 H01L 21/86 H01S 5/00 - 5/50 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-166933 (JP, A) JP-A-7-131069 (JP, A) JP-A-5-343742 (JP, A) JP-A-5-343742 283758 (JP, A) JP-A-4-312955 (JP, A) JP-A-7-273069 (JP, A) JP-A-51-118187 (JP, A) JP-A-53-237909 (JP, A) JP-A-56-169347 (JP, A) JP-A-9-298339 (JP, A) JP-A-61-131583 (JP, A) JP-A-8-153393 (JP, A) (58) (Int.Cl. 7 , DB name) H01L 33/00 H01L 21/301 H01L 21/86 H01S 5/00-5/50

Claims (1)

(57)【特許請求の範囲】 【請求項1】 基板上にその基板と異なる結晶系の窒化
ガリウム系半導体が積層されたウエハーを分割する方法
において、前記窒化ガリウム系半導体の積層側から第1
の方向にスクライブまたは溝形成を行った後、その第1
の方向に直交する第2の方向に第1のスクライブ線また
は溝を確実に横断する該スクライブ線または溝よりも
広で深さの深い溝を形成した後、ウエハーを分割するこ
とを特徴とするウエハーの分割方法。
(1) In a method for dividing a wafer in which a crystalline gallium nitride-based semiconductor different from that of a substrate is laminated on a substrate, the first gallium nitride-based semiconductor is firstly stacked from the lamination side .
Scribe or groove formation in the direction of
After forming a groove that is wider and deeper than the scribe line or groove that surely crosses the first scribe line or groove in a second direction orthogonal to the direction of, the wafer is divided. A method for dividing a wafer, comprising:
JP1684197A 1997-01-30 1997-01-30 Wafer splitting method Expired - Fee Related JP3421523B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1684197A JP3421523B2 (en) 1997-01-30 1997-01-30 Wafer splitting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1684197A JP3421523B2 (en) 1997-01-30 1997-01-30 Wafer splitting method

Publications (2)

Publication Number Publication Date
JPH10214997A JPH10214997A (en) 1998-08-11
JP3421523B2 true JP3421523B2 (en) 2003-06-30

Family

ID=11927445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1684197A Expired - Fee Related JP3421523B2 (en) 1997-01-30 1997-01-30 Wafer splitting method

Country Status (1)

Country Link
JP (1) JP3421523B2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4659300B2 (en) 2000-09-13 2011-03-30 浜松ホトニクス株式会社 Laser processing method and semiconductor chip manufacturing method
EP1494271B1 (en) 2002-03-12 2011-11-16 Hamamatsu Photonics K.K. Method for dicing substrate
TWI326626B (en) 2002-03-12 2010-07-01 Hamamatsu Photonics Kk Laser processing method
TWI286232B (en) * 2002-10-29 2007-09-01 Mitsuboshi Diamond Ind Co Ltd Method and device for scribing fragile material substrate
TWI520269B (en) 2002-12-03 2016-02-01 Hamamatsu Photonics Kk Cutting method of semiconductor substrate
JP4563097B2 (en) 2003-09-10 2010-10-13 浜松ホトニクス株式会社 Semiconductor substrate cutting method
KR100576317B1 (en) * 2003-12-24 2006-05-03 주식회사 이츠웰 GaN-based LED and manufacturing method of the same utilizing the technique of saphire etching
TWI374553B (en) 2004-12-22 2012-10-11 Panasonic Corp Semiconductor light emitting device, illumination module, illumination apparatus, method for manufacturing semiconductor light emitting device, and method for manufacturing semiconductor light emitting element
US8039283B2 (en) 2005-12-26 2011-10-18 Panasonic Corporation Nitride compound semiconductor element and method for manufacturing same
KR100757802B1 (en) 2006-09-29 2007-09-11 서울옵토디바이스주식회사 Vertical light emitting diode and method of fabricating the same
JP2010109015A (en) * 2008-10-28 2010-05-13 Panasonic Electric Works Co Ltd Method of manufacturing semiconductor light-emitting element
KR101678063B1 (en) * 2015-06-18 2016-11-22 주식회사 세미콘라이트 Semiconductor light emitting device and method of manufacturing the same
CN107154455B (en) * 2016-03-04 2020-03-10 日东电工(上海松江)有限公司 Method for manufacturing sealed optical semiconductor element

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