JPH08101667A - Method for gradation driving of active matrix liquid crystal panel - Google Patents

Abstract

PURPOSE: To provide a method for driving gradation of an active matrix liquid crystal panel capable of performing multi-level display, reducing the number of external source input lines and the number of analog switches and low voltage driving a gradation drive circuit of a low cost flat display. CONSTITUTION: A gradation reference voltage (a) inverts a slope of a staircase step voltage at every one scan time according to write polarity, and the step voltage of a positive polarity write period T1 is reduced with a step time, and the voltage when the amplitude of the gradation reference voltage (a) is maximum is held for a fixed period, and the step voltage of a negative polarity write period T2 is increased with the step time, and the voltage when the amplitude of the gradation reference voltage (a) is maximum, is held for a fixed period, and a drive condition of a scan bus line sets a scan bus line voltage in an off voltage within a fixed hold period of the gradation reference voltage, and on the other hand, the drive voltage of a counter electrode is inversion- driven at every one scan line synchronizing with the write polarity of the gradation reference voltage (a).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grayscale driving method which enables halftone display in a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 10 is well known as a circuit of a liquid crystal display which is a kind of flat display. In FIG. 10, a plurality of X electrode lines (X ₁ , X ₂ , ...) And Y electrode lines (Y ₁ , Y ₂ , ...) Are arranged so as to intersect with each other, and the X electrode lines and the Y electrode lines are intersected with each other. An active element 6 such as a TFT (thin film transistor) and a liquid crystal display element 7 are formed.

The Y electrode line is also called a data signal line, and is connected to a display signal circuit 9 which outputs a display data signal of each liquid crystal display element 7. The X electrode line is also called a scanning signal line, and is connected to the scanning signal circuit 10 that sequentially outputs scanning signals. The active element 6 is driven by a line-sequential driving method in which the X electrode lines are sequentially scanned and driven, and the active elements 6 on the X electrode lines are turned on in synchronization with the scanning of the X electrode lines. The display data signal is output from the signal circuit 9, and the data signal is written to the corresponding liquid crystal display element 7 via the active element 6 in the ON state. It has been attempted to improve the charge retention characteristics of the liquid crystal display element 7 by providing the liquid crystal display element 7 with a storage capacitor 8 if necessary.

Here, by varying the amplitude value of the data signal voltage to be written in the liquid crystal display element 7, the write voltage to the liquid crystal display element 7 or the charge amount is variably controlled, and the light transmittance of the liquid crystal is varied. Can be controlled. This method is called a voltage modulation driving method, and is a typical gradation driving method for displaying halftones in a liquid crystal display.
As a liquid crystal drive circuit that enables gradation display by the voltage modulation drive method, for example, "Hitachi, driver for liquid crystal drive, HD66310T" shown in FIG. 11 is known. FIG. 11 is capable of displaying 8 gradations, and includes 3-bit display data D0j, which corresponds to a liquid crystal pixel.
D1j and D2j are synchronized with the clock signal CL2 to generate the first signal.
Is input to the latch circuit 11. First latch circuit 11
Then, the display data signal input to the second latch circuit 12 is input to the second latch circuit 12 in synchronization with the clock signal CL1.
Then, the output of the second latch circuit 12 is input to the voltage selector circuit 13.

The voltage selector circuit 13 is composed of a decoder circuit or the like, and, for example, based on a 3-bit input signal, one of 2 ³ = 8 output lines is selected.
Data is output on the output line of the book. In this circuit configuration, the output of the voltage selector circuit 13 selects any _{one of the} next-stage analog switches 14 _{1 to} 14 ₈ to turn it on, and outputs _eight switches connected to the analog switches 14 _{1 to} 14 _8. Any one of the power supply input lines V0 to V7
One of them is output to the driver output Y _n .

The liquid crystal driver circuit manufactured by Hitachi, Ltd. includes 160 driving circuits shown in FIG. In addition, the liquid crystal display device includes a number of liquid crystal driver circuits corresponding to the number of pixels of one horizontal scanning line. The transfer from the first latch circuit 11 to the second latch circuit 12 is performed after the display data for one horizontal scanning is input to the first latch circuit 11.

[0007]

However, in the above-mentioned gradation drive circuit of the liquid crystal display,
When increasing the number of gradations, it is necessary to input an external power source in a number corresponding to gradation reproduction. Further, if the drive circuit is integrated into an IC, the area occupied by the wiring system of the power supply input line increases inside the IC, which is not economical.

Furthermore, the number of analog switches composed of P-MOS, N-MOS, FET, etc., is also required to be equivalent to the number of gradation reproductions, which is not economical when considering IC implementation.
The present invention solves the above-mentioned problems, can perform multi-gradation display, and can reduce the number of external power supply input lines and the number of analog switches. An object of the present invention is to provide a gradation driving method of an active matrix type liquid crystal panel that can be driven by voltage.

[0009]

In order to achieve the above-mentioned object, the present invention provides: (1) a scan bus line and a data bus line arranged to intersect each other, and an intersection of the scan bus line and the data bus line. A rear substrate provided with a switching element corresponding to each pixel electrode disposed in the section, a front substrate provided with a transparent counter electrode, and a liquid crystal layer disposed between the rear substrate and the front substrate. In the grayscale driving method of an active matrix liquid crystal panel, an n-bit grayscale is used as a data signal circuit for performing grayscale display of 2 ⁿ level (n is an integer of 2 or more) display pixels connected to a data bus line. A shift register circuit that sequentially transfers data, a latch circuit that stores the contents of the shift register circuit, a grayscale data stored in the latch circuit, and a grayscale control clock number. A circuit for detecting a match, a pulse width modulation circuit for converting into a pulse having a width according to the output of this detection circuit, and the output of this pulse width modulation circuit is inputted as a switching signal for controlling ON / OFF, and this switching signal The grayscale reference voltage is input to one of the analog switch circuit and the analog switch circuit controlled by, and the data bus line is connected to the other of the analog switch circuit. A voltage is charged in the wiring capacitance connected to the data bus line, and the output of the analog switch is in a high impedance state during the OFF period to hold a potential of the wiring capacitance, and the gradation reference voltage is stepped. The slope of the step voltage is inverted every scanning time according to the write polarity, and the positive polarity write period is changed. The step-up voltage decreases with the step time, and the voltage when the amplitude of the gradation reference voltage is maximum is maintained for a certain period, and the step voltage during the negative polarity writing period increases with the step time and the amplitude of the gradation reference voltage becomes maximum. Voltage is held for a certain period of time, and the driving condition of the scanning bus line is to set the scanning bus line voltage to the off voltage within the certain holding period of the gradation reference voltage, while the driving voltage of the counter electrode is set to the gradation reference voltage. Inversion driving is performed for each scanning line in synchronization with the writing polarity.

(2) In the gray scale driving method of the active matrix type liquid crystal panel described in (1) above, the data bus line voltage in the white display mode is almost gray scale because the gray scale reference voltage is fully sampled and charged. Try to obtain a voltage waveform equivalent to the reference voltage. (3) In the grayscale driving method of the active matrix type liquid crystal panel described in (1) above, the data bus line voltage in the halftone display mode is set to a predetermined differential voltage after following the grayscale reference voltage.

(4) In the grayscale driving method of the active matrix type liquid crystal panel described in (1) above, in the black display mode, positive and negative first grayscale voltages corresponding to a constant holding period of the grayscale reference voltage are sampled. Therefore, the holding voltage period of the data bus line is set to be the longest, and the differential voltage applied to the liquid crystal cell is set to be the largest.

[0012]

[Action]

(1) According to the grayscale driving method of the active matrix type liquid crystal panel described in (1) above, as shown in FIG. 1, the grayscale reference voltage a is written with a stepwise step voltage gradient every scanning time. The voltage is inverted according to the polarity, the step voltage in the positive polarity writing period T ₁ decreases with the step time, and the voltage when the amplitude of the gradation reference voltage a is maximum is held for a certain period.
The step voltage in the negative polarity writing period T ₂ increases with the step time, the voltage when the amplitude of the gradation reference voltage a is maximum is held for a certain period, and the driving condition of the scan bus line is the constant holding period of the gradation reference voltage. Since the scanning bus line voltage is set to the off voltage in the inside, while the driving voltage of the opposite electrode is inverted and driven for each scanning line in synchronization with the writing polarity of the gradation reference voltage a, (A) Active By adopting the analog switch system as the output form of the data signal circuit of the matrix type liquid crystal panel, and by writing and holding the liquid crystal drive voltage in the wiring capacitance of the data bus line with one analog switch for the data bus line, Since the data signal circuit can be simplified, high integration of the IC can be achieved.

(B) Since the amplitude of the gradation reference voltage can be set to be equal to the liquid crystal drive voltage, it is possible to reduce the voltage and power consumption of the IC. Therefore, an IC for gradation driving
Cost reduction can be realized. (2) According to the gradation driving method of the active matrix type liquid crystal panel described in (2) to (4), as shown in each display mode, one kind of gradation reference voltage is applied to the input terminal of the analog switch. By inputting, converting the gradation data into time data, modulating the on time of the analog switch, and using the wiring capacity of the data bus line for sampling and holding functions, multi-gradation driving can be realized by a simple method. .

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram of a gradation driving method of an active matrix type liquid crystal panel showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of an active matrix type liquid crystal display device showing an embodiment of the present invention.

In FIG. 2, 106 is a data signal circuit for generating a voltage that enables halftone display, 107 is a scanning signal circuit, 108 is a data bus line connected to the output of the data signal circuit 106, and 109 is a scanning signal. A scan bus line connected to the output of the circuit 107, 110 is provided at the intersection of the data bus line 108 and the scan bus line 109, for example, an a-si thin film transistor (hereinafter, T).
FT), 111 is a liquid crystal cell, one of which is connected to the TFT 110, and the other of the liquid crystal cell 111 is connected to the counter electrode 113, and is electrically a capacitor of, for example, about 0.2 PF.

Reference numeral 112 denotes a storage capacitor provided in parallel with a capacitor composed of the liquid crystal cell 111, for example, 0.5 PF.
Is the capacitor. In addition, the data bus line 10
8 and the scanning bus line 109 are arranged to face the counter electrode 113 via the liquid crystal, and the capacitor 114 and
And 115 are formed. Also, data bus line 1
08 and the scan bus line 109 intersect with each other, a parasitic capacitance 116
Is formed. The wiring capacitance of the data bus line 108 is dominated by the capacitor 114 and the parasitic capacitance 116.

FIG. 3 is a block diagram of a data signal circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention. As shown in this figure, for example, 201 is input with 8-bit grayscale data D0 to D7, a start signal ST which is a horizontal synchronization signal, and a data shift clock CP, for example, a shift of 8 bits × 192. A register circuit 202 is, for example, an 8-bit × 192 latch circuit to which the output of the shift register circuit 201 is input,
By the LOAD signal, D0 of the shift register circuit 201
~ D7 output is stored in the latch circuit 202. The output of the latch circuit 202 is input to the pulse width modulation circuit 203. The pulse width modulation circuit 203 has L as a set signal.
The OAD signal and the pulse width control clock CPG are input as the reset generation signal.

The output signal of the pulse width modulation circuit 203 is supplied as an ON / OFF control signal for the analog switch 204. The gradation reference voltage Vref set to the stepwise voltage is supplied to one of the analog switches 204, and the output V _0m (m = 1 to 192) is obtained from the other. FIG. 4 is a pulse width modulation circuit diagram in a data signal circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention.

The operation of this pulse width modulation circuit will be described with reference to FIG. When the gradation display data D0 to D7 are stored in the latch circuit 202 by the LOAD signal, the stored data are input to the coincidence circuit 303-2 from the outputs D0 to D7 of the latch circuit 202. At the same time, the LOAD signal sets the flip-flop circuit 303-3 that constitutes the pulse width modulation circuit 303. Clock counter 3
03-1 counts the number of pulse width control clocks CPG, and outputs 0 to g7 to output Q0 of the latch circuit 202.
To Q7 and the data of outputs g0 to g7 of the clock number counter 303-1 are Q _m and g _m (m = 0 to 6)
The signal obtained by inputting to the EXNOR circuit and the pulse width control clock CPG so that the data of the
It is input to the D circuit and the output of the coincidence circuit 303-2 is obtained.

The output obtained by the coincidence circuit 303-2 resets the output of the flip-flop circuit 303-3.
The output is set by the LOAD signal and reset by the output signal indicating the coincidence of the number of gradation data and the gradation control clock CPG. As described above, the pulse width modulation circuit output PWM-m having the pulse width corresponding to the gradation data is obtained. The output PWM-m is supplied to the analog switch 204 as shown in FIG. 3, and controls the on / off of the analog switch 204.

FIG. 5 shows a block for generating the gradation reference voltage Vref input to one of the analog switches 204.
As shown in FIG. 5, the gradation reference voltage generating circuit is
An OR circuit is provided, and gradation reference voltage generation data (Vref-
D0 to D7), a data generation circuit 410 for outputting D / A input data, a D / A converter 411, and a D / A converter
It is composed of an amplifier 412 that amplifies the output voltage of the converter 411.

Table 1 shows gradation reference voltage generation data (Vref
-D0 to D7) and D / A input data determined by the logical condition (exclusive OR) of the write polarity signal.

[0023]

[Table 1]

As the D / A input data, the gradation reference voltage generation data is inverted and input when the polarity is positive. FIG. 6 shows the relationship between the output voltage and input data (D0 to D7) of the D / A converter in the data signal circuit of the active matrix type liquid crystal display device showing the embodiment of the present invention.

As is apparent from this figure, the positive polarity write voltage characteristic and the negative polarity write voltage characteristic are inverted with respect to the D / A input data. For example, if the D / A input data is 00H
In the case, the negative write voltage outputs 0V, and the positive write voltage outputs 1V. In the case of FFH, the negative write voltage is 1V and the positive write voltage is 0V.

FIG. 7 shows a DA in a data signal circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention.
The output voltage waveform of the converter 411 is shown. That is, FIG.
7A is a write polarity signal, FIG. 7B is a waveform of gradation reference voltage generation data (Vref-D0), and FIG. 7C is D /.
A input data (D / A-D0) waveform, FIG.
The A output voltage waveforms are shown.

During the negative writing period, the step voltage increases with the step time. The step voltage level is
It is determined by the D / A input data, and for example, in the case of an 8-bit input, a 256 level voltage can be generated. When the D / A output voltage waveform reaches the 256 level in the negative polarity writing period, the D / A output voltage waveform is held at the same level for a certain period. In the positive polarity writing period, the step voltage decreases with the step time,
When the level reaches 6 levels, a certain period of 2
Hold 56 levels.

The operation of the gradation driving method of the present invention will be described with reference to FIGS. 1 and 8. FIG. 8 shows the output voltage waveform of the data signal circuit, and FIG. 8A shows the waveform of the gradation reference voltage a and the waveform of the data bus line voltage b, respectively.
Indicates the data bus line holding voltage. FIG.
8B shows an analog switch control signal, and FIG. 8C shows LO.
The AD signal, and FIG. 8D shows the matching circuit signal, respectively.

In the output configuration of the data signal circuit, analog switches are connected to each data bus line in pairs. The gradation reference voltage a is supplied to the input terminal of the analog switch, and the voltage of the data bus line is determined by time modulation of the analog switch control signal. The control time of the analog switch is determined by the LOAD signal and the coincidence circuit signal, and the data bus line voltage state during the positive polarity write period is such that when the analog switch is turned on, the grayscale reference voltage a is kept constant. It is initialized to a voltage value of (first gradation voltage of positive polarity voltage). During the ON period of the analog switch, the voltage of the data bus line samples and charges the wiring reference capacitance of the bus line with the gradation reference voltage a.

During the off period of the analog switch, since the switch output forms a high impedance state, the charge voltage of the data bus line is held until the analog switch is turned on next time. During the negative polarity writing period, the same operation as the positive polarity is performed. When the analog switch is turned on, the potential of the data bus line is kept for a certain holding period (negative voltage of 1
It is initialized to the voltage of the gradation voltage) and holds the bus line potential when it is off.

A gradation driving method of the active matrix type liquid crystal panel of the present invention will be described with reference to FIGS. FIG. 9 shows the relationship between the liquid crystal cell drive voltage and the transmittance. Taking the drive voltage (V) on the horizontal axis and the transmittance (T) on the vertical axis, the transmittance (T) of the liquid crystal cell is high when the driving voltage is low,
The display mode is set so that the transmittance decreases when the driving voltage is high.

FIG. 1 is an explanatory view of a gradation driving method of an active matrix type liquid crystal panel of the present invention. FIG. 1A shows a gradation reference voltage a, and FIG. 1B shows a white display mode. ,
1C shows the data bus line voltage b and the counter electrode voltage c in the halftone display mode and in the black display mode, respectively. In FIG.
The gradation reference voltage a inverts the stepwise step voltage gradient every scanning time according to the writing polarity, and the step voltage in the positive polarity writing period T ₁ decreases with the step time.
The voltage when the amplitude of the gradation reference voltage a is maximum is held for a certain period, the step voltage of the negative polarity writing period T ₂ increases with the step time, and the voltage when the amplitude of the gradation reference voltage a is maximum is constant. The scanning bus line driving condition is maintained for a certain period, and the scanning bus line voltage is set to an off voltage within a constant holding period of the gradation reference voltage, while the driving voltage of the counter electrode is synchronized with the writing polarity of the gradation reference voltage a. Then, inversion driving is performed for each scanning line.

As described above, the counter electrode of the liquid crystal cell is AC-driven to guarantee the life of the liquid crystal cell and to drive the data signal circuit at a low voltage, and supplies a rectangular voltage which is inverted for each write polarity. . Since the data bus line voltage in the white display mode is fully sampled and charged by the gradation reference voltage, a voltage waveform substantially equal to the gradation reference voltage is obtained. The voltage finally written in the liquid crystal cell is determined by the data bus line voltage when the scanning line voltage of the TFT is turned off.

The effective voltage applied to the liquid crystal cell is
It is determined by the voltage difference between the data bus line voltage and the counter electrode voltage. The difference voltage applied to the liquid crystal cell in the white display mode is
The difference voltage is set to V1 (+), which is the lowest in the positive polarity writing period, and V1 (-), which is the lowest in the negative polarity writing period.

The data bus line voltage in the halftone display mode is, for example, a differential voltage V128 after tracking the gradation reference voltage.
(+) And V128 (-) are set. In the black display mode, since the positive and negative first grayscale voltages corresponding to the constant holding period of the grayscale reference voltage are sampled, the holding voltage period of the data bus line is the longest, and the differential voltage applied to the liquid crystal cell is V256 ( The maximum value can be set to +) and V256 (-).

As shown in each display mode, one kind of gradation reference voltage is input to the input terminal of the analog switch, the gradation data is converted into time data to modulate the ON time of the analog switch, and By utilizing the line wiring capacitance for the sampling and holding functions, multi-gradation driving can be performed by a simple method. Even if the gradation reference voltage is input for each color (R.G.B.), the other operations are the same.

The off-voltage condition of the scanning line voltage is set during the period during which the holding voltage of the data bus line after sampling and charging is stable, and the TFT is turned off after the data bus line voltage is stable especially in the white display mode. Put in a state. Further, the amplitude of the gradation reference voltage can be set within the drive voltage range of the liquid crystal cell (range of V1 to V256). The switching of the counter electrode voltage is set after the scan line voltage (after writing the data bus line voltage).

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0039]

As described in detail above, according to the present invention, the following effects can be achieved. (1) The analog switch system is adopted as the output form of the data signal circuit of the active matrix type liquid crystal panel, and the liquid crystal drive voltage is written and held in the wiring capacitance of the data bus line with one analog switch for the data bus line. By doing so, since the data signal circuit can be simplified, high integration of the IC can be achieved.

(2) Since the amplitude of the gradation reference voltage can be set to be equal to the liquid crystal drive voltage, it is possible to reduce the voltage and power consumption of the IC. Therefore, an IC for gradation driving
Cost reduction can be realized.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a grayscale driving method of an active matrix type liquid crystal panel showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of an active matrix liquid crystal display device showing an embodiment of the present invention.

FIG. 3 is a block diagram of a data signal circuit of an active matrix liquid crystal display device showing an embodiment of the present invention.

FIG. 4 is a pulse width modulation circuit diagram in a data signal circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention.

FIG. 5 is a block diagram of a grayscale reference voltage input to one of analog switches in a data signal circuit of an active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the output voltage and the input data of the D / A converter in the data signal circuit of the active matrix type liquid crystal display device showing the embodiment of the present invention.

FIG. 7 is a diagram showing an output voltage waveform of a DA converter in a data signal circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention.

FIG. 8 is an output voltage waveform diagram of a data signal circuit of an active matrix liquid crystal display device showing an embodiment of the present invention.

FIG. 9 is a diagram showing a relationship between liquid crystal cell drive voltage and transmittance.

FIG. 10 is a circuit diagram of a conventional active matrix type liquid crystal display device.

FIG. 11 is a drive circuit diagram of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

 106 data signal circuit 107 scanning signal circuit 108 data bus line 109 scanning bus line 110 a-si thin film transistor (TFT) 111 liquid crystal cell 112 storage capacitor 113 counter electrodes 114, 115 capacitor 116 parasitic capacitance 201 shift register circuit 202 latch circuit 203 pulse width Modulation circuit 204 Analog switch 303 Pulse width modulation circuit 303-1 Clock number counter 303-2 Matching circuit 303-3 Flip-flop circuit 410 Data generation circuit 411 D / A converter 412 Amplifier

Claims (4)

[Claims] 1. A back substrate provided with a scanning bus line and a data bus line arranged to intersect each other, and a switching element corresponding to each pixel electrode arranged at an intersection of the scanning bus line and the data bus line. And a front substrate provided with a transparent counter electrode, and a liquid crystal layer disposed between the rear substrate and the front substrate, in a grayscale driving method of an active matrix type liquid crystal panel, the method is connected to a data bus line. A shift register circuit that sequentially transfers n-bit grayscale data and a content of the shift register circuit are stored as a data signal circuit that performs grayscale display of 2 ⁿ levels (n is an integer of 2 or more) for each display pixel. A latch circuit, a circuit that detects a match between the grayscale data stored in the latch circuit and the number of grayscale control clocks, and a pulse having a width corresponding to the output of the detection circuit A pulse width modulation circuit, an output of the pulse width modulation circuit is input as a switching signal for controlling ON / OFF, and an analog switch circuit controlled by the switching signal, and a grayscale reference voltage is applied to one of the analog switch circuits. The data bus line is connected to the other side of the analog switch circuit, the gradation reference voltage is charged to the wiring capacitance connected to the data bus line during the ON period of the analog switch circuit, and the analog switch is connected during the OFF period. Is provided with a data signal circuit configured to hold the potential of the wiring capacitance in a high impedance state, and the gradation reference voltage inverts the slope of the stepwise step voltage according to the write polarity every one scanning time, Voltage during the write operation period decreases with the step time, and the voltage is constant when the amplitude of the gradation reference voltage is maximum. The step voltage during the negative writing period increases with the step time, and the voltage when the amplitude of the gray scale reference voltage is maximum is held for a certain period, and the driving condition of the scan bus line is the constant holding period of the gray scale reference voltage. The scan bus line voltage is set to the off voltage in the inside, while the drive voltage of the counter electrode is inverted and driven for each scan line in synchronization with the writing polarity of the gradation reference voltage. Driving method for LCD panel. 2. The grayscale driving method for an active matrix type liquid crystal panel according to claim 1, wherein the data bus line voltage in the white display mode is substantially the grayscale reference voltage because the grayscale reference voltage is fully sampled and charged. A gradation driving method for an active matrix type liquid crystal panel, which is characterized by obtaining a voltage waveform equivalent to 3. The grayscale driving method for an active matrix type liquid crystal panel according to claim 1, wherein the data bus line voltage in the halftone display mode is set to a predetermined differential voltage after following the grayscale reference voltage. A method for driving a gradation of a characteristic active matrix type liquid crystal panel. 4. The gradation driving method for an active matrix type liquid crystal panel according to claim 1, wherein in the black display mode, a positive and negative first gradation voltage corresponding to a constant holding period of the gradation reference voltage is sampled. A gradation driving method for an active matrix type liquid crystal panel, characterized in that a holding voltage period of a data bus line is set to be longest and a difference voltage applied to a liquid crystal cell is set to be largest.