JPH0799620B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory capable of reducing the chip area at high speed and high S / N.

[0002]

[Prior art]

[0003]

[Problems to be Solved by the Invention] As semiconductor memories become highly integrated and have large capacities in the future, there will be designs that fully consider the area occupied by the memory array and the speed or S / N directly related to the memory array itself. Becomes important. However, although the conventional method is insufficient, this conventional example will be described by taking a one-transistor MOS memory as an example.

FIG. 1 shows an X and Y decoder (XDEC, YD
This is an example in which the area of the decoder section is reduced by arranging EC) at almost the same position as compared with a method in which XDEC and YDEC are separated as described later. However, the drawback is that the control line YC for the control signal φ _y of the sense amplifier is used.
However, as shown in FIG. 2, the memory array must be bent at a right angle in the middle, and because the material of this control line is the same as the material of the word line and data line, the effective memory cell area is reduced by this control line. Is large. Therefore, even if the decoder area becomes small, the memory array area becomes large, and consequently the chip area cannot be reduced. Data pair line D to be electrically balanced, which causes complicated operation of the decoder and causes erroneous operation.
₀ , D ₀ ￣ are spatially separated cells (open deta
It is called a line arrangement or 1-intersection cell), so there is a lot of noise. FIG. 3 shows a method for eliminating the above-mentioned drawback. That is, YDEC and XD
EC is separated, and φ _y selected by YDEC laid out close to the sense amplifier SA is output.
Is controlled to output to common output lines I / O and I / O. However, the disadvantage of this method is that YD
EC, I / O line, SA, memory array MA1 and MA
2, or because it is laid out at the midpoint of MA3 and MA4, it is difficult to layout, and in view of the layout, capacitance imbalance easily occurs in the data symmetry D ₀ , D ₀ ￣, and noise becomes large. The capacity of
If one data line is divided into 2n (n = 2 in this figure) for the purpose of increasing the read signal to the A input terminal, YDE
N sets of C, I / O lines, and SA are required, and the area increases as n becomes larger, which is one intersection cell, so that noise is large. FIG. 4 shows an example in which the YDEC is arranged at one end of the chip in order to eliminate the complexity of laying out the SA and the YDEC close to each other. However, as a drawback, the control line YC for φ _y that controls the output of SA is formed in the same wiring layer as the data lines D ₀ and D ₀ ￣ as shown in FIG. 5, and this YC runs in MA1. So
The area of MA1 will increase by that amount.
It suffices for C to have the function of controlling SA,
The MA2 side is unnecessary. However, in order to maintain the electrical balance of D ₀ and D ₀ , it is also necessary on the MA2 side. Therefore, the area of MA2 is large like MA1, and since it is a one-intersection cell, noise is large and two pairs of I / O lines are required. FIG. 6 shows another conventional example. Memory cells (fo
It is a high S / N in general because it is called an "dedded dataline arrargement" or a 2-intersection cell, and SA is YDEC.
Since it can be arranged at one end of MA1 and MA2 regardless of the I / O line, the layout is easy. However, the disadvantage is that if one data line is divided into 2n (n = 2 in this example) for the purpose of reducing the capacity of the data line and increasing the read signal to the SA input terminal, I / O line And SA are n sets, Y
DEC requires n / 2 pairs, and the larger n is, that is, the higher the integration and the larger the capacity, the larger the area.

FIG. 7 shows another conventional example. The advantage is that
Since the layout is a 2-intersection cell, divide the data line in two,
If MOSTQ ₀ , Q ₁ , Q ₀ ￣ and Q ₁ ￣ are selected, it is possible to sense at the midpoint. Therefore, S from the memory cell MC
The read signal to the A input terminal can be doubled as compared with the conventional method (FIG. 6) because the capacity of the data line is halved due to the division. As a drawback, the layout has two intersection cells, but the operation is one intersection cell, so noise is large. Since the I / O line is taken out on one side, the write operation to the memory cell MC on the MA1 side can be performed from the I / O line by Q _{1 −} and Q ₀ and Q ₁ and Q _0.
It is slow because it is done via ￣, at the time of reading,
The amplified signal is output to I / O and I / O via Q ₁ and Q _y as well as Q ₀ and Q _y , so the data is slow in the two-intersection cell layout. Since the line pitch is almost twice that of the one-intersection cell, the YDEC and I / O lines cannot be arranged in the SA part which is the midpoint between MA1 and MA2. Therefore, as described above, the I / O line, which is slow, is set to MA1.
If you try to take it out from the side as well, you can solve the above-mentioned drawback of low speed. However, the area increases by the I / O line and YDEC. This conventional example is IEEE J. Solid-State C
ircuits, vol. SC-15, No. 5, Oct. 1980, P.831.

FIG. 8 shows another conventional example, and the details are ISSCC81 Te.
chnical Digest, P.84. The advantage is that since it is a two-intersection cell, it has low noise, and the data line can be divided into two and sensed at the midpoint. That is, the read signal to the SA input terminal can be doubled as compared with the conventional method (FIG. 6). However, as a drawback, since the I / O line is taken out on one side, the write operation to the memory cell MC belonging to MA1 is performed with Q _{y −} , Q ₁ and Q ₀ , and Q _y , Q _{1 −} and Q _0.
It is slow because it is done via ￣. When reading,
Since the amplified signal is output to the I / O line via Q ₁ and Q _y and Q _{1 −} and Q _y , the data line pitch is 1 in the 2-intersection cell where the read operation is slow. Since it is twice as large as the intersection cell, YDEC and I / O lines are set to MA1 and MA2.
It cannot be placed in the SA part, which is the middle point. Therefore, if the I / O line, which becomes slow as described above, is also taken out from the MA1 example, the above-mentioned drawback of low speed can be solved. However, the area increases by I / O lines and YDEC.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a chip
Providing highly integrated semiconductor memory devices that effectively utilize area
To do. In order to achieve such an object of the present invention
A semiconductor memory device according to a representative embodiment has a plurality of wires.
The word line (W) and the plurality of word lines (W) are crossed.
A plurality of data line pairs (D ₀ , D ₀ ￣; D
₀ ', D ₀ '), and one of the above word lines
One word line and one of the plurality of data line pairs
It is provided in one of the two parts where the data line pair intersects.
Of a folded data line system having a memory cell
And the second memory array (MA, MA ') and the first memory array
Memory array (MA) data line pairs (D ₀ , D ₀ ￣)
And the data line pair (D) of the second memory array (MA ').
₀ ', _{D 0'} above with commonly provided in ¯¯¯) and
The data line pair of the first memory array (MA)
(D ₀ , D ₀ ￣) and the second memory array (M
A ') with the above data line pair (D ₀ ', D ₀ '￣ ￣ ￣)
Common data line pair (CD ₀ , CD ₀ ￣) placed between
And the data line pair of the first memory array (MA)
(D ₀ , D ₀ ￣) and the common data line pair (CD ₀ , C
First switch means (GC) to connect with D ₀ ￣
And the data line of the second memory array (MA ')
Pair (D ₀ ', D ₀ ' ￣ ￣) and the common data line pair (C
Second switch means for connecting D ₀ , CD ₀ ￣)
(GC ') and the signal appearing on the common data line pair
The common data line pair (CD ₀ , CD ₀ ￣) as wide as possible
Common to the amplifier (SA) whose two inputs are connected to
The third connected to the data line pair (CD ₀ , CD ₀ ￣ ￣)
The switch means (SW) and the third switch means (S
W) via the common data line pair (CD ₀ , CD ₀ ￣
Common signal line pair (I / O, I / O)
), The first switch means (GC) and the second switch means
First decoding hand control the switch means (GC ')
The stage (XDEC) and the third switch means (SW)
Second decoding means for controlling the (YDEC), the second
Decoding means (YDEC) and the third switch means
(SW) and is connected to the third switch.
And a control line (YC) for controlling the switch means (SW).
The above memory cell has one capacity and one transistor.
Of the first memory array (MA).
The data line pair (D ₀ , D ₀ ￣) is the second decoding
Of the stage (YDEC) and the third switch means (SW)
The control line (YC) disposed between the
The above-mentioned data line pair (D ₀ , D ₀ ￣ ) of the rear array (MA)
It is provided on the conductive layer that constitutes the
It is composed of another conductive layer, and has the above-mentioned first memo.
The above data line pair (D ₀ , D ₀ ￣) of the rear array (MA )
Of the first memory array (MA) so that it is substantially parallel to
It is characterized by being arranged above (see FIG. 17).
That is, a common signal common to the first and second memory arrays
A line pair, and a data line pair of the first and second memory arrays
The third switch means for connecting the common signal line pair includes the first and the third switch means.
The first memory is arranged between the two memory arrays.
Moriaray has a second decoding means and a third switching means.
And a control disposed between and for controlling the third switch means
The lines form a conductive line forming a data line pair of the first memory array.
Another conductive layer provided on the layer through an insulating film.
Is completed and the first memory array return date is
The first memory so that it is substantially parallel to the data line pair of the data line system.
It is characterized by being arranged on an array.
It

[0008]

[0009]

According to the typical embodiment of the present invention,
It has a naive effect. (1) When viewed from the common signal line, the data of the first memory array
The balance between the data line pair and the data line pair of the second memory array
Read from which memory array.
However, there is no imbalance in read time. (2) The second decoding means includes a first memory array and a second memory array.
Since it is not placed between memory arrays, the memory array section
Area can be reduced. (3) The control line configures the data line pair of the first memory array.
Another conductive layer provided on the conductive layer formed through an insulating film
Because it is composed of layers, it increases the area of the memory array.
There is nothing to do. (4) The control line is almost the same as the data line pair of the folded data line system.
Since they are arranged in parallel, both data lines of the data line pair
On the other hand, the noise from the control line is in phase, and the effect of noise is small.
Sai.

[0010]

EXAMPLES Examples will be described below.

FIG. 9 shows the concept of the present invention.
That is, in a memory that forms a memory array by forming a matrix with word lines W and data lines D _ij , one data line is divided into D ₀₀ , D ₀₁ , D ₀₂ and D ₀₃ as shown in the figure. , A switch SW ₀₀ , SW ₀₁ , SW ₀₂ , which is controlled by an output control signal YC ₀ by a Y decoder and a Y driver (YDEC in the figure) on a part of each divided data line.
A common input / output line I / O0, I / O1, I common to other divided data lines (eg, D ₁₀ ) provided with SW ₀₃
Data is exchanged between / O2 and I / O3. By doing so, the data lines are subdivided, so that the word voltage appearing on the selected word line W by the X decoder and the word driver (generally referred to as XDEC in the figure) causes high speed transfer from the memory cell MC to the data line D ₀₀ . A high output voltage read signal can be obtained at. In this method, an increase in chip area due to subdivision can be suppressed. That is, as in the conventional example (Fig. 3), YDE is attached to each switch part.
This is because it is not necessary to lay out C, and YDEC that is common to the subdivided data lines is sufficient.

Further, in FIG. 9, if YC is formed by a manufacturing process different from that of D _ij , three-dimensional wiring becomes possible, so that the area of the memory array does not increase. For example, the word line is made of metal such as poly-Si or Mo, and the main part of D _ij is made of A in the first layer.
It is also conceivable that YC is formed by A1 in the second layer. Alternatively, it is conceivable that the word line is formed by A1 of the first layer, the main part of D _ij is formed by poly Si or a diffusion layer, and YC is formed by A1 of the second layer. This is the tenth
As shown in the 11-transistor cell 11, the memory cells (two-intersection cells in FIG. 10 and one-intersection cell in FIG. 11) differ, but in short, three-dimensional wiring may be performed.

That is, in the conventional example a in the case of the one-intersection cell shown in FIG. 12 and the present invention b, and in the present invention a and b in the case of the two-intersection cell shown in FIG. 13, YC (in the figure) By providing the broken line) in a layer different from the layer in which the word line W and the data line D are provided, the layout problem and the problem of increasing the cell area due to the provision of YC are solved.

Further, FIGS. 14 and 15 show an example in which two YCs are shared by two pairs of data lines in a two-intersection cell. FIG. 14 shows a case of sharing with an adjacent pair line in the same sub array, and b is an example in which the data line of a is divided into two and I / Os are arranged in the middle. In FIG. 15, YC is shared with the pair lines in different subarrays, and b is an example in which the data pair lines are further divided into two as in the above.

Further, FIG. 16 shows the case of FIG.
FIG. 17 shows a more detailed specific example of FIG. That is, FIG. 16 shows data pair lines D _ij and D _ij ￣
And another data pair line D ′ _ij , D ′ _ij — is a common differential amplifier (sense amplifier: hereinafter abbreviated as SA). D _ij via the gate control GC controlled by XDEC the SA in common, D _ij ¯ or D _'ij, D'
By connecting to _{ij and} turning on one of the GCs belonging to the selected memory cell MC, a sufficient read signal voltage from MC can be obtained as in FIG. The signal voltage is amplified by each SA, and the amplified signal is controlled by YC which is controlled by YDEC. For example results YC ₀ is selected, the pulse voltage appears in YC _0, only the output of the SA, which is controlled by the YC ₀ each I
/ O lines I / O0, I / O1, ..., and the data output Dout controlled by the address signal A and the write / read control signal WE is taken _out of the chip by the read / write control circuit (RWC). . Similarly, writing is performed by inputting the data input D _i from the outside of the chip to the selected I / O line and then to the selected MC.

This will be described in more detail with reference to FIGS. 17 and 18. First, all nodes (D ₀ , D ₀ ￣, CD ₀ , CD ₀ ￣, D ′ ₀ , D ′ ₀ ￣, etc.) are precharged to a high potential by the precharge signal φ _p , and then the word line is XDEC. When W is selected and the word pulse φ _w is output, the MC connected to it is selected and the corresponding data line (for example, D ₀ ) has the storage capacity C _{s of the} MC and the capacity of the data line. The determined minute signal voltage is output. At the same time, by turning on φ _DW from the dummy cell DC, a reference voltage is generated on CD ₀ . Before the word line is selected, the gate control GC 'to which the selected MC does not belong is turned off by changing GCL' from the high level during precharge to the low level.
C remains ON. Therefore the D _0, CD ₀ signal voltage corresponding to the information from the MC to the, D ₀ ¯, CD ₀
The reference voltage from DC appears in ￣. This reference voltage is MC because the DC capacity is selected to be Cs / 2.
Is set to the middle of the read voltage appearing on D ₀ and CD ₀ corresponding to the information "1" and "0" of the sense amplifier SA.
A delicate fluctuation voltage corresponding to the information "1" and "0" always appears at the input terminal of. After that, the SA is operated by the start pulse φ _a to amplify the differential voltage. After that, φ is selected for YC selected by the Y decoder YDEC.
_y is output and the amplified differential voltage is differentially taken out to the I / O line via the switch SW. The features of this circuit are
As shown in Fig. 8, the I / O line is not taken out on one side, but M
Since it is between A and MA ', high-speed read / write operation can be performed, and since the precharge circuit PC and DC are shared by MA and MA', the area becomes smaller accordingly. Of course, these circuits can be arranged in each MA and MA 'as in the conventional case without making them common. Note that FIG. 18 shows an example in which the power supply voltage V _cc = 5V, and φ _p ,
GCL and GCL 'are 7.5 V because the data lines D ₀ and D ₀
This is because a sufficiently high voltage is applied to ￣ so that the same voltage is precharged. Further, φ _W and φ _DW are set to 7.5 V in order to increase the read voltage from the memory cell by boosting the word line to 7.5 V by the capacitor. A specific circuit for this purpose is well known and therefore omitted in the drawing. The reason why φ _y is 7.5 V is to increase the gm of the MOST in SW so that a signal can be taken out from CD ₀ , CD ₀ ￣ to I / O, I / O ￣ at high speed. The method of boosting φ _y to 7.5 V is unique to the method of the present invention, and therefore is specifically shown in FIGS. That is, conventionally, the data lines D ₀ and D ₀ as shown in FIG.
A circuit as shown in FIG. 19 is used in order to extract the signal from the I / O line at high speed. The drawbacks of this circuit are Q _t and Q _t ￣
That is, the gate voltage of is in a floating state when it is not selected. However, even if it is in a floating state, since the lead line from this gate is short, a coupling voltage appears and Q _t and Q _t ￣ are not turned on although they should have been unselected. However, this circuit cannot be directly used in the present invention. This is because YC becomes a wiring that runs in the memory array for a long time, and the coupling voltage also increases. Therefore, the circuits of FIGS. 20 and 21 may be used. Q
_{Due to 1} and Q ₂ , the unselected YC has a low impedance and becomes the ground potential, so that the coupling voltage hardly appears in the YC.

In FIG. 22, in order to reduce the noise equivalently by making the coupling capacitances of YC and the data pair lines D ₀ and D ₀ ￣ in FIG. 17 equal and making the capacitances of D ₀ and D ₀ ￣ equal. FIG. In the case of a two-intersection cell, even if YC is laid out in the middle of D ₀ and D ₀ as shown in FIG. 10, since the layers are different, D ₀ and D ₀ ￣ due to the mask shift occurring in the manufacturing process. The capacity of each is different, which also becomes a noise source. Therefore, even if a mask shift occurs, YC is made to intersect with one of the data lines in the paired line (D ₀ , D ₀ ￣) an odd number of times (in the figure, once), so that D ₀ , D ₀ ￣
Both can share the capacitance of C ₀ + C ₁ equally. FIG. 23 shows another embodiment, which is an example in which paired lines are crossed an odd number of times.

FIG. 24 shows an example in which SW is controlled only by YC in the embodiments of FIGS. 16 and 17, while SW is controlled by IOC controlled by YC and XDEC. That is, only the SW existing at the intersection of the selected X and Y is turned ON, so that the output can be arbitrarily taken out to I / O0, I / O1 and the like in FIG. This is I in advance
Since it means that / O0 and I / O1 can be decoded, a simplified circuit can be adopted for RWC.

FIG. 25 shows an example in which YC is provided not for each data pair line but for two sets of data pair lines by expanding FIG. By doing so, the number of YC wirings is half, that is, the wiring pitch is doubled as compared with the previous embodiments, so that the manufacturing is facilitated. In the operation of this circuit, only SWs in which IOC0, IOC1 and YC are matched are turned on as in the case of FIG. 24.
0 and IOC1 are different in that they include information on the Y-system address signal in addition to the X-system address signal. That is, when the pair of data lines D ₀ and D ₀ ￣ is selected, when the pair of IOC0 data lines D ₁ and D ₁ ￣ is selected, IOC1 is X and YD.
It is selected by the EC (normally the signal "1" is output). The X-system and Y-system address signals described above are
It goes without saying that it simply means X and Y in the arrangement of the secondary points on a plane and should be distinguished from the logical address of the memory.

It should be noted that here, Y is used for two pairs of data pairs.
Although C is provided, it goes without saying that it can be provided corresponding to any number of pairs of data lines.

FIG. 26 shows another embodiment in which the YC wiring pitch similar to the above is doubled, for example, in this case, I
Two sets of / O lines are provided, and I / O-for CDO and CDO
0, I / O-0￣￣￣￣, CD1, CD1￣￣
The I / O-1 and I / O-1 are connected by SW to exchange signals with the outside. These two sets of I / O lines are connected to Di and Dout by selecting one of them by, for example, the RWC described in FIG. 9, but in addition to this, a plurality of Di and Dout are provided and the selection operation is directly performed. It is also possible to connect to Di and Dout.

Also according to this embodiment, YC as in FIG.
The wiring pitch can be expanded, and the manufacturing becomes different.

Although the above-described embodiments have been based on FIGS. 9, 16 and 17, it is also clear that the X and Y decoders may be arranged close to each other as shown in FIG. FIG. 27 shows an embodiment for that purpose. Here, an example in which the X and Y decoders are shared is shown in the embodiment of FIG. 17 described above, but it goes without saying that the same can be applied to other embodiments.

As shown in FIG. 28, the XDEC and Y-DEC shown in the figure divide the time zone into operations A and Y of the X decoder.
The operation B of the decoder is performed. The outputs φ _xy and φ _x , φ _y are matched by WD and YD, and the outputs of W and YC are formed. Further, in FIG. 27, WD and YD are shown by simple AND symbols, but specifically, they are configured as a circuit as shown in FIG. 20, for example. The W and YD formed as described above are arranged and wired in the same manner as the other embodiments described above, and perform a predetermined operation.

In this embodiment as well, among the problems pointed out in the prior art of FIG. 1, there remains a problem concerning the controllability of the decoder, but it is formed by a conductor of a layer different from W and YC, and is of a two-intersection type. By using the memory cell, the problem of can be solved and the practical value is increased.

In FIG. 27, the XDEC shown on the right side of the drawing does not have the function of a Y decoder, but the number of decoders required for forming YC is within the number of decoders on the left side of the drawing. This is because it is assumed that, and the right decoder may have the same function as the left decoder in some cases. Further, when it is difficult to design WD and YD juxtaposed with each other due to the occupied area, it is possible to distribute the YD circuit to a plurality of decoder sections for design.

29 and 30 are examples for a one-intersection cell or a flip-flop type static memory cell, whereas the above-described embodiments have been intended for a two-intersection cell. The arrangement of XDEC in FIG. 29 will be described. Since a word line of a normal two-intersection cell uses a wiring material having a relatively high resistance (for example, poly Si), the word line delay time becomes a problem. Therefore, in order to keep the time as small as possible, as shown in FIG.
Divide the word line and use an X decoder or driver (X
(DEC is collectively shown). On the other hand, since the word line is formed of A1 having a low resistance in the one-intersection cell, it is not necessary to divide the word line, the XDEC can be arranged at one end as shown in FIG. 29, and the driver is also one on each side. Because it is good, the area can be reduced. Therefore, the position of the XDEC can be changed appropriately according to the memory cell used.

Next, with respect to the arrangement of the peripheral circuits which becomes a problem when the chip is actually designed by using the above-mentioned embodiment, a concrete embodiment directly related to the present invention will be described.

Since universality is emphasized for the memory LSI, the world standard DIP (Dual in Line Package) is used. The longer the chip shape, the easier it is to accommodate in this DIP. On the other hand, the present invention is characterized in that the data lines are subdivided. However, as the data lines are subdivided, the data line direction, that is, the YC direction becomes longer. Therefore, by arranging the memory cells so that the YC direction coincides with the long side direction of the chip, it is possible to design a memory that can be easily accommodated in the DIP. A conceptual diagram of the chip in this case using FIGS. 16 and 17 is shown in FIG. Here, PRC1 and PRC2 indicate an address buffer circuit and other control circuits.

In this case, the YC line is connected to the memory array M.
It will pass over A ₀ ′ but not over the end memory array MA ₀ . If the memory arrays MA ₀ and MA ₀ ′ are arranged with one-intersection cell or a flip-flop type static memory cell, the YC line is arranged in parallel with only one of the paired data lines. The noise from is applied to only one of the paired data lines. However, in the present embodiment, since the two-intersection cell, that is, the folded data line system is used, the YC lines are always arranged in parallel on both of the paired data lines, and the effect of noise from the YC lines is reduced. .

FIG. 32 shows an example in which the pitch of YC is expanded as described above, and a signal and a feeder line different from YC are arranged in the same layer as YC. For example, if this signal is a signal related only to the communication between the peripheral circuits PRC1 and PRC2, the chip area can be reduced because the memory array can be run without increasing the area of the memory array.

[0032]

As is apparent from the above, according to the present invention, a high speed and highly integrated memory can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a conventional example.

FIG. 2 is a diagram for explaining a conventional example.

FIG. 3 is a diagram for explaining a conventional example.

FIG. 4 is a diagram for explaining a conventional example.

FIG. 5 is a diagram for explaining a conventional example.

FIG. 6 is a diagram for explaining a conventional example.

FIG. 7 is a diagram for explaining a conventional example.

FIG. 8 is a diagram for explaining a conventional example.

FIG. 9 is a diagram showing a concept for explaining the present invention.

FIG. 10 is a diagram illustrating a memory cell.

FIG. 11 is a diagram for explaining a memory cell.

FIG. 12 is a diagram for comparing and explaining a conventional example (a) and the present invention (b).

FIG. 13 is a diagram showing an embodiment of the present invention.

FIG. 14 is a diagram showing an embodiment of the present invention.

FIG. 15 is a diagram showing an example of the present invention.

FIG. 16 is a diagram showing an example of the present invention.

FIG. 17 is a diagram showing an example of the present invention.

FIG. 18 is a diagram showing an example of the present invention.

FIG. 19 is a diagram showing an example of the present invention.

FIG. 20 is a diagram showing an example of the present invention.

FIG. 21 is a diagram showing an example of the present invention.

FIG. 22 is a diagram showing an example of the present invention.

FIG. 23 is a diagram showing an example of the present invention.

FIG. 24 is a diagram showing an example of the present invention.

FIG. 25 is a diagram showing an example of the present invention.

FIG. 26 is a diagram showing an example of the present invention.

FIG. 27 is a diagram showing an example of the present invention.

FIG. 28 is a diagram showing an example of the present invention.

FIG. 29 is a diagram showing an example of the present invention.

FIG. 30 is a diagram showing an example of the present invention.

FIG. 31 is a diagram showing an example of the present invention.

FIG. 32 is a diagram showing an example of the present invention.

[Explanation of symbols]

SA ... sense amplifier, YC ... control line, MA ... memory array, W ... word line, D ... data line, MC ... memory cell,
SW ... switch, DC ... dummy cell.

Claims (3)

[Claims] 1. A plurality of word lines, a plurality of data line pairs arranged so as to intersect the plurality of word lines, one word line of the plurality of word lines, and the plurality of data lines. A first and a second memory array of a folded data line system having a memory cell provided in one of two portions where a pair of data line pairs of the pair intersect with each other; The data line pair and the data line pair of the second memory array are commonly provided and are arranged between the data line pair of the first memory array and the data line pair of the second memory array. Common data line pair, first switch means for connecting the data line pair and the common data line pair of the first memory array, the data line pair and the common data of the second memory array. Connect the wire pair Second switch means, an amplifier whose two inputs are connected to the common data line pair so as to amplify a signal appearing on the common data line pair, and third switch means connected to the common data line pair. A common signal line pair connected to the common data line pair via the third switch means, first decoding means for controlling the first switch means and the second switch means, A second decode means for controlling the third switch means; and a control line connected between the second decode means and the third switch means and controlling the third switch means. and will be, the memory cells, and a single capacitor and a single transistor, the data line pair of said first memory array between said second decoding means and the third switching means And the control line is formed by another conductive layer provided via an insulating film on the conductive layer forming the data line pair of the first memory array, and A semiconductor memory device arranged on the first memory array so as to be substantially parallel to the data line pair of the memory array. The semiconductor memory device according to claim 1, wherein the control lines for both data lines with one data line and the other data line of said data line pair of said first memory array A semiconductor memory device, wherein the semiconductor memory devices are arranged so as to have substantially equal coupling capacitances. 3. The semiconductor memory device according to claim 1, wherein the common signal line pair is arranged in substantially the same direction as the plurality of word lines. .