JPH079759B2 - Voice recorder - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a voice recording device for recording voice data in a memory.

[Conventional technology]

The voice recording device is used, for example, built in an electronic wristwatch or the like, and is a device for storing voice data in a memory in the electronic wristwatch as a sound for a time alarm. Conventionally, RAM (random access memory) having a capacity of about 32 Kbit has been used as a memory used for such a purpose. For example, if audio data is sampled at a frequency of 2 KHz using a RAM having this capacity and 4-bit quantized data is recorded at each sampling, the audio data can be recorded for 4 seconds.

[Problems of conventional technology]

The voice recording device as described above has a built-in RAM for about 4 seconds as described above, but it is unlikely that the entire memory is used for voice data used for alarm sound. In addition, memory is wasted when it is not used at all.

[Object of the Invention]

In view of the above-mentioned drawbacks, the present invention provides a voice recording device that enables the voice data storage unit to be used for storing other data such as a name, a telephone number, a schedule, and a timetable. The purpose is to

[Main points of the invention]

According to the present invention, the storage means is divided into areas of variable length so that digital input data and digital audio data are recorded in the respective areas, and the address means is controlled so that the digital input data and the digital input data can be recorded from the respective areas. The digital audio data and the digital audio data are controlled to be selectively read, the read digital input data is displayed by the display unit, and the read digital audio data is output as audio by the audio output unit. When the digital input data is already stored in the storage means, when the digital audio data is to be stored, the use area of the digital audio data is entered up to the use area of the digital input data detected by the detection means, By storing the voice data in the storage means, the digital input data already stored will be erased. And we shall have to have a memory control means for preventing.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In this embodiment, the voice recording device of the present invention is built in an electronic wrist watch.

FIGS. 1 (a) and 1 (b) are diagrams showing the display state of the display unit of the electronic wrist watch. In the same figure (a), (b),
The display unit 1 of the electronic wrist watch is composed of a liquid crystal display element,
The display unit 1 is provided with an address data display unit 1b in addition to the time display unit 1a for displaying the day and time. The address data display unit 1b displays address data stored in a voice recording storage unit (RAM) described later provided in the electronic wristwatch. Also, the address data display section 1b
Shows the RAM address divided into 0 to 60.
When voice data etc. (data such as telephone number to be described later in addition to voice data) is written in the RA, the voice data etc. is written
Display the address on M. For example, in FIG. 1 (a), the total capacity of voice data is set to 60, the voice data is stored in half 0 to 30, and the data of the name and telephone number is 4 on the RAM.
It shows that it is stored in 5 to 60, and that nothing is stored in 30 to 45. Moreover, the same figure (b)
Then the voice data is stored in the RAM at addresses 0 to 45,
Data of other people's addresses and telephone numbers are stored in RAM at addresses 45 to 6
Indicates that it is stored in 0.

The electronic wristwatch having the display unit 1 as described above has a second
It has an electronic circuit as shown.

In the figure, the switches SW _{1 to} SW ₅ are external operation switches provided at locations not shown in the electronic wristwatch, and as described in detail later, by operating the switches SW _{1 to} SW ₅ in combination, the time is adjusted and the sound is output. You can instruct to record (store) and play (read) data and phone numbers. Further, the microphone 2 and the speaker 3 are also provided at locations (not shown) of the electronic wristwatch.

Normally, when displaying the time, the high-frequency signal of the oscillator 4 composed of a crystal oscillator or the like is output to the frequency dividing circuit 5, the high-frequency signal input by the frequency dividing circuit 5 is frequency-divided, and the clock circuit 1 Hz
The signal of is output. The clock circuit 6 converts an input signal of 1 Hz into a time display signal of seconds, minutes, hours, etc., and outputs the time display signal to the display selection unit 7, and when the display selection unit 7 inputs a time mode signal S ₀ described later, This time display signal is displayed on the time display unit 1a of the display unit 1 via the display control unit 8.

Further, when correcting the time displayed on the time display unit 1a is row by operating the switch SW _2, SW _3, SW ₄ described above, and outputs an instruction signal to the input control unit 9 Be seen. That is, the input control unit 9 has a circuit configuration as shown in FIG. 3. For example, when the switch SW ₄ is operated, a pulse signal is output to the ring-shaped shift register 11 via the one-shot circuit 10. . The shift register 11 has a bit area 11a for the time mode, a bit area 11b for the recording / playback mode, and a bit area for the write / read mode.
It has three areas 11c, and the logic "1" sequentially moves in the shift register 11 every time the above-mentioned pulse signal is input. At this time, at the same time, the time mode signal S ₀ , the recording / reproducing mode signal S ₁ , and the writing / reading mode signal S ₂ are output to the above-mentioned display selecting section 7. Therefore, set to logic "1" in bit area 11a of the time mode of the shift register 11 in the case of correcting the time, modified from the decoder unit 10a by operating the switch SW _2, SW ₃ signal l _0, l ₁ Is output to the clock circuit 6. If this correction signal l ₀ is used for digit selection during time adjustment and the correction signal l ₁ is used for actual time adjustment, switch SW ₂ is operated to select the correction digit and switch S
You can adjust the time of the selected digit by operating W ₃ .

On the other hand, in the place where the voice data input from the microphone 2 shown in FIG. 2 is recorded, the switch SW ₄ is operated to operate the shift register 1
Move the logical "1" to the 1 recording / playback bit area 11b.
Then, by operating the switch SW ₂ , the recording signal R
Is output from the input control unit 9 to the amplification / low-pass filter circuit 12, the analog / digital converter (hereinafter referred to as A / D converter) 13, the quantization circuit 14, and the gate 16. Further, the φ ₁ signal (sampling signal) is also output from the input control unit 9 to the address control unit 15 by operating the switch SW ₂ .

Amplification and low-pass filter circuit 12, A to which recording signal R is input
The / D converter 13 and the quantization circuit 14 are in the recording state, and the gate 16 is in the open state.

At this time, when the voice data is output from the microphone 2 to the amplification / low-pass filter circuit 12, the amplification / low-pass filter circuit 12 cuts the high frequency band of the voice data at a predetermined cutoff frequency, amplifies the voice data, and Output to / D converter 13. The A / D converter 13 samples the input audio data at the above-mentioned φ ₁ signal timing. The voltage value of the voice data sampled in this way is converted into a digital value, and is passed through the quantization circuit 13 and the gate 16 to the RAM 17
Is output to.

Further, the φ ₁ signal input to the address control unit 15 is +1 of the address counter via the AND gate 18 shown in FIG. 4 (a concrete circuit diagram of the address control unit 15) when the coincidence signal described later is not output. Address counter 19
The address value of is sequentially incremented. The up count data of the address counter 19 is the address control unit 15
The digital data (voice data) output from the RAM 17 to the RAM 17 and input to the RAM 17 is sequentially written (recorded) from the address 0 of the RAM 17.

Further, the address counter 19 (address control unit 15) also outputs address data that sequentially increases to the display selection unit 7. Since the recording / playback mode signal S ₁ is being input to the display selection unit 7 at this time, the input address data is output to the display unit 1 via the display control unit 8, and the display unit 1 shown in FIG.
The address of the voice data is displayed on the address data display section 1b shown in (b).

On the other hand, when reproducing the voice data recorded as described above, the switch SW ₄ is left as it is (in the recording / reproducing mode and the bit area 11b holds the logic "1"), and the switch SW ₃ is turned on. It is done by operating. When the switch SW ₃ is operated, the reproduction signal P and the φ ₁ signal are output from the input control section 9 as shown in FIG. The reproduced signal P output from the input control unit 9 is input to a gate 20, a decoding circuit 21, a digital / analog converter (hereinafter referred to as a D / A converter) 22, an amplification / low-pass filter 23, and a decoding circuit 21, D / A converter 22, amplification and low-pass filter 23
And the gate 20 is opened.

On the other hand, the φ ₁ signal is supplied to the address counter 19 of the address controller 15 via the gate 18 until a match signal described later is output.
Input to the +1 terminal of. The address counter 19 sequentially increments the address value of the RAM 17 from 0 by inputting the φ ₁ signal. At this time, since the gate 20 is already opened as described above, the voice data in the RAM 17 is sequentially read from the address 0 and input to the decoding circuit 21. Decoding circuit 21
Then, the input voice data is decoded and output to the D / A converter 22.

The D / A converter 22 converts the sequentially input data into an analog signal and outputs it to the amplification / low-pass filter 23. The amplification / low-pass filter 23 sufficiently amplifies the input analog signal (voice data) to a voltage value necessary for operating the speaker 3, and then outputs the voice data to the speaker 3. The speaker 3 outputs the input voice data (signal) to the outside.

Next, the configuration of the function of storing or reading the name and telephone number of another person in the RAM 17 (hereinafter, this function will be referred to as a data bank function) will be described.

First, move the logical "1" in bit area 11c of the write / read shift register 11 by operating the switch SW _4.
Next, the switches SW ₂ and SW ₃ are operated to output the digit selection signal m ₀ and the setting signal m ₁ from the input control unit 9 to the temporary storage register 24. In the temporary storage register 24, when the digit selection signal m ₀ is input, the digit in the temporary storage register 24 is selected. Further, when the setting signal m ₁ is input, the name or telephone number to be stored is input to the digit selected above through a bus line (not shown). By operating the switches SW ₂ and SW ₃ sequentially, the name and telephone number are stored in each digit of the temporary storage register 24.

When writing the name and telephone number temporarily stored in the temporary storage register 24 in this way to the RAM 17, the switch SW ₅ is operated. When the switch SW ₅ is operated, O in the input control unit 9
A signal is output to the R gate 25 and the one-page counter 26, and at the same time, a signal D1 is output from the input control unit 9 to the gate 27 and the address control unit 15. In the gate 27, the gate 27 is opened by the input of the signal D1 and the data of the name and the telephone number in the temporary storage register 24 is output to the RAM 17. Further, the signal D1 input to the address controller 15 is input to the signal D1 and the rising edge detection circuit 28 which detects the rising edge. Rise detection circuit 28
Rising detection circuit in which the rising edge of signal D1 is detected by
The output of 28 is the address counter 19 through the AND gate 30 and the OR gate 31 when there is no output of the number detection circuit 29 described later.
Entered in. The address counter 19 presets the counter value of the counter to the final address, that is, all the bits 1 by this input signal. That is, when the signal D1 rises, the address of the address counter 19 is set to the final address. In addition, the set-reset type flip-flop (hereinafter
(Shown as SR type FF) 32 is set and the output Q is connected to the AND gate 33
Signal is output to AND gate 33, AND gate 42 (Fig. 4)
The φ ₂ signal is input to the −1 terminal of the address counter 19 via. The address counter 19 sequentially subtracts the counter value from the final address by inputting the φ ₂ signal, and writes the name and telephone number data temporarily stored in the temporary storage register 24 to the RAM 17. Therefore, the data of the name and the telephone number are sequentially written in the RAM 17 from the final address.

While the data is being written in the RAM 17 in this way, the above-mentioned one-page counter 26 (this one-page counter 26 is
For example, a counter that has a corresponding counter value when writing the name of one person and the number of digits of a telephone number in RAM and has the same capacity as the temporary storage register) continues counting up, and
When the page counter 26 counts up, the OR gate 41
SR type F.F32 is reset by the signal D2 input via, and the countdown operation of the address counter 19 is stopped. By this operation, the RAM 17 stores, for example, one person's name and telephone number. The address value of the RAM 17 in which the name and telephone number of one person are stored is stored as address data in the temporary storage circuit 35 through the gate 34 which is opened by the signal D2 from the address counter 19. Further, the address value write / reproduction mode signal S ₂ indicator is the input selection unit 7, is displayed in the address data display unit 1b via the display control unit 8.

The count value of the address counter 19 stored in the temporary storage circuit 35 (the address value of one person's name and telephone number stored in the RAM 17) is also output to the match detection circuit 36. This coincidence detecting circuit detects coincidence with the address value of the above-mentioned audio data sequentially stored from address 0 of the RAM 17 input from the address counter 19. That is, R
Data in all storage areas in AM17 (voice data and name,
It detects whether or not the telephone number data) is stored. This coincidence detection signal is sent to the above-mentioned inverter 37 via the inverter 37.
When the audio data is output to the ADN gate 18 and stored in the RAM 17, the φ ₁ signal output from the input control unit 9 is cut off. Therefore, when the storage address of RAM17 is full, the voice data is
I can't remember it in M17. Therefore, the name of the data bank machine,
Your phone number never disappears.

If the area to be stored in the RAM 17 remains, the name and telephone number of the next person are temporarily stored in the temporary storage register 24 using the switches SW ₂ and SW ₃ as described above, and are sequentially input to the RAM 17. Can be stored. However, at this time, since the temporary storage circuit 35 stores the address data when the name and telephone number of the previously input person are stored, the count detection circuit 29 already counts down the addresses in the RAM 17. A signal indicating that is output through the OR gate 37 and the AND gate 30 is closed. Therefore, the address counter 19 is not reset to the final address,
Names and telephone numbers after the first person are stored in sequence.

Finally, reading the circuit constituting the name and telephone number of others written in RAM17, the switch SW ₄ is intact (the bit area 11c of the write / read mode at setting a logic "1"), the switch It is configured by operating SW ₁ . By operating this switch SW ₁ , the signal D ₀ is output from the input control unit 9 to the address control unit 15 and the gate 38, and the gate 38 is opened. Further, the signal D ₀ is input to the rising edge detection circuit 39 and the timer circuit 40 in the address control unit 15. The rising edge of the signal D ₀ input to the rising edge detection circuit 39 is detected, and the address counter 19 is preset to the final address via the OR gate 31 as described above. At the same time, the timer circuit 40 activates the signal D ₀ for 5 seconds, for example.
The SR type FF is set by, and the φ ₂ signal is input to the address counter 19 to sequentially count down the address value of the address counter 19 from 60. At this time, the timer circuit 40 is an intermittent timer and outputs a signal to the AND gate 34 every 5 seconds. Further, the timing for reading out the name and the telephone number of each person one by one is set for these five seconds. For example, when the name and telephone number of the first person are displayed from the RAM 17 on the display unit 1 via the gate 38, the temporary storage register 24, and the display selection unit 7,
After 5 seconds, the name and telephone number of the second person are simultaneously displayed on the display unit 1 via each circuit block. At this time, the data of the displayed name and telephone number is displayed in the timetable time section 1a of the display section 1 instead of the time display.

In this way, the data of the name and the telephone number stored in the RAM 17 are sequentially read, and when the name and the telephone number of the last person are read (the address data of the temporary storage circuit 35 and the above-mentioned reading data). If the address value matches), the A signal
The data is output to the OR gate 41, the SR type F.F32 is reset, and the reading of the data from the RAM 17 is completed.

According to the voice recording apparatus of the present invention having the above circuit block diagram, the voice data input from the microphone 2 can be stored in the voice recording RAM 17 by operating the switches SW ₂ and SW _4. . At the same time, the value on the RAM 17 of the voice data stored in the RAM 17 is displayed on the display unit 1. The address data displayed on the display unit 1 is the first
As shown in FIG. 6A, the number of the displayed data increases from address 0 in the direction of 60 as the voice data is stored.

On the other hand, the operator can confirm whether the voice data is stored in the RAM 17 by visually observing the display unit 1 from the outside. The remaining capacity of RAM17 is judged by this confirmation,
For example, the remaining capacity of the memory as shown in FIG.
If there is 5) or if it is not stored in the voice data at all, the above-mentioned name and telephone number can be stored in the RAM 17 for voice recording.

When to RAM17 to perform data bank functions described above are performed by operating the switch SW ₂ to SW ₅ as described above. At this time, the RAM 17 is also displayed on the address data display section 1b of the display section 1 at the same time.
The name and the address value of the telephone that are stored in are sequentially displayed. Also, this display is from address 60 to address 0
Since the data is moved and displayed, the data bank function may be stopped at the time when the address value of the name, the telephone number, and the address value of the voice data match (FIG. 1 (b)).
Further, in this embodiment, the name and telephone number are RA when the above-mentioned coincidence occurs.
When not all are stored in M17 (for example, when the last digit of the phone number is not entered), the last part of the stored voice can be erased and written over it completely. It is configured to store the missing name and telephone number data.

In this embodiment, the data bank function for storing data other than voice data in the RAM 17 has been described by name and telephone number, but not limited to name and telephone number, for example, a simple message, another person's address, schedule, etc. You may make it memorize | store in RAM.

Further, in this embodiment, basically, the circuit block diagram of FIG. 2 is used to write the data other than the voice into the RAM 17 for voice recording, but the present invention is not limited to the above circuit block diagram and the voice is not limited to the above circuit block diagram. Any circuit having a configuration in which data other than voice in the recording memory can be written can be similarly used.

Further, the voice recording device of the present invention can be used not only in an electronic wristwatch but also in other small electronic devices.

〔The invention's effect〕

As described in detail above, according to the present invention, the storage means is divided into areas having variable lengths, and digital input data and digital audio data are stored in the respective areas,
Further, since the digital input data read from the storage means is displayed and the digital voice data is output as voice, the storage means can be effectively used, and both the output form of voice and display can be selectively selected. You will be able to take it.

In addition, when the storage control unit tries to store the digital voice data when the digital input data is already stored in the storage unit, the storage unit stores the digital voice data up to the use area of the digital input data detected by the detection unit. Since it is possible to prevent the digital input data that has already been stored due to the use area being entered and the digital voice data being stored in the storage means from being erased, the digital input data may be deleted by an erroneous operation on the storage means. It is possible to prevent the erasure from occurring and improve the operability for the user.

[Brief description of drawings]

1 (a) and 1 (b) are configuration diagrams of a display unit according to one embodiment of the present invention, FIG. 2 is a circuit block diagram of one embodiment of the present invention, and FIG. 3 is an input control unit of FIG. FIG. 4 is a circuit diagram of the address controller of FIG. 1 ... Display unit, 1b ... Address data display unit, 9 ... Input control unit, 15 ... Address control unit, 17 ... RAM, 19 ... Address counter, 24 ... Temporary storage register, 35 ... Temporary Memory circuit, 36 ... Match detection circuit, 40 ... Timer.

Claims (3)

[Claims] 1. Input means for supplying digital input data, audio data conversion means for converting an applied audio signal into digital audio data, said digital input data from said input means and said audio data conversion means. Selection means for selectively supplying digital audio data, storage means for storing the digital input data or the digital audio data selectively supplied by the selection means, and an address of the storage means is controlled. By doing so, the storage means is divided into areas of variable length, the address means for storing the digital input data and the digital voice data in each area, and reading from each area, and the address means for controlling The usage state of the area division of the storage means is defined as the usage area of the digital input data. The detection means for detecting the use area of the digital voice data and the address means are controlled to control to selectively read the digital input data and the digital voice data from the area different from the storage means. Read control means, display means for supplying the digital input data read by the control of the read control means and displaying the contents, and digital audio data read by the control of the read control means. A voice output means for supplying a voice output of the contents, and a detecting means for detecting the digital voice data when the digital input data is already stored in the storage means. Up to the usage area of digital input data, the usage area of digital audio data above Voice recording apparatus characterized by the digital audio data is provided with a storage control unit that already prevent the digital input data stored disappears by being stored in the memory means. 2. The address means controls the address so as to store the digital input data from the head or end address of the storage means, and the address so as to store the digital voice data from the end or head address of the storage means. The voice recording device according to claim 1, wherein the area division is performed by controlling. 3. The display means further displays the size of the usage area of the digital data and the usage area of the digital audio data detected by the detection means. The voice recording device according to item 1 or 2.