JP2870742B2 - Voice recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention]   The present invention relates to a voice recording / reproducing device. [Problems of the prior art]   Conventionally, audio waveform data input as an audio recording method
For example 2KH_z, 4KH_zAt a sampling frequency such as
Digital recording method that pulls and records
Have been. However, in this method, the sampling frequency
Each time the volume data must be stored, so
Even when recording, it requires a huge amount of memory
Yes, for example, 2KH_zUsing the sampling frequency of
1 byte capacity at sampling timing
2K bytes of storage capacity, even for 1 second recording
With quantity. [Object of the invention]   This invention records and plays back audio for a long time with little memory.
The purpose is to provide a voice recording / reproducing device that can reproduce
Things. [Gist of the invention]   In order to achieve the above object, the first invention is an external device.
These voices are recognized for each single sound, and each unit of this recognized voice is recognized.
A recognition code corresponding to each sound is output, and when recording voice,
Instead of recording external audio as it is,
Remember the output recognition code,
The stored recognition code is stored in
Converted to audio corresponding to the recognition code and output
The point is.   Also, the second invention recognizes an external sound for each single sound.
Recognition code corresponding to each single sound of the recognized voice.
When recording audio, the external audio is output.
Instead of recording as it is, the output recognition code
Is stored, and the corresponding recognition code is stored.
Displays characters separately for each note. On the other hand, when playing audio,
The stored recognition code is stored in the corresponding recognition code for each single sound.
The audio is converted to the audio corresponding to the
When the voice is reproduced for each single sound, the stored recognition code is used.
Characters corresponding to each mode are displayed for each single note.
And the main point. 〔Example〕   FIG. 1 shows an embodiment in which the present invention is applied to an electronic timepiece.
1 shows an overall circuit block diagram.   The voice recording / reproducing apparatus according to the present embodiment
Recognize the voice for each phone, and for each phone of this recognized voice
Configure speech recognition means to output the corresponding recognition code
And the voice recognition device VR that is
Instead of recording the audio from the
For storing the recognition code output from the recognition device VR.
RAM5 and recording / playback system that constitute
The control unit 3 and the recognition unit stored in the RAM 5 when the sound is reproduced.
A code corresponding to each recognition code
It constitutes a sound reproducing means for converting and outputting to
It has a voice synthesizer VG and a recording / playback control unit 3.
You.   Further, the audio recording / reproducing apparatus according to this embodiment
Display unit 7 constituting display means for displaying characters on crabs
And a character corresponding to the recognition code stored in the RAM 5
A first display system for displaying each sound on the display unit 7
The recording / playback control unit 3 constituting the control means,
At birth, the recognition code stored in the RAM 5
And convert it to a voice corresponding to the recognition code and play it
The voice synthesizer VG and the recording / playback control unit 3 for
When the sound is reproduced for each single sound, the stored recognition
The character corresponding to the code is displayed on the display unit 7 for each single sound.
Recording / reproducing constituting the second display control means for performing
And a raw control unit 3.   Hereinafter, these configurations will be described in detail.   In other words, the illustrated device has functions other than those of a normal electronic timepiece.
Has a sound recording and playback function.
Indicates that the audio signal input from the microphone is
Are recognized one by one, and the resulting voice code
Recorded by writing to voice memory RAM,
To display the corresponding characters on the display unit. In addition, the playback mode
Mode, the audio code in the audio RAM is read out sequentially
Speech signal is sent to the voice synthesizer,
And send it to a speaker to play the audio.
The corresponding character is sometimes displayed on the display unit. Other, fast forward
Mode, rewind mode, etc., and digital recording
However, it looks like a normal tape recorder
It is supposed to work. The details of the operation will be described later.
First, the configuration of the apparatus will be described in detail below.   The oscillation signal from the oscillation circuit 1 is sent to the frequency division timing circuit 2
Is entered. The frequency division timing circuit 2 is a clock for clocking
2H besides sending the signal to the clock circuit 6_zClock (fast forward
In the rewind / rewind mode, the counter CTR
It is used to increase / decrease
You. ) To the address control unit 4, 8H_zClock (see below)
Recording / reproduction control unit 3)
To, 64H_z~ 32H_zAny of the clocks (as described below)
To the recording / playback control unit 3)
Supply.   The key input unit 8 outputs a key input signal via the bus B-2.
Recording mode, playback mode, early
Forward mode, rewind mode, rewind during playback, alarm
Set (automatic address counter preset), stop
Can be entered by key operation, and the clock circuit
I will also do it.   The clock circuit 6 has a normal clock function (clock signal for clock).
And the time is counted, and this time information is displayed on the display unit 7.
The sending time is displayed via the bus B-1. Outside)
-Generate various signals according to each key input from the input unit
You. That is, for the recording input operation, first, from the CC output
Outputs a pulse that clears the contents of the address counter CTR.
And a signal higher than the R output, that is, the recording mode.
And outputs it to the recording / playback control unit 3 for voice recognition.
Send to device VR. For playback input operation, C
Output the playback mode signal of
3 and sent to the voice synthesizer VG. For fast forward input operation
Output a high-level fast-forward mode signal from the F output,
This is sent to the address control unit 4. For rewind input operation
Output a high-level rewind mode signal from the B output,
This is sent to the address control unit 4 as well. Set alarm
The operation of the internal alarm circuit (not shown)
At the time of operation, that is, the alarm time, via the address bus AB-2
Output preset address and output LD
Preset the reset address to the address counter CTR.
Automatically play from that preset address.
Let Further, the clock circuit 6 includes recording / playback / fast forward / rewind.
Mode (when operating as a recording / playback device)
Address) output from the address counter CTR.
Data via the address bus AB-2, and
After decoding, the address value is digitally or
Display a nalog. As a result, the current
Address location, that is, the recorded capacity and the remaining capacity
You can know. In addition, in the recording / playback mode,
The voice code of each single sound recognized by the voice recognition device (voice memory RA
Code written to M5 or input to speech synthesizer
That is, the code read from the voice storage RAM 5.
) Via the data bus DB-5, and
The corresponding character is displayed on the display unit 7 by coding.   Next, the voice recognition device VR uses the signal R in the recording mode.
Operates, receives audio signals from the microphone MC, and silently
Character code, for example, ASCII code
Code (or similar recognition code) to the data bus DB
-3. At the same time, enable indicating completion of single note recognition
The signal of the latch 14 is output via the control line L1 which outputs the signal from the output E.
Send to the CP input and activate the latch 14 to read the recognition code
Latch and output to bus DB-2. Also from output E
The enable signal is also sent to the recording / playback control unit 3.   18 is a 3-state gate for recording / replaying in recording mode.
Enable sent from the raw control unit 3 via the control line L4
Signal operates at (low level) and is on bus DB-2
The recognition code is output to the data bus DB-1. Audio recording RA
M5 is each recognition code from the voice recognition device VR in the recording mode
Each address addressed by the address counter CTR
Stored in the location, and in playback mode the address counter CTR
Therefore, the recognition code stored in the address
And outputs it via the voice synthesizer and the clock circuit 6.
Send it to the indicator 7. That is, RAM5 is in recording mode.
Address from the dress counter CTR via the address bus AB-1.
The dress is designated, and the recording / playback control unit 3 controls the control units L4 and L5.
Write signal (low level) input via
At the same time, a low level select signal is applied to the CS input.
In the voice storage RAM 5 on the data bus DB-1
A recognition code (voice code) is written. Also play
In mode, the ▲ ▼ input is active and the address
With the address specified by the counter CTR, the voice memory R
Recognition code is read out on data bus DB-1 from AM5
This identification code is sent to the latch 16.   The latch 16 is used by the recording / playback control unit in the playback mode.
Enable input to CP input via control line L2 from 3
Latch operation is performed by the signal, and the
Sense code is output on the data bus DB-4 and the speech synthesizer VG is output.
Sent to   The voice synthesizer VG outputs the voice from the RAM 5 through the latch 16
Decodes sequentially read recognition codes and converts them into audio signals
And sends it to the speaker SP via the output line OUT and plays back the sound.
Let it.   Also, during recording and playback, the data bus DB-1
The recognition code sent to the latch 15 is sent to the latch 15.
Appears on the data bus DB-1 in the recording / playback mode.
The recorded speech recognition code is transmitted from the recording / playback control unit 3 to the control line.
When an enable signal is applied to the CP input via L6
To the clock circuit 6 via the fetch data bus DB-5.
Display the corresponding characters on the display
It is. Next, the address control unit 4 and the address counter
The configuration of the CTR will be described with reference to FIG.   The address counter CTR counts the lower three bits A0 to A2.
11, middle 3 bits A3 to A5 counter 10, upper 10 bits
A total of 16 bits consisting of counters A6 to A15
You. Therefore, 32768 words can be stored in the RAM 5. But
The preset inputs of counters 11, 10 and 9 are
Provided by the clock circuit 6 via the sub bus AB-2 and loaded
Preset when signal LD is supplied
I have. The count outputs of the counters 11, 10, and 9 are
As described above, the clock circuit 6 and RA are connected via the address bus AB-1.
Supplied to M5. Recording on the CP input of the lower counter 11
In the recording / playback mode, the control line L5
Is input. Each counter
As described above, the clock input to the LD input
A load signal is input. CL input of each counter
At the start of the playback mode, the clear signal from the clock circuit
Is entered. The C output of the lower counter 11 (carry
The output is sent to the CP input of the middle counter 10 via the OR gate 32,
The C output of the middle counter 10 is sent to the upper
It is connected to the CP input of the counter 9.   The address control unit 4 is provided with a fast-forward mode by a clock circuit.
Mode signal F, rewind mode signal B, and playback mode signal P
2H from frequency division timing circuit 2_zClock is input
It is. That is, the fast-forward mode signal is input to the 2-input AND gate 24.
F and 2H_zA clock is input and its output is a 3-input OR gate.
To the CP input of the upper address counter 9
You. The 3-input AND gate 25 outputs the rewind mode signal B and 2H_zK
Lock and playback mode given via inverter 35
Signal (hence operation disabled in playback mode)
The output is applied to the upper
Input to the CP input of the counter 9. In addition, 3 input AND gate 2
6 includes the reproduction mode signal P and 2H_zClock and rewind signal
Has been entered and therefore the rewind mode during playback
And outputs its output through a two-input OR gate 32
Add to CP input of counter 10. Rewind mode signal B
Is the UD of the upper and middle counters 9 and 10 via the inverter 36
When tied to the input and therefore in rewind mode
Each of these counters performs a countdown operation.   Next, the recording / playback control unit 3 will be described with reference to FIG.
explain. The recording / playback control unit has playback from the clock circuit.
Mode signal P and recording mode signal R frequency division timing circuit
8H from_zClock and 64H_z~ 32KH_zAny of
Clock, indicating completion of single note recognition from speech recognition device
The signal L-1 is input.   That is, the signal P and 8H are applied to the two-input AND gate 23._zclock
Is input (thus operating in playback mode) and its output
Is applied to the three-input OR gate 30. The 2-input AND gate 22
Recording mode signal R and 64H_z~ 32KH_zClock is input
(Therefore, it operates in the recording mode), and its output is 2 input OR
Input to gate 30. The output of OR gate 30 is
D flip-flops (D-FF) 12 and 13
available. Both D-FF12 and 13 constitute a quaternary ring counter
doing. That is, the Q output of D-FF12 is the D input of D-FF14.
In addition, the output of D-FF13 is coupled to the D input of D-FF12.
You.   Further, the two-output AND gate 21 outputs the recording mode signal R, R
Combined with set output Q of S flip-flop (RS-FF) 17
(Therefore, in playback mode and RS-FF17
Operates only when set. ) The output is D-FF1
2, 13 Add to R input (clear input). Therefore 2
During the operation of the input AND gate 21, the D-FFs 12 and 13 are used.
The operation of the ring counter is stopped.   The output of D-FF12 and the Q output of D-FF13 are two-input AND gates.
The output is added to the S input of RS-FF17.
It is. The R input of RS-FF is used for the complete recognition of a single note from the speech recognition device.
Acknowledgment signal L-1. The 2-input AND gate 27 is D
-Combine the Q output of FF12 and the output of D-FF13 and output
Is coupled to the first input of a two-input AND gate
At the data input side of the RAM via the control line L6
Connected to CP input of latch 15. 2-input AND gate 19
Is coupled to the playback mode signal P (but
Operates in the playback mode), and outputs the output via the control line L2.
Applied to the CP input (latch operable input) of latch 16. D
The output of −FF12 is the ▲ ▼ input of RAM5 (chip select signal
) And the CP input of the lower counter 11 (clock signal and
And then sent to).   The 2-input OR gate 29 is connected to the Q output of the D-FF12 and the inverter.
33 and the recording mode signal from the clock circuit.
(Therefore the output is low active)
Output only when in recording mode)
In addition to the CP input (enable at low level)
You. The two-input AND gate 20 outputs the output of the AND gate 27 and the R signal.
Is input (and thus works in recording mode) and its output
Is the input of RAM5 via the inverter 34 control line L3.
(Active at low level). AND gate 2
The output of 7 is latched via the control line L6 (data of the clock circuit).
(Latch on the data input side).   The operation of the device having the above configuration will be described below. Recording mode   This mode is selected by operating the key input unit 18.
In this case, an R signal, that is, a recording mode signal
(High level) appears. This R signal allows the speech recognition device
3 operates, and each single sound of the sound input from the microphone 1 is
E-pulse indicating recognition completion and recognition each time recognition is performed
Code is output. Therefore, the latch 14 operates
And latch output (recognition code) on data bus DB-2
put out. At the same time, the E pulse is the RS of the recording / playback control unit.
-Reset FF. As a result, the AND gate 21 closes,
Clear input of D-FF12 and 13 which constitute the quaternary ring counter
Since the force R becomes “0”, both flip-flops are reset
The state is released and operation as a ring counter starts.
You. FIG. 4 shows a timing chart of this operation. Immediately
When the timing is as shown in FIGS. 4a and 4b, D-FF12 =
0, the output of the OR gate 29 is low when the playback mode signal R = 1.
The bell becomes a bell and the 3-state gate 18 opens, and the data bus DB
The recognition code is output on -1. Similarly, timing
In the case of a and b, D-FF12 = 0 and the control line L5 is low level
And the chip selection input CS of the audio memory RAM5 is active
Becomes At timing a, D-FF12Q = 1, DF
When F13 = 1, AND gate 27 opens and recording mode
And the AND gate 20 is open. Therefore, control line L3
Becomes low level, and the write input of the voice storage RAM5 ▲
▼ becomes active. Therefore, address counting
Data bus DB at the location specified by the
-1 recognition code, for example, a character that recognized the phoneme "A"
The ASCII code of A is written. At the same time, control
A signal is applied to enable input CP of latch 15 via line L6.
Therefore, the recognition code is decoded through the clock circuit 6.
Character corresponding to a single sound (phoneme) recognized by the display unit 7, eg
For example, A is displayed. RAM addressed at this time
In the memory location, that is, the count value of the address counter CTR
(Binary data) is clocked via the address bus AB-1.
Converted to decimal via road 6 and displayed by display 7
Display the address value. Therefore, the user
For voice input to the
Errors can be visually confirmed, and the single note is written
To know where it is stored in RAM.   Also, the lower counter 11 of the 16-bit address counter CTR
D-FF12 (negative pulse) is
Between timings b and c (negative pulse
Of the address bus AB-
Output next address (= current address + 1) on 1
You. Further, at timing C, D-FF12 = 1, D-FF13
When Q = 1, the AND gate 28 is opened, RS-FF17 is set, and AN
The clear input is applied to both D-FFs 12 and 13 (link
Counter). Therefore, the ring counter
Is activated until the next recognition code is output from the voice recognition device VR.
Stop working.   The above operation is repeated every time the next recognition is completed.
And the audio information is stored in a continuous storage area in RAM.
A series of sound code strings are stored, and voice recording is performed. Play mode   In this mode, the clock circuit 6 outputs a high-level P signal.
, Ie, a reproduction mode signal. Also start playback
Occasionally, a one-shot clear signal CC is output from the clock circuit 6.
To clear the address counter CTR and
Is set to address 0. The recording / playback control unit 3 includes the above
Signal and 8H from the frequency divider timing circuit 2_zclock
Signal is input, and the signal is input through an AND gate 23 and an OR gate 30.
Each clock input of the quaternary ring counter (D-FF12 and 13)
8H for CP_zSupply clock. Therefore, D-FF12
2H by the output of_zClock is RAM5 chip select input
▲ ▼ and lower counter 11 of address counter CTR
Clock input CP. Therefore, the address
Is incremented by one every half second, and
The recognition code is read out every half second, and
Switch 16 also latches the code read every 1/2 second.
And supplies it to the speech synthesizer VG. As a result, the speech synthesizer
The corresponding audio signal is sent to the speaker SP
And the sound is reproduced at a rate of two characters / second. With latch 16
In synchronization with this, the latch 15 also latches the code read from the RAM.
Then, the character corresponding to the display unit 7 is
It is displayed sequentially in units of sound / second. Also read from RAM
Memory location to be issued, that is, address counter CTR count
The display value is also displayed on the display unit 7 via the clock circuit 6 (tape value).
Like the tape counter of a precoder,
Increase). Therefore, the user can use the speaker SP
Is output in units of single phone (phonemes)
It can be recognized through the displayed characters. When rewinding during playback   In this case, in addition to the P signal output from the clock circuit, B
A signal is output. Therefore, the address control unit 4
Signal from the gate 36 is a down signal.
To the up / down input UD of counters 9 and 10,
The und goes into the down mode. Gate 26 opens
And 2H_zClock signal is the middle bit (A3 to A5)
8 counts at a relatively low speed
Rewind. In the configuration shown in the figure,
And the recording / playback control unit 3 operates.
However, the operation may be prohibited.
The 2-input AND gate 23 in the control unit 3 is replaced with a 3-input AND gate
And the third input (additional input) is a signal (inverter
To the B signal). Preset auto play mode   This mode is activated when an alarm time is detected in the clock circuit.
Enter the code. In this mode, the clock circuit 6
Signal, that is, the load signal of the counter,
Preset address data, i.e.
Address data to start playback from the area
Load counter LD input and preset data input
Added to power. Therefore, the address counter CTR is R
On address bus AB-1 connected to AM5 (and clock circuit)
Output the preset address. This address
Playback is performed. That is, in the playback mode described above,
Is played from the top address. In this case,
Indicates that the playback start address is a preset address.
You. Except for this difference, the playback mode and operation described above are the same.
Therefore, further description is omitted. Fast forward mode   In this mode, the F signal from the clock circuit 6, that is, the fast-forward mode
A code signal is output. In this case, the recording / playback control unit 3
Has no effect on the operation. Then, the address control unit 4
F signal is 2H_zInput with clock signal and AND
Counter 24 and OR gate 31, the upper 10-bit counter 9
Clock input CP. Therefore, 16 bits
64 counters per clock signal
And fast forward. And 64 via the address bus
Address signal (counter value) incremented by 1
Is input to the clock circuit and displayed on the display unit 7 in decimal. Rewind mode   In this mode, the clock circuit 6 outputs a high-level B signal,
That is, a rewind mode signal is output. Recording /
Playback control is not involved in the operation and address control
B signal and 2H in part 4_zA clock signal is input. That is,
The B signal is the address of the upper 10 bits via the inverter 36
Apply a low-level signal to the U / D input of the counter,
Operate as a down counter. B signal and 2H_z
The clock signal passes through the AND gate 25 (at this time, the P signal
Is a low level and a high level signal via the inverter 35
Is added to the remaining inputs of this gate), and
Upper 10-bit address counter 9 via OR gate 31
2H to clock input CP of_zClock signal. did
As a result, the entire address counter is counted by 64 counts.
The default value goes down and rewinding is performed. Indication of rewind
Calculates the count value on the address bus via the clock circuit 6.
This is performed by sending to the display unit 7. Stop   When stop is instructed by key operation, the clock circuit
The signals that were output before (eg, R signal, P signal, B signal,
Or F signal) disappears, and recording /
Each device of the playback device is stationary. For example, recording mode
Stop on the address bus AB-1 at the time of stop.
(Count value) on the data bus DB-5
Is displayed on the display unit 7 for recording / playback control.
And the address control unit are stopped. If there is an error in voice recognition during recording   For example, despite the sound of "A" being put into the microphone MC
And the speech recognition device mistakenly recognizes
You. In such a case, the character 0 is displayed on the display unit 7.
Therefore, the user can know that there is a misperception.
At the same time, the location where the misidentification code was written in RAM5 is also displayed.
You can know through the department. That is, the address counter CT
R count value (RAM address) is bus AB-1, clockwise
This is displayed on the display unit 7 through the road, so that
You can know. Therefore, stop and rewind modes
Mode, stop operation, and then enter recording mode again.
By doing so, a corrected recording can be made.   However, the device shown is fast rewind (64 counts
And replay from the top address
Therefore, it is somewhat inconvenient for correction. To make corrections easier,
For example, if you identify a misidentification,
Let the user rewind, and at some point (the user
Rewind until you can confirm from the count value on the display), then
The play key operation (not the top address)
Play back from the rewind address and confirm by the user
Stop where possible (eg, syllable breaks)
Recording operation from, you can record for correction
What is necessary is just to comprise. For slow rewind, the address
Low-speed clock input to lower counter 11 of counter CTR
You only need to insert a clock to play from the rewind position
Goes to the address counter described in the playback mode.
Of the clear signal CC from the clock circuit (for example,
Using a gate).   One of the features of the embodiment described above is that the actual situation is different.
It looks like a normal tape recorder
And it is very easy to use.   The present invention is not limited to the above-described embodiment, but may be variously modified and changed.
Is possible.   In this embodiment, the term "single sound" is used in principle.
Means the unit of the speech recognition result of the high-temperature recognition device
Used in. 〔The invention's effect〕   As can be understood from the above description, according to the first invention,
For example, when recording audio, the external audio is stored as it is.
Instead of using voice recognition, external voice
After recognizing each sound, a pair is recognized for each sound of this recognized voice.
Since the corresponding recognition code is stored,
Very little memory compared to storing
With the capacity, can recognize the recognized recognition code
You. On the other hand, when the sound is played, the stored recognition code
Can be converted to the corresponding audio and played.
Thus, external sound can be reproduced faithfully.   According to the second invention, the field of the first invention described above is provided.
Not only can you achieve the same effect as
Recognition code corresponding to external voice when recording voice
While the characters corresponding to
At the time of birth, the stored recognition code is divided into
When converting to the voice corresponding to the recognition code and playing
A character corresponding to the stored recognition code,
Since it is displayed separately, the displayed voice response
The voice of any content is memorized from outside through the characters
And what kind of audio was played
Can be confirmed visually as well as auditory.
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of an embodiment in which the present invention is applied to an electronic timepiece. FIG. 2 is a diagram showing a configuration example of an address control unit and an address counter in FIG. FIG. 3 is a diagram showing a configuration example of the recording / reproduction control unit of FIG. 1, and FIG. 4 is a time chart relating to storage of a single sound in the recording mode. 2 ... frequency dividing timing circuit, 3 ... recording / playback control unit,
4 Address control unit, 5 Voice memory RAM, 6 Clock circuit, 7 Display unit, 8 Key input unit, CTR Address counter, VR Voice recognition device, VG Voice Synthesizer, MC ... microphone, SP ... speaker.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G10L 3/00

Claims (1)

(57) [Claims] Voice recognition means for recognizing an external voice for each phone and outputting a recognition code corresponding to each phone of the recognized voice; and when recording the voice, instead of recording the external voice as it is, the voice A recognition code storage unit for storing a recognition code output from the recognition unit; and, when reproducing a voice, converting the recognition code stored in the recognition code storage unit into a voice corresponding to the recognition code for each single sound. An audio recording / reproducing apparatus, comprising: audio reproducing means for reproducing. 2. Voice recognition means for recognizing an external voice for each phone and outputting a recognition code corresponding to each phone of the recognized voice; display means for displaying characters; and Instead of recording as it is, a recognition code storage means for storing a recognition code output from the voice recognition means, and a character corresponding to the recognition code stored in the recognition code storage means is displayed on the display means for each single sound. First display control means; and voice reproduction means for converting a recognition code stored in the recognition code storage means into a voice corresponding to the recognition code for each single sound when reproducing the voice, and reproducing the voice. When the sound is reproduced by each sound by the reproduction means, the character corresponding to the recognition code stored in the recognition code storage means is displayed on the display means by each sound. 2
And a display control unit.