JPS6228999A - Sound recording device - Google Patents

Abstract

PURPOSE:To clarify the remaining capacity of a sound recording memory and to aim at the effective use of the memory by writing sound data and the data other than that on the memory starting from the both ends of an address. CONSTITUTION:A sound signal from a microphone 2 is quantized 14 by the operation of switches SW2 and SW4, and also an address control 15 is performed on it, the sound data storing on an RAM17. According to the increase of the stored data, a corresponding address data re displayed at a display part 1. With confirming the data at the display part 1, an operator decides the remaining capacity of the RAM17. And by operating the switches SW2-SW5, the data of a name and a telephone number temporaily stored at a storage register 24 is stored on the RAM17. At such a time, the address is indicated from the last address to a high-order one on the RAM17, displaying the indicated address value at the display part 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an audio recording device that records audio data in a memory.

[Traditional technique]

A voice recording device is a device that is built into, for example, an electronic wristwatch and is used to store voice data in the memory of the electronic wristwatch as, for example, a sound when a time alarm occurs. Conventional 1
A RAM (Random Access Memory) having a capacity of about 32 Kbits is used as a memory for this purpose.

For example, if a RAM having this capacity is used to sample audio data at a frequency of 2KIIz and 4-bit quantized data is recorded for each sampling, audio data can be recorded for 4 seconds.

[Problems with conventional technology]

The voice recording device described above has a built-in RAM of approximately 4 seconds as described above, but it is rare that the entire memory is used for voice data used for alarm-like sound.

Furthermore, memory is wasted when it is not used at all.

(Object of the Invention) In view of the above-mentioned drawbacks, the present invention provides an audio data storage unit that enables the storage unit for audio data to be used for storing other data, such as two names, telephone numbers, schedules, timetables, etc. The purpose is to provide recording equipment.

[Key points of the invention]

The present invention stores audio data and data other than audio data in the audio recording memory by writing audio data and data other than audio data into the audio recording memory from both addresses h::h of the memory. At the same time, the purpose is to clearly indicate the remaining capacity of the audio recording memory.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In this embodiment, two voice recording devices of the present invention are built into an electronic wristwatch.

Figure 1 ti11. (b) is a diagram showing the display state of the display section of the electronic wristwatch. Same 11'! ](a), (
In b), the display section 1 of the electronic wristwatch is composed of a liquid crystal display element, and the display section 1 is provided with an address data display section 1b in addition to a time display section 1a on which the day of the week and time are displayed. This Al-Resdake display section 1b includes a voice recording storage section (RAM) provided in the electronic wristwatch, which will be described later.
) is displayed. In addition, the address data display section 1b displays the address of the RAM divided into 0 to 60, and when audio data etc. (in addition to the audio data, data such as a telephone number which will be described later) is written to the RAM, Displays the address on the RAM where audio data etc. are written. For example, in Figure 1 [a], the total capacity of voice data is 60, the voice data is stored in half 0 to 30, and the data of 3 names and telephone numbers is stored in 45 to 6 on the RAM.
This shows that 0 is stored, and nothing is stored between 30 and 45. In addition, 2 the same figure (b
), voice data is stored in addresses 0 to 45 on the RAM, and data of other people's addresses and telephone numbers are stored in addresses 45 to 60 on the RAM. Indicates that the

An electronic wristwatch having the display section 1 as described above has a second display section inside.
It has an electronic circuit as shown in the figure.

In the figure, switches S W l - S W v are external switches installed at locations not shown in the electronic wristwatch, and as will be described in detail later, each switch S W l - S W v
By operating 5 in combination, it is possible to instruct time adjustment, recording (memory) and playback (reading) of voice data, telephone numbers, etc. Further, a microphone 2 and a speaker 3 are also provided at locations not shown in the electronic arm 19.

Normally, when displaying two times of day, a high frequency signal from an oscillator 4 composed of a crystal oscillator etc. is output to a frequency divider circuit 5, and the high frequency signal inputted by the divider by two circuit 5 is divided and sent to a clock circuit 6. I
Outputs a Hz signal. The clock circuit 6 converts the IHz input signal into a time display signal such as 9 minutes and 1 o'clock, and outputs it to the display selection section 7. When the 1 display selection section 7 receives a time mode signal So, which will be described later, This time display signal is displayed on the time display section 1a of the display section 1 via the display control section 8.

Moreover, when correcting the time displayed on this time display section 1a, the above-mentioned switch SW2 is used.

SW3. Make SW4 a masterpiece and be on the power side! This is done by outputting an instruction signal to the 11 section 9. That is, the input control section 9
has a circuit configuration as shown in FIG. 3. For example, when switch SW 4 is activated, a pulse signal is outputted to ring-shaped shift register 11 via one-shot circuit 10. The shift register 11 has a bit area 11a for time mode.

Bit area 11b for recording/playback mode, write/
It has three areas of bit area llc for successive mode, and every time the above-mentioned pulse signal is input, the logic
1'' is sequentially moved in the shift register 11. At this time, the time mode signal So is simultaneously activated.

A recording/playback mode signal S+ and a write/continue mode signal S2 are output to the display selection section 7 described above. Therefore, when adjusting the time by 1, set a logic "1" to the time mode pin I/area lla of the shift register 11, and switch SW2. By operating SW3, the decoder section 10a outputs the modified signal ρ0. ρi is output to the clock circuit 6. Also, this correction signal flo is used for digit selection when adjusting the time.

If the correction signal II is used for actual time correction, operate switch SW2 to select the correction digit, and then switch SW3.
You can adjust the time of the selected digit by operating .

On the other hand, when recording audio data input from the microphone 2 in FIG.
] ”. Then, by operating the switch SW 2, the recording signal R is transferred from the input control section 9 to the amplification/low-pass filter 2 circuit 12 and the analog/digital converter (hereinafter referred to as Δ/D converter) 13. .Quantization circuit 1
4. Gate] 6. Further, by operating the switch SW2, the φ1 signal (sampling signal) is also output from the input control section 9 to the address control section 15.

Amplification and low-pass filter circuit 12 into which the recording signal R is input
．． to/D converter 13. The quantization circuit 14 is in a recording state, and the gate 16 is in an open state.

At this time, the audio data from microphone 2 is amplified and low-pass filtered 1? &12, the amplification and low-pass filter circuit 12 cants the high frequency range of the audio data at a predetermined cutoff frequency, amplifies the audio data, and outputs the audio data to the A/D converter 13.

The Δ/D converter 13 samples the input audio data at the timing of the aforementioned φ1 signal.

The voltage value of the audio data thus sampled is digitized and output to the RAM 1.7 via the quantization circuit 13 and the gate 16.

Further, when the coincidence signal, which will be described later, is not output, the φl signal input to the address control unit 15 is input to the A N D data 1 shown in FIG. 4 (specific circuit diagram of the address control unit 15).
8 to the +1 terminal of the address counter 2 and sequentially counts up the address value of the address counter 19. This address power unku 19 asop count 1-
Data is output from the address control unit 15 to the RAM 1.7, and the digital data (audio data) input to the RAM 17 is sequentially written (recorded) from address 0 of the RAM 17.

Also, a) response counter 19 (A+” response control unit 1
5), sequentially increasing address data is also output to the display selection section 7. In the display selection section 7.

At this time, since the recording/playback mode signal S1 is input,
The input address data is output to the display section 1 via the display control section 8, and the address of the audio data is displayed on the address data display section 1b shown in FIGS. 1(a) and 1(b).

On the other hand, when playing back the audio data recorded as described in -1- above, the switch SWa is left as is (with the bit area Ilb in the recording/playback mode holding logic "1"), and the switch SW3 is This is done by manipulating the . When the switch SW3 is operated, the reproduction signal P and the φ1 signal are outputted from the input control section 9 as shown in FIG. The playback signal P output from the input control section 9)2
0° decoding circuit 21. Digital/analog converter (hereinafter referred to as 1/Δ converter) 22. It is input to an amplification and low-pass filter 23, and a complex circuit 21. The tFIIm/low-pass filter is set to the 23rd state and the gate 20 is opened.

On the other hand, the φ (signal is inputted to the G1 terminal of the address counter 19 of the address control unit 15 via the gate 18 until a match signal, which will be described later, is output. By inputting this φ1 signal, the address counter 19 inputs the address value of the RAM 17. O
The count increases sequentially from At this time, since Goo 1-20 has already been opened as described above, the audio data in RA and M17 are sequentially read out from address O and sent to the decoding circuit 21.
Enter. The decoding circuit 21 decodes the input audio data and outputs it to the D/A converter 22.

The D/A converter 22 converts the sequentially input data into analog signals and outputs them to the amplification/low-pass filter 23 . The amplification/low-pass filter 23 sufficiently amplifies the input analog signal (audio data) to a voltage value necessary to operate the speaker 3, and then outputs the audio data to the speaker 3. Speaker 3: Outputs the input audio data (signal) to the outside.

Next, the configuration of a function (hereinafter referred to as a data bank function) for storing or reading another person's name and telephone number in the RAM 17 will be explained.

Shift register 1 by operating switch S W a
Logic “1” in bit area Ilc for writing/reading of 1
move. Next, the input control section 9 outputs the digit selection signal mO and the setting signal m1 to the temporary storage register 24 by operating the switches SW2 and SW3. -Special note: The digit of the temporary storage register 24 is selected by inputting the digit selection signal mo to the la register 24. Furthermore, the setting signal m1
When you enter .

The name and telephone number to be memorized are entered into the digits selected above via a lot line (not shown). Sequential switch SW
2. By operating SW3, the temporary memory register 24
The name and phone number are stored in each digit.

When writing the name and telephone number temporarily stored in the temporary memory register 24 in this way to the RAM 17, switch 5
Operate Vl15. When switch SW5 is operated,
OR gate 25.1 page count 2 in input control section 9
A signal is output to gate 27.G from input control section 9. A signal D1 is output to the address control section 15. In Goo I.27, the gate 27 is opened by the input of the signal D1, and the name and telephone number data in the temporary storage register 24 mentioned above are output to the RAM 17. In addition, the address control unit 1
The signal D1 input to the circuit 5 is input to a rising edge detection circuit 28 which detects the rising edge of the signal DI. The output of the rising edge detecting circuit 28 when the rising edge of the signal D1 is detected by the rising edge detecting circuit 28 is as follows.

When there is no output from the number detection circuit 29, which will be described later, the AND gate 30. Address counter 1 via OR gate 31
9 is input. In the AT/counter 19, this input signal presets the counter value of the counter to the final address, that is, all bits are 1. That is, when the signal D1 rises, the address of the address counter 19 is set to the final address. In addition, the center reset type flip-flop (hereinafter referred to as SR type F, F) 32 is set by the signal inputted to the OR gate 25 in FIG.
D gate 33. Through the AND gate 42 (FIG. 4),
The φ2 signal is input to the 11 terminal of one address counter. In the case of a single address counter, the counter value is sequentially incremented from the last address by the input of this φ2 signal.
Temporarily write ↑ to M17 to L and R, and write the name and telephone number data temporarily stored in the a register 24. Therefore, R.A.
Name and telephone number data will be sequentially written into M17 starting from the final address.

While the data is being written to the RAM 17 in this way, the aforementioned 1 page counter 26 (this 1 page counter 26 stores 1, for example, the number of digits of one person's name and telephone number)
When the page counter 26 counts up, the counter (which has a counter value corresponding to the counter value when inputting K and has the same capacity as the temporary storage register) continues to count up. , F32 are reset, and the countdown operation of the address counter 19 is stopped. By this operation, the RAM 17 stores, for example, the name and telephone number of one person. Further, the address value of the RAM 17 in which the name and telephone number of this one person are stored is stored as an address control section from the address counter 19 into the temporary storage circuit 35 via the gate 34 which is opened by the above-mentioned signal D2. It is heard. Additionally, this address value is
The reproduction mode signal S2 is displayed on the address data display section 1b via the display selection section 77 and the display control section 8.

Address counter 1 stored in the circuit 35
The count value of 9 (the address value of one person's name and telephone number stored in the RAM 17) is also output to the minus number output circuit 36. This minus number output circuit 36 detects a match with the address value of the aforementioned audio data inputted from the address counter 19 and stored sequentially from address 0 in the RAM 17.

That is, it is detected whether data (voice data, name, and telephone number data) is stored in all storage areas in the RAM 17. This minus number output signal is output to the above-mentioned AND gate 18 via the inverter 37, and when the audio data is stored in the RAM 17, the φl signal output from the input control section 9 is cut off. Therefore, when the storage address of RAM 1.7 becomes full, audio data cannot be stored in RAM 17. Therefore, the name and telephone number of the data bank machine will not disappear.

If there is space left in RA and M17, the name and telephone number of the second person are stored in the temporary storage register 24, and the switch SW2. -θjM can be stored using SW3, and can be sequentially input to the RAM 17 and stored. However, at this time, the temporary memory circuit 35 stores the address data when the name and telephone number of the person previously entered are stored. a, so the number detection circuit 29
A signal indicating that the address has already been counted down to the RAM 17 is outputted via the OR gate 37.

The ΔND gaming 30 is brought into a closed state. Therefore, the address counter 19 sequentially stores the names and telephone numbers of the second and subsequent persons without being reset to the final address.

Finally, the circuit configuration for reading out the other person's name and telephone number written in RAM 1.7 leaves the switch SWa as is (
Logic “
1"), the switch SW1 is set to 1".

By operating this switch SWl, a signal D[ is outputted from the input control section 9 to the address control section 15 and the gate 38, and the gate 38 is opened. Also.

This signal Do is applied to the rising edge detection circuit 39 in the address control section 15. and input to the timer circuit 40.

The rising edge of the signal Do input to the rising edge detection circuit 39 is detected, and the address counter 19 is preset to the final address via the OR gate 31 as described above. At the same time, the timer circuit 40 is activated for 1, for example, 5 seconds.
The SR types F and F are set by the signal Do, and the φ2 signal is input to the address counter 19, and the address value of the address counter 19 is sequentially decremented by 1 from 60. At this time.

The timer circuit 40 is an intermittent timer and outputs a signal to the ND group 1-3/I every 5 seconds. Also, during these 5 seconds, the timing is set without reading out the name and telephone number of each person. For example, the first person's name and phone number are from RAM17 to +-38.

-Special note 1. When the name and telephone number of the second person are displayed on the display section 1 via the display selection section 7 of the Kirisuku 241, the name and telephone number of the second person are similarly displayed on the display section 1 via the respective circuit blocks five seconds later. The name and telephone number data displayed at this time 2 are displayed on the time display section 1a of the display section 1 instead of the time display.

In this way, the name and telephone number data stored in the RAM 17 are sequentially read out, and when the last person's name and telephone number are read out (the address data in the temporary storage circuit 35 and the (if the address value matches),
A signal is output to the OR gate 41, and the SR type F, F32
Reset.

Reading of data from RAM 17 is completed.

According to the audio recording device of the present invention having the circuit block diagram as described above, audio data input from the microphone 2 can be stored in the audio recording RAM 17 by operating the switches SW 2 and S'Wa. I can do it. Also,
RAM 17 for audio data stored in RAM 47 at the same time
The upper value is displayed on the display section 1. The address data displayed on the display section 1 is increased in the 60 direction from the address O as the audio data is stored, as shown in ta+ in FIG.

On the other hand, the operator can check whether audio data is stored in the RAM 17 by visually observing the display unit 1 from the outside. This check determines the remaining capacity of the RAM 17.9 For example, if there is remaining memory capacity (30 to 45) as shown in the same figure (a+), or if no audio data is stored at all, the RAM17 for recording
can store the aforementioned name and phone number.

When the RAM 17 is to perform the two-speed data bank function, the switches SW2 to SW5 are operated as described above. At this time as well, the address data display section 1b of the display section 1 sequentially displays the name and telephone address value stored in the RAM 17. Also, since this display is sequentially moved from address 60 to address 0, when the address value of one name and telephone number matches the address value of voice data (Fig. 1 (b)), the data All you have to do is stop the bank function. In addition, in this embodiment, when the full name and telephone number are not stored in the RAM 17 at the time of the coincidence described above (for example, when the last digit of the telephone number has not been input), the last part of the stored voice is used. is configured to erase the name and store the name and phone number that could not be completely written on it.

9 In this embodiment, the data bank function for recording data other than audio data in the RAM 17 was explained using names and telephone numbers. .

The scheduler and the like may be stored in the RAM.

Furthermore, in this embodiment, data other than audio is written to the RAM 1.7 for audio recording using basically the circuit block diagram shown in FIG. However, any circuit that can write data other than audio into a memory for audio recording can be used in the same manner.

Furthermore, it goes without saying that the voice recording device of the present invention can be used not only for electronic wristwatches but also for other small electronic devices.

〔Effect of the invention〕

As described in detail above, according to the present invention, data other than audio data can be stored in the audio recording memory in the audio recording device.

Also, since audio data and data other than audio data are stored in this memory sequentially starting from the addresses at both ends of the memory, in principle it is not possible to delete stored data and store new data. do not have.

Furthermore, since the address values of the audio data and data other than the audio data stored in the memory are displayed on a display unit or the like, the remaining capacity of the memory can be easily checked and the memory can be used effectively.

[Brief explanation of drawings]

FIG. 1 (11+, fb) is a configuration diagram of a display section according to an embodiment of the present invention. FIG. 2 is a circuit block diagram of an embodiment of the present invention. FIG. 3 is a circuit diagram of the input control section of FIG. 2. FIG. 4 is a circuit diagram of the address control section of FIG. 2. 1...Display section. 1b...Address take display section. 9...Input control section. 15...Address control section. 17...RAM. 19...Address count. 24...Temporary memory register. 35...Temporary memory down circuit. 36...-Number construction circuit. 40...Timer. Patent Applicant Casio Computer Co., Ltd. Figure 1 (a) h Figure 1 (b)

Claims (1)

[Claims] storage means for storing audio data and data other than the audio data; address control means for causing the storage means to store the audio data and data other than the audio data from the beginning or end address of the storage means; and the storage means 1. A voice recording device comprising display means for displaying the storage capacity of the voice data and data other than the voice data stored in the voice recording device.