JPH0795265A - Signal selecting circuit - Google Patents

Abstract

PURPOSE:To switch a current signal system to the normal standby system as soon as possible according to the fault generation in the current main signal system by selecting the normal signal system to be selected next by a means for forming the next selection signal. CONSTITUTION:A signal selecting means 2 selects the normal signal system as a current system of the plural main signal systems according to the selection signal held by a storage means 1. A means 3 forming the signal to be selected next forms the selection signal of the normal signal system to be selected next based on the alarm signal of each signal system. When an alarm signal is detected in the active signal system, a selector 4 outputs an alarm signal and sets the next selection signal of the means 3 forming the next selecting signal to the storage means 1. According to the selection signal, the signal selecting means 2 switches the main signal system. Thus, even when a fault is generated in the active main signal system, the signal system can be switched to the normal standby main signal system as soon as possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal selection circuit, and more particularly to a signal selection circuit for selecting and outputting a normal one of main signals of a plurality of signal systems based on alarm signals of a plurality of signal systems. Regarding the circuit. For example, in a communication system, for the purpose of safety of system operation, a plurality of clock signal systems are prepared in advance, and this is switched to a spare clock signal system when a failure occurs in the current clock signal system.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional signal selection circuit, in which 10 is a clock signal generator (CG),
0 ₁ and 10 ₂ are clock signal generation blocks (CG
A, CGB), 10 ₃ and 10 ₄ are alarm state detection blocks (CMA and CMB), 12 and 14 are selectors (SEL), and 16 is a counter circuit (CTR).

Clock signal generation block 10₁Are the same
4 systems of clock signal CA₀~ CA ₃Occurs (or re
Clock signal generation block 10₂Also
The same four clock signals CB as above₀~ CB₃From
It is live (or regenerated). On the other hand, the alarm status detection
Lock 10₃Is the clock signal CA₀~ CA₃Each system related to
Monitor for abnormalities, and detect abnormalities in either system.
And the corresponding alarm signal EA₀~ EA₃From
To live. Also, alarm state detection block 10_FourAs well
And clock signal CB₀~ CB₃In any system related to
When an abnormality is detected, the corresponding alarm signal EB₀~ EB₃
To occur.

The counter circuit 16 is reset, for example, when the communication system is started up, and its count outputs (selection signals) Q _{0 to} Q ₂ = 0. In this state, the selector 12 selectively outputs the clock signal CA ₀ , and the selector 14 selectively outputs the alarm signal EA ₀ . Then, when a failure occurs in the system of the clock signal CA ₀ at a certain point, the output ER of the selector 14 becomes ER = 1 due to the alarm signal EA ₀ = 1 and thus the counter circuit 16 increments by the clock signal CLK synchronized with the system. As a result, the count outputs Q _{0 to} Q _{2 of} the counter circuit 16 become 1, whereby the selector 12 selectively outputs the normal clock signal CA ₁ and the selector 14 the alarm signal EA ₁ . Since the alarm signal EA ₁ = 0, the counter circuit 16 does not increment any more, and this state is maintained until the alarm signal EA ₁ = 1 thereafter. Therefore, in such a case, the clock signal CK supplied to the communication system is not abnormal or instantaneously interrupted, and the communication system can continue to operate.

As described above, the conventional signal selection circuit has a configuration in which when a failure occurs in the active system, the counter circuit 16 is rotated until a normal system is found, and when a normal system is found, the count output at that time is held. It was

[0006]

However, although the above case is good, for example, the clock signal generation block 10 ₁
There may be a failure in the whole. Alternatively, while the system of the clock signal CA ₀ is normal, the clock signals CA _{1 to} CA
The system of ₃ may be abnormal. In the former case, the clock signals CA _{0 to} CA ₃ go down substantially at the same time. Therefore, the counter circuit 16 sequentially takes time until the count outputs Q _{0 to} Q ₂ = 4 in the same manner as described above. I have to count up. The same applies to the latter case. As a result, conventionally, the clock signal CK supplied to the system in this section is in an abnormal state or a momentary interruption, and the communication system cannot operate continuously.

An object of the present invention is to provide a signal selection circuit capable of instantly switching the main signal to a normal spare system even if a failure occurs in a part of the main and auxiliary main signal systems. .

[0008]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the signal selection circuit of the present invention is a signal selection circuit that selects and outputs one of the main signals of the plurality of signal systems, which is normal, based on each alarm signal of the plurality of signal systems. Signal selecting means 2 for selectively outputting any one of the main signals of the plurality of signal systems according to the selection signal to be selected, and next selecting from the main signals of the plurality of signal systems based on the alarm signals of the plurality of signal systems. And a next selection signal forming means 3 for forming a next selection signal for selecting a normal one to be selected. When the alarm signal of the signal system selected by the signal selection means 2 is generated, the next selection signal forming means 3 is generated. The next selection signal is set in the storage means 1.

[0009]

In FIG. 1, the signal selecting means 2 selectively outputs one of the normal main signals of the plurality of signal systems in accordance with the selection signal held by the storage means 1. In this state, the next selection signal forming means 3 forms a next selection signal for selecting a normal one to be selected next from among the main signals of the plurality of signal systems based on the alarm signals of the plurality of signal systems. is doing.
Then, when an alarm signal is detected in the signal system (current system) selected by the signal selecting means 2 at a certain point of time, the alarm signal is output from the selector 4, thereby forming the next selection signal forming means 3. Then, the next selection signal is set in the storage means 1.

Therefore, according to the present invention, even if a failure occurs in a part of the main and auxiliary main signal systems, it is possible to instantly switch the main signals to the remaining normal spare systems. Preferably, the next selection signal forming means 3 forcibly alarms the alarm signal of the signal system selected by the signal selection means 2 among the input alarm signals EA _{0 to} EB ₃ , as shown in FIG. And a signal processing circuit 3 ₁ that outputs the other alarm signals in the same state as the input and a counter circuit 3
_And a selector circuit 3 ₃ for selectively outputting any one of the alarm signals output from the signal processing circuit 3 ₁ according to the next selection signal Q _{0 to} Q ₂ held by the selector circuit 3 _3.
The counter circuit 3 ₂
Is configured to energize the counting operation of.

Therefore, for example, the clock signal CA₀System of
Clock signal CA while normal₁~ CA₃System is abnormal
Counter circuit 3₂Next choice
Issue Q ₀~ Q₂Is already set to 4, so after that, black
Signal CA₀When an abnormality occurs in the
Signal CB₀It is possible to switch to the system. Also preferably
The next selection signal forming means 3 is, for example, as shown in FIG.
Part of each alarm signal of multiple signal system EA₀~ EA₃Of
Laying output Q₂Next selection signal Q₀~ Q₂To be part of
Is configured.

Therefore, in this case, the alarm signal EA₀~
EA₃Clock signal CB only when all are abnormal₀~ CB
₃Will be selected, and thus the clock signal
CA ₀~ CA₃Control to preferentially use the system
It becomes possible to do. Also preferably, the next selection signal type
For example, as shown in FIG.
Ram signal EA₀~ EB₃Next selection signal P based on₀~
P₂Is directly formed by the signal conversion circuit.

Therefore, for example, the current clock signal CA ₀
Even if the standby clock signals CA _{1 to} CA ₃ are down at approximately the same time, the signal conversion circuit instantaneously determines and outputs the next selection signals P _{0 to} P ₂ = 4 in response to this, so that the current clock is used. The system of the signal CA ₀ can be instantaneously switched to the system of the spare normal clock signal CB ₀ . Also preferably,
The signal conversion circuit is configured to form the next selection signal according to a predetermined priority, as shown in FIG. 5, for example.

[0014]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. Figure 2 is a block diagram of a signal selection circuit of the first embodiment, 1 in the figure the latch circuits (LATCH), 2, 4 is a selector (SEL), the following selection signal forming means 3, 3 ₁ signal processing circuit, DEC is a decoder, MSK is a mask circuit, E is an EXOR circuit, O is O
R gate circuit, 3 ₂ counter circuit (CTR), 3 ₃ a selector (SEL), 5 denotes an AND gate circuit (A).

Clock signals CA _{0 to} CA ₃ and CB _{0 to} C
The relationship between B ₃ and the alarm signals EA _{0 to} EA ₃ and EB _{0 to} EB ₃ is the same as that described with reference to FIG. Counter circuit 3 ₂ and the latch circuit 1, for example, is reset at the time of start-up of the system, the count output (following selection signal) Q ₀ to Q ₂ and the latch output (select signal) L ₀ ~L ₂
Are both 0. As a result, the selector 2 selectively outputs the normal clock signal CA ₀ , and the selector 4 selectively outputs the alarm signal EA ₀ of the same system. Further, in this state, the next selection signal forming means 3 outputs the alarm signals E
Each Based on A ₀ ~EB ₃ clock signal CA ₀ to CB ₃
Next selection signals Q _{0 to} Q ₂ for selecting the normal one to be selected next are formed.

[0016] That is, in the first signal processing circuit 3 _1, the selection signal L ₀ ~L ₂ = ₀ of the decoder DEC is inputted,
The output DC ₀ = 1 and the other outputs DC _{1 to} DC
₇ = 0 is output. Among them, the output DC ₀ = 1 forcibly sets the output M ₀ of the OR gate circuit O of the mask circuit MSK to 1 (that is, the alarm signal EA ₀ = 1 state). As a result, the output SER of the selector 3 ₃ becomes 1, and the counter circuit 3 ₂ is incremented accordingly.

[0017] Thus When the next selection signal Q ₀ ~Q ₂ = 1, the selector 3 ₃ is to select the output M ₁ of the mask circuit MSK. Now, looking at the state of the input signal forming this output M ₁ , since DC ₁ = 0, the output M ₁ of the OR gate circuit O is not forcibly set to 1 and instead EX
It depends on the output of the OR circuit E. Since DC ₁ = 0 at the input of the EXOR circuit E, its output is 1 if the input alarm signal EA ₁ = 1,
If the alarm signal EA ₁ = 0, 0 is output. Therefore, the OR gate circuit O in this case outputs the alarm signal M ₁ in the same state as the input. Mask circuit MS
The same applies to each OR gate circuit O associated with the outputs M _{2 to} M ₇ of K. Therefore, if it is assumed that the alarm signals EA _{1 to} EB ₁ = 1 (that is, the alarm state) during a certain period of time, the counter circuit 3 ₂ is sequentially incremented in the same manner as described above, and the next selection signal is output. Q ₀ ~
When Q ₂ = 6, the increment of the counter circuit 3 ₂ is stopped.

When the alarm signal EA ₀ is generated at a certain point after that, the output ER of the selector 4 becomes 1 and the AND gate circuit 5 is energized at the timing of the next clock signal CLK, whereby the counter circuit 3 ₂ Next selection signals Q _{0 to} Q ₂ = 6 are set in the latch circuit 1. As a result, the selector 2 outputs the normal clock signal CB ₂
Is instantly selected and output, and the selector 4 selectively outputs the alarm signal EB ₂ of the same system.

FIG. 3 is a block diagram of a signal selection circuit according to the second embodiment. In the figure, 3 ₄ is an AND gate circuit (A). In the second embodiment, for example, the alarm signal E
The logical product output of A _{0 to} EA ₃ is configured to be a part Q ₂ of the next selection signals Q _{0 to} Q ₂ . In this way, the next selection signal Q ₂ will not be 1 unless all the alarm signals EA _{0 to} EA ₃ are 1, so the next selection signal forming means 3
Will operate so as to preferentially select the next normal system within the range of the clock signals CA _{0 to} CA ₃ . On the other hand, when all the alarm signals EA _{0 to} EA ₃ are 1, Q ₂ = 1 and as a result, the next selection signal forming means 3 is normal within the system range of the clock signals CB _{0 to} CB _3. It works as if you select the next system. And
Even if any one of the clock signals CB _{0 to} CB ₃ is selected, any one of the clock signals CA _{0 to} CA ₃ is selected.
When the above system is restored, the next selection signal forming means 3 operates so as to next select a normal system within the range of the clock signals CA _{0 to} CA ₃ . Thus, according to the second embodiment, the groups of clock signals CA ₀ to CA ₃ are preferentially used.

The alarm signal EA is taken as the logical product.
_{It is} not limited to _{0 to} EA ₃ , and the logical product output is not limited to a part Q ₂ of the next selection signals Q _{0 to} Q ₂ . The logical product of any alarm signal may be taken and the logical product output may be associated with any bit of the next selection signal. FIG. 4 is a block diagram of a signal selection circuit according to the third embodiment. In FIG. 4, reference numeral 3 is an encoder (ENC) which is an example of a next selection signal forming means (signal conversion circuit). In addition, such an encoder 3
Can be composed of a RAM, a ROM, or a combinational logic circuit of gate circuits.

The latch circuit 1 is used to start the system, for example.
Reset, and its latch output (selection signal) L₀
~ L₂Is 0. As a result, selector 2 is normal
Clock signal CA₀Is output selectively, selector 4
Is the same system alarm signal EA ₀Is selected and output. This
In this state, the encoder 3 sends each alarm signal EA₀~~ E
B₃Based on each clock signal CA₀~ CB₃Next out of
Next selection signal P for selecting a normal one to be selected
₀~ P₂Is formed. And at some point an alarm
Signal EA₀Occurs, the encoder 3 will
Signal EA₀The next positive selection that should be
Next selection signal P for selecting the usual one ₀~ P₂(= Example
For example, 1) is instantly formed. At the same time, the selector 4
The output ER = 1 and the timing of the next clock signal CLK
AND gate circuit 5 is energized to
Next selection signal P of encoder 3₀~ P₂= 1 is the latch circuit 1
Is set to. As a result, selector 2 is
Signal CA₁Of the same system.
Alarm signal EA₁Will be selected and output.

Preferably, the encoder 3 has a predetermined size.
Next selection signal P according to the priority of₀~ P₂Forming
Is configured to. FIG. 5 shows the priorities of the embodiment.
It is a truth table of the tee encoder. In this example, Enco
The input of the feeder 3 is at least A₀= 0 (that is, EA₀=
0) the other remaining inputs A₁~ A₇1 / of
Next selection signal P regardless of 0₀~ P₂= 0. See you
The input of the encoder 3 is at least A₀= 1 and A₁= 0
, The other remaining inputs A₂~ A₇To 1/0 of
Regardless of the next selection signal P ₀~ P₂= 1. And so on
Is. That is, in this example, the clock signal CA₀The system is
No., which has the highest priority,₁~ C
B₃The order of priority is lower. In addition, this
Priority is just an example.
How to use RAM or ROM as the card reader 3
You can easily incorporate even priority information. Of course,
Arbitrary next-choice logic without the concept of priority
It is clear that the encoder 3 with
is there.

Although the above embodiment has described the case where a plurality of clock signals are selected, the present invention can be applied to selection of any kind of signal system. Further, although an example of application to a communication system has been described in the above embodiment, the present invention can be applied to other computer systems, electronic devices and the like.

[0024]

As described above, according to the present invention, it is possible to select, based on each alarm signal of a plurality of signal systems, a normal one to be selected next from among the main signals of the plurality of signal systems. Since the next selection signal forming means for forming the selection signal is provided,
Even if a failure occurs in a part of the main and standby main signals, the main signals can be instantaneously switched to the normal standby system. Furthermore,
In that case, it is possible to give priority to the normal system to be selected next.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a signal selection circuit of the first embodiment.

FIG. 3 is a block diagram of a signal selection circuit according to a second embodiment.

FIG. 4 is a block diagram of a signal selection circuit according to a third embodiment.

FIG. 5 is a truth table of the priority encoder of the embodiment.

FIG. 6 is a block diagram of a conventional signal selection circuit.

[Explanation of symbols]

 1 Storage Means 2 Signal Selection Means 3rd Selection Signal Forming Means 4 Selectors

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 28, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

FIG. 5 is a truth value table of the priority encoder of the embodiment.

Claims (5)

[Claims] 1. A signal selection circuit for selectively outputting any one of the main signals of the plurality of signal systems, which is normal, based on each alarm signal of the plurality of signal systems, the selection signal held by a storage means (1). Signal selecting means (2) for selectively outputting any one of the main signals of the plurality of signal systems according to the above, and next selecting among the main signals of the plurality of signal systems based on the alarm signals of the plurality of signal systems. A next selection signal forming means (3) for forming a next selection signal for selecting one that should be normal, and the next selection signal is generated by generation of an alarm signal of the signal system selected by the signal selection means (2). A signal selection circuit, characterized in that the next selection signal of the forming means (3) is set in the storage means (1). 2. The next selection signal forming means (3) is selected by the signal selection means (2) among the input alarm signals.
The alarm signal of the current signal system is forcibly alarmed
And the other alarm signals are in the same state as input
Signal processing circuit (3₁) And a counter circuit (3₂Signal according to the next selection signal held by
No. processing circuit (3₁) Which of the alarm signals is output
Selector circuit (3₃) And a selector circuit (3₃) Has output an alarm signal
Counter circuit (3 ₂) I will activate the counting operation
The signal selection circuit according to claim 1, characterized in that
Road. 3. The next selection signal forming means (3) is configured such that a logical product output of a part of the alarm signals of the multiple signal system is used as a part of the next selection signal. Signal selection circuit. 4. The next selection signal forming means (3) comprises a signal conversion circuit for directly forming the next selection signal based on each alarm signal of the plurality of signal systems.
Signal selection circuit. 5. The signal selection circuit according to claim 4, wherein the signal conversion circuit is configured to form a next selection signal according to a predetermined priority.