JPH03255728A - Current/stand-by system selecting signal output circuit in dual system - Google Patents

Abstract

PURPOSE:To output a select signal for current and stand-by systems without fail by providing a decoder to receive the binary alarm signals of the active and auxiliary systems and to output plural bits with a required pattern, and a logical gate circuit to output the select signal for the current or stand-by system from the output of the decoder. CONSTITUTION:Based on current system alarm signals MLDM ALM1 (W) and IN DWN ALM1 (W) and stand-by system alarm signals MLDM ALM2 (P) and IN DWN ALM2 (P), a decoder 1 receives output signals A and B of logical gate circuits 4 and 5 and outputs four bit outputs X0, X1, X2 and X3 with the required pattern corresponding to this signal pattern. When an output from a NAND gate 21 of a logical gate circuit 2 is made H, the active system is selected by a selector 8 and when the output of an inverter circuit 22 is made H, the auxiliary system is selected.

Description

[Detailed Description of the Invention] [Table of Contents Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Effects (Fig. 1) Examples (Fig. 1) (Figures 2 to 6) Effects of the invention [Summary] In a duplex system comprising a working system and a backup system, what kind of input cover pattern can be used for a circuit that outputs a signal for selecting the working system or the backup system? The purpose of this system is to make it possible to issue a signal that reliably selects the active system or standby system according to predetermined rules corresponding to the input cover turn. and a binary alarm signal issued from the standby system, and output a multi-bit output of a desired pattern according to these signal patterns, and a working system selection signal or a standby system selection signal is output from the multi-bit output of the decoder. The device is configured to include a logic gate circuit that performs the following steps.

[Industrial Field of Application] The present invention relates to a circuit that outputs a signal for selecting the active system or the backup system in a duplex system comprising a working system and a backup system.

[Prior Art] Conventionally, a working system and a standby system are provided, and either the working system or the standby system is activated depending on the signal pattern of a plurality of binary alarm signals issued from the working system and the standby system, respectively. There are redundant systems that are configured to allow you to choose.

In such a duplex system, a circuit is provided that outputs a signal for selecting the active system or the backup system in accordance with the signal pattern of a plurality of binary alarm signals issued from the active system and the backup system, respectively. When assembling a working system/protection system selection signal output circuit, it is conceivable to use a latch circuit using an RS flip-flop, taking into consideration the number of BCs (number of gates), etc.

[Problems to be Solved by the Invention] However, in a conventional latch circuit such as this, patterns that should not be input (for example, input H,
If the latch output goes from H to L at the same time, there is a possibility that the latch output will become unstable.

The present invention has been made in view of these problems, and provides a signal that reliably selects the active system or the standby system in accordance with a predetermined rule corresponding to the input cover turn, regardless of the input cover turn. It is an object of the present invention to provide a working system/protection system selection signal output circuit in a duplex system that is capable of outputting the following signals.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention according to claims 1 and 2.

In this FIG. 1, 1 is a decoder, and this decoder 1
The system receives a binary alarm signal from the active system and a binary alarm signal from the backup system, and outputs a required pattern of multiple bits according to these signal patterns.

2 is a logic gate circuit, and this logic gate circuit 2 outputs a working system selection signal or a standby system selection signal from a plurality of bits output from the decoder 1.

Reference numeral 3 designates a latch circuit, which receives a binary alarm signal from the standby system that is input to the decoder and a part of the bit output from decoder 1, and sends the output to the current input signal that is input to decoder 1. It is supplied as a mask control signal for the binary alarm signal from the system.

4 is a logic gate circuit for mask control; this logic gate circuit 4 receives a mask control signal from the latch circuit 3;
This controls whether or not to mask the binary alarm signal input to the decoder 1 from the active system.

[Function] In the working/standby system selection signal output circuit in the duplex system of the present invention described above, the decoder 1 outputs the binary alarm signal output from the working system and the binary alarm signal output from the standby system. 1, this decoder 1
Now, a plurality of bits of a desired pattern are outputted to the logic gate circuit 2 in accordance with the input signal pattern described above. Thereafter, the logic gate circuit 2 outputs the active system selection signal or the backup system selection signal from the multiple bit output of the decoder 1.

At this time, due to the action of the latch circuit 4 and the gate circuit 5, after the binary alarm signal is output from the working system and the backup system selection signal is cleared, the binary alarm signal from the working system is no longer cleared. After that, no active system selection signal is issued unless a binary alarm signal is issued from the standby system.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

Now, in this embodiment, in a data transmission system, alarm information is put in an overhead bit as a service bit, this overhead bit is extracted from the data, the alarm occurrence location is known, and based on the result, a predetermined According to the established rules, either the active system or the standby system is selected. That is, this data transmission system includes an overhead bit processing unit (○HA) 100.
Between 100 and 100, active multiplexing/demultiplexing equipment (MUX/DMU)
X; MLDM) 101.102 and standby multiplexing/demultiplexing device (MUX/DMUX; MLDM) 103,1
04, and furthermore, in these active and standby systems, in the event of a failure between the multiplexing/demultiplexing devices 101, 102; 103, 104, a binary alarm signal MLDM ALM 1 (W); MLD
M ALM 2 (P) is issued, and 2 (P) is issued in the event of a failure between the overhead bit processing unit and the multiplexing/demultiplexing device.
Value alarm signal IN DllN ALM 1(W);I
NDWN ALM 2 (P) is now issued. And the above binary alarm signal DM ALM
1(W), IN DSN ALM 1(S); ML
DM ALM 2(P); IN DWN ALM 2(
P) is taken out from the overhead bit processing unit 100 and input to a working system/protection system selection signal output circuit as shown in FIG. 2 (block diagram showing an embodiment of the present invention). .

By the way, this working system/protection system selection signal output circuit is connected to the decoder 1.1 as shown in FIG. Logic gate circuit 2. Latch circuit 3. Mask control logic gate circuit 4. It is configured with a logic gate circuit 5 and the like.

First, the mask control logic gate circuit 4 is connected to the latch circuit 3.
A binary alarm signal MLDM ALM from the working system is input to the decoder 1 in response to the mask control signal Q from the ALM
1 (W), IN DWN ALM 1 (II), and for this purpose, two OR gates 41 and 42 are provided.

Here, the OR gate 41 outputs the active system alarm signal MLD.
M ALM 1 (W) and latch output (mask control signal)
In response to Q, the active system alarm signal MLDM ALM
] (11) to control whether to mask or not.
The OR gate 42 outputs the output of the OR gate 41 and the active system alarm signal IN DItlN ALM 1 (W).
), and its output A is input to the decoder 1.

In addition, the logic gate circuit 5 receives a binary alarm signal MLDM ALM 2 (P); IN DWN issued from the standby system.
It receives ALM 2(P) and outputs it as output B to decoder 1. Therefore, one OR gate 5
1.

Here, the OR gate 51 outputs the standby system alarm signal MLD.
M ALM 2 (P), IN D ALM 2 (P)
It receives output B and outputs output B.

In addition, the decoder 1 outputs the active system alarm signal MLDMAL.
M 1 (su), IN DWN ALM], (su) and standby system alarm signal DM AL! 42(P), IN
Two signals A are output from logic gate circuits 4 and 5 based on DWN ALM 2(P).

B, the 4-bit output XO, XI, X2 . It emits X3.

By the way, in this duplex system, the active system alarm signals MLDM ALM 1 (Ij), IN DIilN
When ALM 1 (W) is input, it switches to the standby system, and the standby system alarm signal MLDM ALM 2 (P),
When IN DWN ALM 2 (P) is input, the system switches to the active system, but if the active system is restored after being switched from the active system to the backup system, the system does not switch back to the active system, and then If a failure occurs in the backup system, the system is switched back to the active system. For this purpose, a latch circuit 3, which will be described later, is used.

In addition, the above alarm signal MLDM ALM 1 (S,
INDWN ALM 1 (W), MLDM
ALM 2(P), IN DLILNA
LM 2(P) [However, alarm signal MLDM ALM
For 1 (1+l), the input pattern of the output of the OR gate 41 and the data to be selected (SEL DATA)
For example, the relationship is shown in Fig. 3. In addition,
In this FIG. 3, a, b, c, d are OR gates 41
output.

Signal IN DWN ALM 1 (II), MLDM
ALM 2(P), IN DWN ALM 2(P)
, L indicates a state where no alarm has occurred (No ALM), H indicates a state where an alarm has occurred, and MLDM I DATA indicates that the active system data should be selected.
indicates that backup system data should be selected, and MLDMI DATA* indicates that all multiplexer/demultiplexer units or input disconnections have occurred, so active system data is selected. It represents what should be done.

Therefore, the decoder 1 has inputs A and H.

It outputs a 4-bit output or 0 to X3 that satisfies the relationship shown in FIG. 3 above.

::1', 7lam signal anal DM ALM 1(W),
IN DWNALM 1 (W); MLDM ALM
2(P); IN DIilN ALM 2(P), outputs of logic gate circuits 4 and 5 (input to decoder 1) A, B
, the outputs of decoder 1 X0-X3. An example of a time chart for the mask control output Q of the latch circuit 3 is shown below.
The result will be as shown in Figures (a) to (k).

The logic gate circuit 2 receives the multi-bit output X0 of the decoder 1.
-X3 outputs the active system selection signal MLDM 511 or the protection system selection signal MLDM SW 2, and is provided with a NAND gate 212 and an inversion circuit 22 for this purpose.

The NAND gate 21 outputs the output X01Xi of the decoder 1,
In response to X3, the active system selection signal MLDM 5lil l
The inverting circuit 22 receives the output x2 of the decoder 1 and outputs the backup system selection signal DMSW.
2 is selectively output.

The latch circuit 3 receives the binary alarm signal B from the standby system that is input to the decoder 1 and a part of the bit output X2 from the decoder 1, and sends the output to the binary alarm signal Value alarm signal MLDM ALM 1 (
W), IN DIIN ALM 1 (W) (7) 7 This is supplied as a control signal and also outputs a status signal indicating which system is selected. It has a group configuration. The decoder output X2 is input to the latch circuit 3 via an inversion circuit 6, and a reset signal RESET is input via an inversion circuit 7.

Further, 8 is a selector, and this selector 8 receives the selection signal from this working system/standby system selection signal output circuit and selects the working system data when the working system selection signal DM SW 1 is output. and backup system selection signal MLDM 5lit
If 2 is issued, spare data is selected, and for this purpose two AND gates 81 and 82 and one OR gate 83 are provided.

It should be noted that a flip-flop (not shown) for data latch is provided on the output side of the selector 8 so that an error does not occur even if the phenomenon labeled "whisker" in FIG. 4 occurs.

With the above configuration, FIGS. 4(a) to (d).

Active system alarm signal MLDM AL as shown in (k)
Ml(ld), IN DVN ALM 1(W),
Standby system 7 Alarm signal MLDM ALM 2 (P),
When IN DIilN ALM 2 (P) and the latch output Q are input to the logic gate circuits 4 and 5, the logic gate circuits 4 and 5 output outputs A and B as shown in FIGS. 4(e) and (f). and these outputs A.

B is input to decoder 1. The decoder 1 outputs multiple bit outputs X0-X3 of required patterns as shown in FIGS. 4(g) to 4(j) to the logic gate circuit 2 in accordance with the input signal pattern. Thereafter, this logic gate circuit 2 outputs the active system selection signal MLDMSll 1 or the backup system selection signal M from the multiple bit outputs X0-X3 of the decoder 1.
LDM SW 2 is output. That is, when the output of the NAND gate 21 of the logic gate circuit 2 becomes H, the active system is selected in the selector 8, and the logic gate circuit 2
When the output of the inverting circuit 22 becomes H, the selector 8 selects the backup system.

Also, due to the action of the latch circuit 4 and gate circuit 5,
Binary alarm signal from the current system DM ALM 1 (W)
, IN DWN ALM 1 (W) is issued and the backup system selection signal is issued, then the binary alarm signal signal MLDM ALM 1 (W), IN DWN A from the working system is issued.
Even if LM 1 (II) is no longer output, the backup system will then issue a binary alarm signal MLDM ALM 2 (P),
The active system selection signal is not issued unless IN DSN ALM 2 (P) is issued.

As shown in item 2, no matter what type of input cover turn there is, it is possible to issue a signal that reliably selects either the active system or the backup system, according to a predetermined rule corresponding to the input cover turn.

In the above embodiment, even if no alarm signal is issued from the active system or the backup system, the input data,
When the clock and timing signals are off, it is also possible to switch to another system.

An example of the active system/protection system selection signal output circuit in such a case is shown in FIG. That is, this working system/protection system selection signal output circuit is also connected to the decoder 1.1 as shown in FIG. Logic gate circuit 2. Latch circuit 3. A mask control logic gate circuit 4', a logic gate circuit 5', a selector 8, etc. are provided. Here, decoder 1. logic gate circuit 2
．． Latch circuit 3. Since the selector 8 is the same as that in the previous embodiment, its explanation will be omitted.

Now, the mask control logic gate circuit 4' receives the mask control signal Q from the latch circuit 3 and outputs a binary alarm signal MLDM ALM from the active system that is input to the decoder 1.
1 (Jl), input data disconnection signal DATA IN DALMI, clock disconnection signal CLK IN DIN AL
M1(S).

CLK DWN ALM 1 (R), Timing disconnection signal DWN ALM 1 (S), T
This controls whether or not to mask IIIING IN DEN ALM 1 (R).
R gates 41', 42' and one NAND gate 43'
It has the following.

Here, the OR gate 41' is connected to the active system alarm signal MLD.
The OR gate 42' receives the output of the OR gate 41' and the output of the NAND gate 43' and outputs an output A. The NAND gate 43' Signal DATAIN DSN A
LM1. Clock cutoff signal CLK IN DSN AL
Ml (S), CLK IN D S N ALM 1 (R
), timing disconnection signal TIMING IN DWN A
LM 1(S), TIMING IN DWN ALM
1(R).

The logic gate circuit 5' also receives a binary alarm signal tag DM ALM 2 (P) issued from the backup system, and an input data disconnection signal DATA TN DIjN ALM 2. Clock cutoff signal CLKIN DSN ALM 2(S), CL
K IN DWN ALM 2 (R), timing disconnection signal TIMING IN DWN ALM 2 (S), TIM
It receives ING INDWN ALM 2 (R) and outputs it as two outputs B to the decoder 1. For this purpose, one OR gate 51' and one NAND gate 52' are provided.

Here, the OR gate 51' is connected to the standby system alarm signal MLD.
It receives M ALM 2 (P) and the output of the NAND gate 52' and outputs an output B. The NAND gate 52' receives the input data disconnection signal DATA IN DWN ALM2.
゜Clock cutoff signal CLK IN DWN ALM 2 (
S), CLK IN DSN ALM 2(R), Timing disconnection signal TIMING IN DIIIIN AL
M2(S), TIMING IN DWN ALM
There are some notes on receiving 2(R).

Furthermore, the decoder 1 uses the third
A 4-bit output X0- that satisfies the relationship shown in the figure
X3 is output, and at b, C, and d in FIG. 3 above are the outputs of the OR gate 41', respectively.

NAND gate 42' output, anal DM ALM 2 (P)
, corresponds to the NAND gate 52' output.

In this way, if an alarm signal is issued from the active system and the standby system, the required switching will be performed, and even if no alarm signal is issued from the active system or the standby system, the input data will be switched. , clock, and timing signals are off, switching to another system is performed. In this case as well, no matter what the input cover turn is, a signal can be issued to reliably select the active system or the backup system according to predetermined rules corresponding to the input cover or line. It is something.

Also, due to the action of the latch circuit 4 and gate circuit 5', even if the binary alarm signal signal is no longer output from the active system after the binary alarm signal is output from the active system and the protection system selection signal is output. After that, the active system selection signal is not issued unless a binary alarm signal is issued from the standby system.

Note that the present invention can be similarly applied to duplex systems other than the duplex system as in the above embodiment.

[Effects of the Invention] As described in detail above, according to the active system/standby system selection signal output circuit in the duplex system of the present invention as set forth in claims 1 and 2, no matter what the input cover pattern is, There is an advantage in that a signal for reliably selecting the active system or the backup system can be issued according to a predetermined rule corresponding to the current system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. Fig. 3 is a diagram for explaining the combination of alarm input cover pattern and selection data, Fig. 4 is a time chart for explaining the operation of an embodiment of the present invention, and Fig. 5 is a duplex system to which the present invention is applied. FIG. 6 is a block diagram showing another embodiment of the present invention. 83 is an OR gate.

Claims (2)

[Claims] (1) A working system and a standby system are provided, and either the working system or the standby system can be selected depending on the signal pattern of a plurality of binary alarm signals issued from the working system and the standby system, respectively. In a duplex system configured as follows, the system receives a binary alarm signal issued from the working system and a binary alarm signal issued from the standby system, and outputs a plurality of bits in a desired pattern according to these signal patterns. A decoder (1) and a logic gate circuit (2) that outputs a working system selection signal or a protection system selection signal from the multiple bit output of the decoder (1).
1. A working system/standby system selection signal output circuit in a duplex system, characterized in that it is configured with the following. (2) Even after the binary alarm signal is output from the active system and the backup system selection signal is output, even if the binary alarm signal is no longer output from the active system, the binary alarm signal is subsequently output from the backup system. In order to prevent the active system selection signal from being issued unless an alarm signal is issued, the binary alarm signal from the backup system input to the decoder (1) and the decoder (1)
) and supplies the output as a mask control signal for the binary alarm signal from the active system input to the decoder (1);
2. The active system/protection system selection signal output circuit in a duplex system according to claim 1, further comprising: