JPH0793573B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a PLL circuit, and particularly to reducing the pull-in time in a PLL circuit having a high multiplication rate.

[Conventional technology]

A PLL circuit (Phase locked loop) with a high multiplication rate is used, for example, in a digital video tape recorder (digital VT).
R). That is, the digital VTR employs a method of recording the audio signal by PCM encoding, but from the viewpoint of international standardization, the sampling frequency of the PCM audio signal is locked to the field frequency of the video signal. It is said that it is necessary to select By the way, in the EBU and SMPTE standards, the sampling frequency of the PCM audio signal is 48
It is being recommended to select [kHz].

When recording a PCM audio signal of such a system on a VTR, a processing clock signal for processing four channels of the PCM audio signal is actually required to have a frequency several hundred times higher.

From the above point of view, it is inevitable that the sampling frequency of the PCM audio signal actually becomes a frequency with a high multiplication factor of about 200,000 as compared with the field frequency of the video signal.

For example, when recording a PAL video signal, since the video field frequency f _f is 50 [Hz] and the number of scanning lines is 625, sampling of the PCM audio signal is used as the clock for processing the audio signal. 2 of frequency f _A
Since the frequency f _{C of} 56 times is required, when f _A = 48 [kHz], the frequency of the clock signal for processing the audio signal is f _C , f _C = 245760 × f _f ...... ( It is necessary to select a frequency that satisfies the relationship of 1).

This is because in a digital VTR of this kind, in order to obtain a processed clock signal of the audio signal locked to the video field frequency f _f = 50 [Hz], the frequency is 50 [H
It means that it is necessary to provide a PLL circuit with a high multiplication rate that receives the reference signal [z] and generates an oscillation output having a frequency of the multiplication rate of 245760 times.

By the way, when configuring a PLL with such a high multiplication rate, it is necessary to use an oscillator with a high oscillation frequency as the voltage controlled oscillator (VCO), and it is difficult to apply an LC oscillator from the viewpoint of its stability. It is considered that there is a crystal oscillator is often used.

However, the voltage-controlled crystal oscillator has a drawback that the pull-in time is long due to its high selectivity, and a pull-in time that is as long as several minutes has been used.

[Problems to be solved by the invention]

The present invention has been made in consideration of the above points, and in a PLL circuit using a voltage-controlled crystal oscillator having a high multiplication factor of several hundreds of thousands, it is possible to drastically shorten the pull-in time. It is intended to propose a circuit.

[Means for solving problems]

In order to solve the above-mentioned problems, in the present invention, the phase-frequency comparison circuit 2 of the PLL loop 1 compares the phase difference and frequency of the reference signal RF and the variable signal VF and eliminates the difference so as to eliminate the difference. The oscillation frequency of 7 is controlled, and the oscillation output signal OS of the voltage controlled crystal oscillator 7 is divided by the frequency dividing circuit 5 to obtain a variable signal.
VF is obtained, a window pulse signal WP having a predetermined window section T _W in relation to the reference signal RF is generated in the window signal generation circuit 14, and the forced pull-in control circuit is generated.
When the phase of the variable signal VF deviates from the window section T _W of the window pulse signal WP at 17, the load signal LD
Is generated and the frequency divider circuit 5 is loaded by the load signal LD, thereby locking the phase of the variable signal VF to a predetermined phase near the phase of the reference signal RF, and in addition, switching the pull-in direction. A circuit 31 is provided, and in the pull-in direction switching circuit 31, the phase of the variable signal VF is the window section T _W of the window pulse signal WP in the first direction (for example, the phase of the variable signal VF is the reference signal RF.
, The switching pulse for the reference signal RF of the phase frequency comparison circuit 2
By inserting CP2, the pull-in operation direction of the PLL loop 1 is switched to the second direction (that is, the direction in which the phase of the variable signal VF lags the reference signal RF).

[Action]

When the phase of the variable signal VF deviates from the window section T _W of the window pulse signal WP, the frequency dividing circuit 5 of the PLL loop 1 is loaded by the load signal LD to obtain the output terminal of the frequency dividing circuit 5. By locking the phase of the received variable signal VF near the phase of the reference signal RF, the pull-in operation time necessary for pulling the variable signal VF into the reference signal RF in the PLL loop can be significantly shortened.

When the phase of the variable signal VF is locked, the operation mode of the phase frequency comparison circuit is
When the phase of the variable signal VF is separated from the reference signal RF, the operation mode of the phase frequency comparison circuit 2 is switched to change the phase of the variable signal VF from the loaded phase to the reference signal RF. The frequency comparison circuit 2 is operated. By doing this, PL
The pulling operation of the L loop 1 can be reliably performed.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a first embodiment of the PLL circuit according to the present invention, which has a PLL loop 1 for generating an oscillation output multiplied by 245760 times with respect to a reference signal RF. The PLL loop 1 has a phase frequency comparison circuit section 4 composed of a phase frequency comparison circuit 2 and a charge pump 3 connected to its output end, and a reference signal RF given from the outside to the phase frequency comparison circuit 2 is supplied. , The variable signal VF obtained at the output terminal of the frequency dividing circuit 5 is compared.

The error output of the phase frequency comparison circuit section 4 is converted into a direct current in a low pass filter 6 having an integrating circuit structure and is given to the voltage controlled crystal oscillator 7 as a control signal. The oscillation output OS of the voltage controlled crystal oscillator 7 is given to the frequency dividing circuit 5, and the frequency divided output is fed back to the phase frequency comparing circuit 2 as a variable signal VF.

Here, as the reference signal RF, the vertical synchronizing signal SV of the video signal is used through the reference signal forming circuit 11 and the input gate circuit 12, and thus has the same frequency (for example, 50 [Hz]) as the vertical synchronizing signal SV. On the other hand, the voltage-controlled crystal oscillator 7 is the frequency of the reference signal RF.
Oscillation output OS of oscillation frequency f _C (= 50 × 245760 = 12.888 [Hz]) with a high multiplication factor of 245760 times f _f (= 50 [Hz])
To occur.

On the other hand, the frequency dividing circuit 5 divides the oscillation output of the oscillator 7 at a very high frequency dividing rate, that is, 245760 frequency division, and thus approximately 50 [Hz].
The variable signal VF is obtained and given to the phase frequency comparison circuit 2.

The phase frequency comparison circuit unit 4 includes a phase frequency comparison circuit 2 having a circuit configuration as shown in FIG. 2 and a charge pump 3 having a circuit configuration as shown in FIG. 3, and is manufactured by Fairchild IC ( 11C44) is used. This phase frequency comparison circuit 2 uses the reference signal RF and the variable signal VF.
In response to the change in the logic level of, the two UI and DI outputs whose logic levels are changed are sent as shown in the flow table of FIG.

In FIG. 4, the numbers shown in the column of "states of RF and VF" can be taken by the phase frequency comparison circuit 2 according to four states that can occur due to the combination of logic levels of the reference signal RF and the variable signal VF. It indicates the operation mode, and the numbers in parentheses indicate the phase frequency comparison circuit 2.
Means that the phase frequency comparator circuit 2 can be stabilized in that state, while the numbers without () indicate that the phase frequency comparison circuit 2 is in an unstable state. Then, when the phase frequency comparison circuit 2 is in this unstable state, the operating state of the phase frequency comparison circuit 2 transits to the state of the numbers shown in the other columns in the vertical direction, and thus the same number with () is added. It will stabilize to the state. Also, if the combination of the reference level RF and the variable level VF changes,
When the new stable state is unstable, the stable state is changed to the stable state.

The phase frequency comparison circuit 2 configured as shown in FIGS. 2 and 4 changes its state as shown in FIG. 5 (C) when the reference signal RF has twice the frequency of the variable signal VF. And U1 as shown in FIGS. 5 (D) and (E)
Send D1 output.

On the contrary, when the frequency of the variable signal VF is twice as high as the frequency of the reference signal RF, the phase frequency comparison circuit 2 enters the state as shown in FIG. The U1 and D1 outputs shown in FIGS. 6D and 6E are transmitted.

Thus, two outputs that change according to the difference in frequency, that is, U1 and D1 outputs are supplied to the input ends PU and PD of the charge pump 3, and the output ends UF and DF of the charge pump 3 are connected in common to connect the low-pass filter 6 to By connecting to the input end, a control voltage for changing and controlling the oscillation frequency of the voltage-controlled crystal oscillator 7 can be sent to the output end of the low-pass filter 6 in a direction to eliminate the frequency difference.

Further, the phase frequency comparison circuit 2 makes the phase of the reference signal RF 180 with respect to the variable signal VF when the reference signal RF and the variable signal VF have the same frequency.
As the vehicle progresses, the state change shown in FIG. 7 (C) is exhibited, and U1 and U1 shown in FIGS. 7 (D) and (E)
Send D1 output.

On the contrary, when the phase of the reference signal RF is delayed by 180 ° with respect to the variable signal VF, the phase frequency comparison circuit 2 exhibits a state change as shown in FIG. 8 (C).
This results in U1 as shown in FIGS. 8 (D) and (E) and
Send D1 output.

Thus, when the phases of the reference signal RF and the variable signal VF are different, the U1 and D1 outputs corresponding to the phase difference are obtained, which controls the operation of the charge pump 3 so that the output end of the low-pass filter 6 can be affected. A control voltage that cancels the phase difference is generated, and thus the phase of the variable signal VF is controlled so as to match the phase of the reference signal RF.

The reference signal forming circuit 11 has three stages of flip-flop circuits 13A to 13C which are cascaded to each other, and the trigger input terminal of each stage has a composite sync signal SY (FIG. 9 (B)) included in the video signal. ) Is given.

Thus, when the vertical synchronizing signal SV falls from the logic "1" to the logic "0" at the time t ₀ as shown in FIG. 9 (A), the change of this state comes after that.
By SY, the flip-flop circuits 13A, 13B and 13C are sequentially written.

The outputs of the first-stage flip-flop circuit 13A and the Q-output of the third-stage flip-flop circuit 13C are given to the 2-input AND circuit 14 which constitutes the window signal forming circuit, and thus the output end of the AND circuit 14 is shown in FIG. As shown, a window pulse signal WP is obtained which rises at the rising edge of the composite sync signal SY that first arrives after the falling edge of the vertical sync signal SV and falls at the rising edge of the third composite sync signal SY. . Thus the wind pulse signal
WP forms a window section T _W which becomes logical “1” for two horizontal sections from the timing of the composite synchronization signal SY which arrives only after the fall of the vertical synchronization signal SV.

This window pulse signal WP is supplied to the forced pull-in control circuit 17. This forced pull-in control circuit 17 is a window pulse signal.
Start-up state detection circuit 18 of D-type flip-flop circuit configuration that directly receives WP as a trigger signal, and window pulse signal
A falling state detection circuit 20 having a flip-flop circuit configuration that receives WP as a trigger signal via an inverter 19. The rising state detection circuit 18 receives the variable signal VF obtained from the PLL loop at the D input terminal and receives the window pulse signal.
When WP rises from the logic "0" to the logic "1", the rising operation causes the set operation when the variable signal VF is the logic "1" or the reset operation when the variable signal VF is the logic "0". Thus, the rising state detection circuit 18 stores the state of the variable signal VF at the rising time of the window pulse signal WP. Similarly, the variable signal VF is applied to the D input terminal of the falling state detection circuit 20, and when the window pulse signal WP falls from the logic "1" to the logic "0", this fall is inverted in the inverter 19. Is applied as a trigger signal, the falling state detection circuit 20 performs a set operation or a reset operation according to the logic state of the variable signal VF. Thus, the rising state detection circuit 18 stores the state of the variable signal VF at the falling edge of the window pulse signal WP.

Q output of rising state detection circuit 18 and falling state detection circuit 20
Output is given to a 2-input NAND circuit 21, and the NAND output is a load signal forming circuit having a flip-flop circuit configuration.
It is given to the D input terminal of 22.

On the other hand, the output of the second-stage flip-flop circuit 13B of the reference signal forming circuit 11 and the Q output of the last-stage flip-flop circuit 13C are input to the 2-input NAND circuit 25 of the input gate circuit 12, and its output terminal is shown in FIG. As shown in D), the output RFX which falls during the section corresponding to the latter half of the window section T _W of the window pulse signal WP is formed. This output RFX
Is input to the phase frequency comparison circuit 2 as a reference signal RF shown in FIG. 9 (E) through a 2-input NOR circuit 26 having an inverting circuit at its input end.

Thus, the output RFX obtained in the NAND circuit 25 of the input gate circuit 12 is passed through the inverter 27 of the forced pull-in control circuit 17 to the D of the preset circuit 28 of the flip-flop circuit configuration.
It is input to the input terminal. The composite sync signal SY is applied as a trigger signal to the preset circuit 28, and every time the composite sync signal SY arrives, the set operation and the reset operation are performed according to the inverted logic level of the output RFX.

The Q output is sent to the load signal forming circuit 22 as the preset signal PR.
Given as. Thus, the preset signal PR is, as shown in FIG. 9 (F), from time t ₃ when the window pulse signal WP falls to time t ₄ when the next composite sync signal SY arrives.
Until that time, it is obtained as a signal which rises to the logic "1", and the rise thereof forces the load signal forming circuit 22 to be reset to the reset state.

The oscillation output signal OS of the voltage-controlled crystal oscillator 7 is used as a trigger signal for the load signal forming circuit 22, whereby the load signal forming circuit 22 is triggered at a high frequency that the oscillation output signal OS has.

By the way, a NAND circuit input to the load signal forming circuit 22.
The output of 21 is the rising state detection circuit 18 and the falling state detection circuit.
It is controlled to the set or reset state according to the 20 stored states. First, when the vertical synchronizing signal SV occurs in the window section T _W of the falling window pulse signal WP of the variable signal VF, as shown in FIG. 9 (G1), at the rising time t ₁ of the window pulse signal WP. whereas variable signal VF is a logic "1", variable signal VF at the falling time t ₃ of the window pulse signal WP is a logic "0". Therefore, the rising state detection circuit 18 is set and its output becomes logic "1", while the falling state detection circuit 20
Is reset and its Q output becomes a logic "1". Therefore, at the falling time point t ₃ of the window pulse signal WP, the D input given from the NAND circuit 21 to the load signal forming circuit 22 becomes logic “0”, and at that time point, the load signal forming circuit 22 is in the reset state. When the load signal LD is not sent.

After that, when the vertical synchronizing signal SV repeatedly falls at time t ₀ , if the falling edge of the variable signal VF is within the window section T _W of the window pulse signal WP, the rising state detection circuit 18 and the falling state detection circuit 20 Since the memory state is not changed and is in the set and reset states respectively, the load signal forming circuit 22 continues to maintain the reset state, and accordingly maintains the state in which the load signal LD is not transmitted. At this time, the PLL loop 1 maintains the original pull-in operation.

On the other hand, as shown in FIG. 9 (G2), when the variable signal VF maintains the state of logic “0” through the window section T _W of the window pulse signal WP, the rising state detection circuit 18 and The falling state detection circuit 20 uses the window pulse signal WP
Since they are in the reset state at the falling time t _3, the output of the NAND circuit 21 becomes logical "1".

Further, as shown in FIG. 9 (G3), the wind pulse signal WP
When the variable signal VF maintains the state of logic “1” through the window section T _W of the rising state detection circuit 18
And falling state detection circuit 20 since the both excisional state at the falling time t ₃ of the window pulse signal WP, the output of the NAND circuit 21 is at logic "1".

Further, as shown in FIG. 9 (G4), the variable signal VF is logic “0” at the falling time point t ₁ of the window pulse signal WP.
, And the and if the Natsuta to logic "1" at the falling time t ₃ state (this state means that the variable signal VF is restored to logic "1" from a logical "0"), the window pulse signal At the falling time point t ₃ of WP, the rising state detection circuit 18 is reset and the falling state detection circuit 20 is set. At this time, the output of the NAND circuit 21 becomes logic "1".

When the load input of the logic "1" is applied to the load signal forming circuit 22 as described above, the load signal forming circuit 22 immediately performs the set operation by the oscillation output signal OS. In this set state, the preset signal PR is given from the preset circuit 28 at the falling time t ₃ of the window pulse signal WP to preset the load signal forming circuit 22 and its Q output is logically changed as shown in FIG. 9 (H). From "1" to logical "0"
Fall to. When this state is followed by the next pulse of the oscillator output signal OS, the load signal forming circuit 22 is triggered and reset again, thus the Q output rises to a logic "1". Then, the rising of the Q output from the logic "0" to the logic "1" is sent to the frequency dividing circuit 5 of the PLL loop 1 as the load signal LD.

In this way, the load signal forming circuit 22
When the falling edge of VF is not in the window section T _W of the window pulse signal WP, the load signal LD is supplied to the frequency dividing circuit 5 to load the frequency dividing circuit 5.

At this time, the frequency dividing circuit 5 is controlled by the load signal LD so as to generate a variable signal VF that falls from the logic "1" to the logic "0" at the rising time thereof, and thus the variable signal VF is transferred. Forcibly matches the falling phase of the load signal LD.

Since the window section T _W is selected for a time long enough for the PLL loop 1 to perform its original pull-in operation, the variable signal forcibly phased by the load signal LD is selected.
VF phases will be lock from the state it was out from the window interval T _W instantaneously window interval T _W vicinity phase.

In addition to the above configuration, the PLL circuit has a pull-in direction switching circuit 31. The pull-in direction switching circuit 31 determines that the phase of the variable signal VF is ahead of the reference signal RF in the phase frequency comparison circuit unit 4 and the variable signal outside the hall.
When a control voltage having a value that delays the phase of VF is applied to the voltage controlled crystal oscillator 7, the operation mode of the phase frequency comparison circuit unit 4 can be switched to bring the phase lock state to the lock state as quickly as possible. Is what you are trying to do.

That is, the phase frequency comparison circuit 2 of FIG.
As described above with reference to FIGS. 7 and 8, when the variable signal VF lags the reference signal RF,
Starting from the state of operation mode 2 in FIG. 2C, the U1 and D1 outputs that change according to the combination of the logic levels of the variable signal VF and the reference signal RF are sent to the charge pump 3 based on the flow table (FIG. 4). To do.

On the other hand, when the variable signal VF is ahead of the reference signal RF, as shown in FIG. 8C, the combination of the logical levels of the variable signal VF and the reference signal RF is started after the operation mode 6 is started. The U1 and D1 outputs, which change accordingly, are sent to the charge pump 3.

This operation is described above with reference to FIG.
When applied to the phase relationship between the variable signal VF and the variable signal VF, the variable signal VF (Fig. 10 (B)) is changed to the reference signal RF (Fig.
10 (A))), the operation mode of the phase frequency comparison circuit 2 indicates that the logical levels of the reference signal RF and the variable signal VF are sequentially “1” and “from the flow table of FIG. 1 ”,“ 0 ”and“ 1 ”,
As it changes like "0" and "0", "1" and "0", the operation mode changes in the order of 7, 2, 5, 8 (Fig. 10 (C)). , The U1 and D1 outputs (FIGS. 10 (D) and (E)) are logic "1" and "1", "0" and "1", "1" and "1", "1".
And "1".

Similarly, when the variable signal VF (Fig. 11 (B)) is ahead of the reference signal RF (Fig. 11 (A)) in phase, the logical levels of the reference signal RF and the variable signal VF are sequentially "1". And "1", "0" and "0",
If it changes like “0” and “0”, “1” and “0”, the operation mode of the phase frequency comparison circuit 2 is shown in FIG. 11 (C).
As shown in FIG. 4, the logic levels of the outputs U1 and D1 are changed to "1" and "0", "1" and "1" according to the flow table of FIG. "1",
It changes like "1" and "0", "1" and "0".

In FIG. 10 and FIG. 11, the time points t ₂₁ and t ₃₁ when the reference signal RF falls from the logic “1” to the logic “0” are the same as the window pulse signal WP as described above with reference to FIG. 9 (D).
Since it is almost in the middle phase of the window section T _W of, the logic level of the D1 output of the phase frequency comparison circuit 2 based on the rising of the window pulse signal WP before these time points t ₂₁ and t ₃₁ is It can be known whether the phase of the variable signal VF with respect to the signal RF is advanced or delayed. That is, as can be seen from FIG. 10 (E), when the phase of the variable signal VF lags the reference signal RF, the logic level of the D1 output is "1". On the other hand, as can be seen from Fig. 11 (E), the variable signal
D1 when the phase of VF is ahead of the reference signal RF
The output logic level is "0".

The pull-in direction switching circuit 31 is a control pulse generation circuit 32 of a mono-multivibrator configuration that is triggered when the output of the inverter 19 of the forced pull-in control circuit 17 falls to a logic "0" level.
And its Q output is given as a trigger signal to the switching pulse generating circuit 33 having a mono-multivibrator configuration.

The switching pulse generation circuit 33 receives the D1 output of the phase frequency comparison circuit 2 as an enable signal, and when the D1 output is logic "0" (that is, the phase of the variable signal VF as described above with reference to FIG. 11E). Is leading the reference signal RF), and when the control pulse CP1 (FIG. 9 (I)) is given from the control pulse generation circuit 32, it is triggered by its rising edge. Thus, the switching pulse signal CP2 (FIG. 9 (J)) which falls to the logic "0" for a predetermined time from the rising edge of the control pulse CP1 is the switching pulse generating circuit 3
3 is provided at the output end of the input gate circuit 12 and is supplied to the second inverting input end of the NOR circuit 26 of the input gate circuit 12.
The level switching pulse CP2 is inserted into the reference signal RF as shown by the broken line in FIG.

In this way, the phase of the variable signal VF is the reference signal.
Switching pulse CP2 is the reference signal R when advanced from RF.
When it is inserted into F (FIG. 12 (A)), the operation mode of the phase frequency comparison circuit 2 is changed as compared with the case of FIG. That is, as shown in FIG. 12, the wind pulse signal
When the switching pulse CP2 (Fig. 12 (F)) generated at the rising edge of WP is generated, the reference signal RF falls from the logic "1" to the logic "0", so that the phase frequency comparison circuit 2 becomes According to the flow table in Fig. 4, the reference signal RF and the variable signal VF are logical level "0".
And when it becomes "1", the operation mode is switched to 6 accordingly.

After that, after the section of the switching pulse CP2 has passed, the states of the reference signal RF and the variable signal VF return to the states of FIG. 11, but at this time, the operation mode of the phase frequency comparison circuit 2 is during the section of the switching pulse CP2. Operation mode 6 switched to
7, 2, and according to the flow table of FIG.
Switch to 5 or 8 (Fig. 12 (C)) and respond accordingly.
The logic level of U1 and D1 output is "1", "1", "0"
And "1", "1" and "1", "1" and "1" (Fig. 12 (D) and (E)).

The operation mode of the phase frequency comparison circuit 2 after this switching pulse CP2 is inserted into the reference signal RF and its U1 and
The change of the D1 output is the same as the operation when the phase of the variable signal VF described above in FIG. 10 is delayed from the reference signal RF. This means that the phase frequency comparison circuit unit 4
Means that the phase of the variable signal VF is judged to be behind the reference signal RF and that the same operation is being performed, and thus the wind pulse signal
When the trailing edge of the variable signal VF is locked to the leading edge of the load signal LD by the generation of the load signal LD (Fig. 12 (G)) generated when WP falls, the phase frequency The comparison circuit unit 4 uses this variable signal
The pull-in operation is performed so that the falling edge of VF is aligned with the falling edge of the window pulse signal WP.

In the above configuration, when the falling edge of the variable signal VF occurs in the window section T _W of the window pulse signal WP (FIG. 9 (C)), the NAND circuit 21 of the forced pull-in control circuit 17 is generated.
Since the output of the logic "L" is obtained at the output end of the load signal forming circuit 22, the load signal forming circuit 22 does not enter the state in which the load signal LD can be transmitted. Therefore, the PLL loop 1 performs the original phase lock operation based on the output of the phase frequency comparison circuit 2 and performs the pull-in operation such that the falling edge of the variable signal VF coincides with the falling edge of the reference signal RF. On the other hand, if the falling edge of the variable signal VF does not occur during the window section T _W of the window pulse signal WP as described above with reference to FIGS. 9 (G2), (G3), and (G4), forced pull-in is performed. Control circuit 17
Since the output of the NAND circuit 21 of becomes a logic "1",
The load signal forming circuit 22 performs a preset operation by the preset signal PR (Fig. 9 (F)) generated at the trailing edge of the window pulse signal WP to generate the load signal LD (Fig. 9 (H)).

Therefore, the falling edge of the variable signal VF obtained from the frequency dividing circuit 5 of the PLL loop 1 is phase-locked with the rising edge of the load signal LD.

On the other hand, during this period, the switching pulse generating circuit 33 of the pull-in direction switching circuit 31 does not operate the switching pulse generating circuit 33 when the logic level is "1" in response to the D1 output of the phase frequency comparison circuit 2, thereby switching pulses. Do not generate CP2. Therefore, at this time, the PLL loop 1 operates so as to advance the phase of the variable signal VF whose phase is delayed based on the output of the phase frequency comparison circuit 2
Phase VF to the reference signal RF.

On the other hand, when the logic level of the D1 output of the phase frequency comparison circuit 2 is "0", it is determined that the falling phase of the variable signal VF is ahead of the falling phase of the reference signal RF, and the switching pulse generation circuit 33 is triggered by the control pulse signal CP1 generated by the trailing edge of the window pulse signal WP to generate the switching pulse CP2. This pulse CP2 is inserted into the reference signal RF through the NOR circuit 26 (12th
(A)), which allows the phase of the variable frequency VF to be changed from the operation mode when the phase of the variable signal VF is ahead of the reference signal RF (see FIG. 11) to the reference signal RF. Switching to the operation mode (Fig. 10) when the phase is delayed (Fig. 12 (C)).

At this time, since the frequency divider circuit 5 of the PLL loop 1 performs the load operation at the time of the fall of the window pulse signal WP by the load signal LD, the fall of the variable signal VF is almost locked to the fall phase of the window pulse signal WP. However, in addition to this, the phase frequency comparison circuit 2 performs the locking operation so as to recommend the variable signal VF toward the reference signal RF, so that the falling edge of the variable signal VF is changed to the reference signal RF in a very short time. You can lock it down.

Note that, unlike the case of the above-described embodiment, when the operation mode of the phase frequency comparison circuit 2 is not switched, when the phase of the variable signal VF is ahead of the reference signal RF, the falling edge of the variable signal VF falls. Must advance in a phase range close to 360 degrees from the phase locked by the load signal (that is, the phase near the trailing edge of the reference signal). However, according to the configuration of FIG. By reversing the pull-in direction of the frequency comparison circuit 2, the variable signal VF is added to the trailing edge of the reference signal RF closest to the position locked by the load signal LD.
Can be matched in phase.

FIG. 13 shows a second embodiment, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In this case, the reference signal forming circuit 11 has two stages of D-type flip-flop circuits 35A and 35B, and a mono-multivibrator 36 which receives the rising of the Q output of the second-stage flip-flop circuit 35B as a trigger signal. Then, in the same manner as described above with reference to FIG.
When SV falls at the time point t ₀ , the flip-flop circuits 35A, 35B are sequentially reset by the composite sync signal SY that arrives at the time points t ₁ , t ₂ , so that the second
At the time t ₂ of the second composite sync signal SY, the monomultivibrator 36 is triggered, whereby the Q output which becomes logic “1” for a predetermined time limit is inverted through the 2-input NOR circuit 37 constituting the input gate circuit 12. Fig. 14 (A)
As shown in (1), it is sent to the phase frequency comparison circuit 2 of the PLL loop 1 as a reference signal RF falling from logic "1" to "0".

The PLL loop 1 has the same configuration as that shown in FIG.
As shown in FIG. 4 (C), when the variable signal VF whose phase is delayed with respect to the reference signal RF is obtained from the frequency dividing circuit 5, the PLL loop 1 performs a pull-in operation in the direction of eliminating this phase delay.

On the other hand, when the phase of the variable signal VF is ahead of the reference signal RF, the variable signal VF as shown in FIG. 15 (C) is obtained.

The window pulse signal forming circuit 14 is composed of a multivibrator, receives the falling of the Q output of the flip-flop circuit 35A of the reference signal forming circuit 11 as a trigger signal, and when the vertical synchronizing signal SV falls at time t ₀ , It is triggered when the first composite sync signal SY (Fig. 9 (B)) arrives, and the reference signal RF comes to the center phase of the window section T _W as shown in Fig. 14 (B). During this period, the window pulse signal WP rising to logic "1" is transmitted.

The forced pull-in control circuit 17 receives the window pulse signal WP D
Has a pull-in signal generating circuit 41 which is a flip-flop circuit, and receives the U1 output of the phase frequency comparing circuit 2 at its trigger input terminal, and is triggered when the U1 output rises from logic "0" to logic "1". It is designed to be. The output is given to one input terminal of the 2-input NAND circuit 42 as the forced pull-in control signal KH. The NAND circuit 42 is supplied with the Q output of the mono-multivibrator 36 of the reference signal forming circuit 11 as a second input, and the falling edge of the output of the NAND circuit 42 is the load signal generating circuit 43 of the mono-multivibrator configuration.
As a trigger signal.

Thus, when the mono multivibrator 41 is in the reset state and the forced pull-in control signal KH is the logic "1" (Fig. 14 (I)), the mono multivibrator 36 of the reference signal forming circuit 11 outputs the inverted reference signal ▲.
When ▼ is given, the output of the mono-multivibrator 43 is sent as a load signal LD (Fig. 14 (J)).
This load signal LD is fed back as a set signal to the pull-in signal generating circuit 41, whereby the pull-in signal generating circuit is generated.
Clear 41 to standby.

Further, the pull-in direction switching circuit 31 has a direction signal generating circuit 45 having a D-type flip-flop circuit configuration, and the phase frequency comparing circuit 2 also receives the D1 output through the inverter 44 as a trigger signal thereof, thus the direction signal generating circuit 45 outputs the D1 output. When the signal falls from the logic "1" to the logic "0", the set or reset operation is performed according to the logic level of the window pulse signal WP. The output is given to the 2-input NAND circuit 46 together with the Q output of the window pulse signal forming circuit 14, and the fall thereof triggers the direction switching signal generating circuit 47 of the mono-multivibrator configuration. This direction switching signal generation circuit 47 is triggered when the falling edge of the variable signal VF is out of the window pulse signal WP and the phase of the variable signal VF is ahead of the reference signal RF, and the switching pulse CP2 (15th pulse) is generated. (H) is given to the input gate circuit 12.

As a result, a pulse obtained by inverting the switching pulse CP2 is inserted in the reference signal RF obtained at the output terminal of the NOR circuit 37 of the input gate circuit 12.

In the configuration of FIG. 13, if the phase of the variable signal VF is in the window section T _W of the window pulse signal WP with respect to the reference signal RF, the PLL loop 1 performs its original pull-in operation, thus In both cases where the phase of the variable signal VF is behind or ahead of the reference signal RF, the phase of the variable signal VF matches the reference signal RF by the original pull-in operation of the PLL loop 1. Operate.

On the other hand, to the extent that the phase of the variable signal VF deviates outside the window section T _W of the window pulse signal WP,
When the trailing edge of the variable signal VF lags the trailing edge of the reference signal RF, it operates as shown in FIG.
Phase of the variable signal VF (FIG. 14 (C)) is delayed from the window period T _W relative i.e. time t ₄₀ ~t ₄₃ also Rifuarensu signal RF generated in the window period T _W (FIG. 14 (A)) If, Rifuarensu signal RF generated between time t ₄₀ ~t ₄₄
Also, the phase frequency comparison circuit 2 transits to the operation modes 7, 2 and 3 as shown in FIG. 14 (D) according to the change of the logic level of the variable signal VF, and in response to this, the U1 output changes to FIG. As shown in (E), the logic changes like "1", "0", "0", while the D1 output is "1", "1",
It does not change like "1". Since the D1 output does not change, the direction signal generating circuit 45 of the pull-in direction switching circuit 31 is not triggered, and accordingly, the direction switching signal generating circuit 47 does not output the switching pulse CP2.

In contrast fall to "0" from logic "1" U1 output at time t _41, since the stand rise changes to a logic "1" in the subsequent time t _44, the forced pull-in control circuit at the rise time t ₄₄ The 17 pull-in signal generation circuits 41 are triggered. Time at this point t _44, since the window pulse signal WP is one Tatsuka to logic "0" (FIG. 14 (B)), pull signal generating circuit 41 is switched to the reset state, forced pull-in control signal KH stand amounts to a logical "1" at t ₄₄ (Chapter 14
(I)). This state is maintained until the next reference signal RF is generated.

Between the time t ₄₄ to the next Rifuarensu signal RF is generated, PLL loop 1 performs the pull-in operation for the variable signal VF, since the lock state is not obtained retraction, the operation mode of the phase frequency comparator circuit 2 is first As shown in FIG. 14 (D), switching is made as 8 and 7. However, due to this switching, the U1 output (FIG. 14 (E)) and the DI output (FIG. 14 (F)) of the phase frequency comparison circuit 2 do not change.

When the next reference signal RF is generated at time t ₄₆ , the two inputs ▲ ▼ and KH of the NAND circuit 42 of the forced pull-in control circuit 17 both become logic “1”,
Since its output falls to logic "0", the load signal generating circuit 43 is triggered, and thus the load signal LD (Fig. 14 (J)) is sent out.

The frequency dividing circuit 5 of the PLL loop 1 performs a load operation by the load signal LD, and the variable signal VF is forced to fall (FIG. 14 (C)). In this it is falling time t _46, which means that Rifuarensu signal RF obtained retracted into Rifuarensu signal RF an Yotsute variable signal VF to lock this fall instantly to the point t ₄₆ when the one under standing ing. For this reason, the time from the fall of the reference signal RF to the fall of the variable signal VF is the operating time of the IC on the actual device, which is a minute time.

Thus, when the variable signal VF is pulled into the reference signal RF, the lock-in state is maintained by the pulling operation of the PLL loop 1 below.

Next, when the phase of the variable signal VF leads the phase of the reference signal RF, it operates as shown in FIG. That is, if the trailing edge of the variable signal VF falls ahead of the reference signal RF that falls at the time point t _{58 and} falls at the time point t ₅₄ , the control is not performed to give the load signal LD to the frequency dividing circuit 5. The PLL loop 1 tries to perform the pull-in operation so that the falling edge of the variable signal VF is locked to the falling edge of the reference signal RF at time t ₅₈ . In this operation, the falling phase of the variable signal VF at time t ₅₄ is the falling edge of the immediately preceding reference signal RF (time
Even if the phase is close to t ₅₁ ), the original operation of the PLL loop 1 tries to pull in the variable signal VF at the falling edge (time point t ₅₈ ) corresponding to the reference signal RF. However, this pull-in operation cannot be locked in during one cycle of the reference signal RF1 because the multiplication factor of the voltage controlled crystal oscillator 7 is extremely large.

However, in the case of FIG. 13, the pull-in direction switching circuit 31 generates a switching pulse CP2 (FIG. 15 (H)) to switch the operation mode of the phase frequency comparison circuit 2 from the advanced operation mode to the delayed operation mode. That is, at the time point t ₅₁ , the phase frequency comparison circuit 2 operates in the operation mode as shown in FIG. 15 (D) in relation to the logic state of the variable signal VF at the time when the preceding fall of the reference signal RF occurs. Transitions are made in the order of 11, 6, 7, and 12. When it falls from the logic "1" to logic "0" so that in D1 output (FIG. 15 (F)) of the phase frequency comparator circuit 2 is time t _54, O connexion inverter 44 to the trailing
The direction signal generating circuit 45 is reset via the control signal, and the pull-in direction control signal HH (FIG. 15 (G)), which is the output, is raised to logic "1".

Rifuarensu signal RF This state is generated at time t ₅₈
The window pulse signal WP (FIG. 15 (B)) corresponding to the trailing edge of is maintained until it is generated at time t ₅₆ .

Eventually at time t ₅₆ is the window pulse signal WP when standing rise to a logic "1", the output of the NAND circuit 46 triggers the Tatsuka connexion direction switching signal generating circuit 47 to "0" from logic "1". As a result, a switching pulse CP2 (FIG. 15 (H)) is generated, and this is inserted into the reference signal RF through the NOR circuit 37 of the input gate circuit 12 (FIG. 15 (A)).

Thus, at time t ₅₈ , before the reference signal RF rises, when the reference signal RF falls to the logic “0” based on the switching pulse CP2, the phase frequency comparison circuit 2
The operation mode of is switched to the operation mode when it is determined that the phase of the variable signal VF is behind the reference signal RF. That is, as can be seen from the flow table of FIG. 4, the operation modes of the phase frequency comparison circuit 2 from time t _{55 to} t ₆₁ are 11, 6, 7, 2, as shown in FIG. 15 (D).
As in 3 and 8, the operation modes are switched in the order different from the phase delay operation mode described above for the times t _{50 to} t ₅₅ .

As a result, when the variable signal VF falls at the time point t ₆₀ , the phase frequency comparison circuit 2 enters the state in which the pull-in operation is performed in the operation mode in which the fall signal is locked in to the trailing edge of the reference signal RF at the time point t ₅₈ . Become. However, even if the operation mode is switched in this way, the pull-in operation of the PLL loop 1 is not so fast, so when the third fall of the reference signal RF occurs at the time t ₆₂ , the pull-in operation of the PLL loop 1 itself is performed. According to the variable signal
VF cannot be pulled into the reference signal RF.

In the section t _{61 to} t ₆₄ near the trailing edge of the reference signal RF at the time point t ₆₂ , the operation mode of the phase frequency comparison circuit 2 is switched to 7, 5 and 8 as shown in FIG. As a result, at time t ₆₂ , the U1 output (Fig. 15 (E)) instantaneously falls to logic "0" and then logic "1".
Return to.

The rising of the U1 signal triggers the pull-in signal generation circuit 41 of the forced pull-in control circuit 17 to lower the forced pull-in control signal KH (FIG. 15 (I)) to logic "0".

At time t ₆₂ , the reference signal RF falls to the logic “0”, so that the inverted reference signal RF provided as the other input of the NAND circuit 42 has the logic “1”.
, The output of the NAND circuit 42 falls to the logic "0", and the trailing edge triggers the load signal generating circuit 43.

Therefore, the load signal LD is generated at time t ₆₂ , and the variable signal VF is generated by loading the frequency dividing circuit 5.
Is forced to fall from logic "1" to logic "0" (15th
(Figure (C)).

As a result, a state is obtained in which the trailing edge of the variable signal VF is immediately locked at the trailing edge of the reference signal RF at time t ₆₂ .

After that, the phase frequency comparison circuit 2 repeats the operation of the operation modes 7, 5 and 8 in which the variable signal VF is pulled into the reference signal RF at the time when the next falling edge of the reference signal RF occurs at the time point t ₆₅ , whereby the phase The lock state is maintained.

Thus, in the case of FIG. 15, when it is detected that the variable signal VF deviates from the window pulse signal WP, first, the phase frequency is set to the operation mode in which the direction signal generating circuit 45 of the pull-in direction switching circuit 31 can be set. It is determined whether or not the comparison circuit 2 is present. When the direction signal generation circuit 45 operates, the operation mode of the phase frequency comparison circuit 2 is switched by the switching pulse CP2 and the forced pull-in control circuit 17 is operated to load signal LD. Generate a variable signal immediately
VF will be pulled into the reference signal RF.

Therefore, in the case of FIG. 15 as well, the PLL loop 1 can lock the phase of the variable signal VF to the reference signal RF in a much faster time than in the conventional case.

On the other hand, when the trailing edge of the variable signal VF is slightly ahead of the trailing edge of the corresponding reference signal, the circuit of FIG. 13 operates as shown in FIG.

That is, if the reference signal RF falls at time t _{72 and the} variable signal VF falls at time t ₇₀ shortly before that, the phase frequency comparison circuit 2
Are operating modes 7, 12, 5, 8 as shown in FIG.
It changes like. Therefore, D1 of the phase frequency comparison circuit 2
Output falls to "0" from logic "1" at time t ₇₀ as shown in Figure No. 16 (F).

At this time, the direction signal generating circuit 45 of the pull-in direction switching circuit 31 is set by the fall of the D1 output, so that the output of the NAND circuit 46 falls from the logic "1" to "0" and the direction switching signal is generated. Trigger circuit 47. Therefore because the pull direction control signal HH rises to a logic "1", when the window pulse signal WP has one rising to a logic "1" at time t _77, the switching pulse CP2 triggers the direction switching signal generating circuit 47 generate.

Therefore, also at this time, the reference signal RF falls to the logic "0" based on the switching pulse CP2 before the reference signal RF falls at the time t ₇₉ .
The operation mode of the phase frequency comparison circuit 2 is switched to the phase delay mode.

Therefore, at time t ₈₃ , the load signal generation circuit 43 of the forced pull-in control circuit 17 is triggered and the load signal LD is transmitted,
At this point, the falling edge of the variable signal VF is locked in to the falling edge of the reference signal RF.

Therefore, also in the case of FIG. 16, the PLL loop 1 can pull in the variable signal VF to the reference signal RF in a very short time.

〔The invention's effect〕

As described above, according to the present invention, when the phase of the variable signal deviates from the window pulse signal, it is obtained at the output end by giving the load signal from the forced pull-in operation circuit to the frequency dividing circuit of the PLL loop. The variable signal to be locked can be immediately locked to a predetermined phase with respect to the window pulse signal, and as a result, the PLL loop can be locked in in a remarkably short time as compared with the case where the original pulling operation is performed. be able to.

In addition to this, when the PLL loop is in an operation mode that does not match the forced pull-in operation of the forced pull-in control circuit, the load signal can be generated after reversing the pull-in direction, so it is always stable and for a short time. A lock-in action can be obtained during.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit according to the present invention, and FIGS. 2 and 3 are phase frequency comparison circuits 2 thereof.
And a circuit diagram showing a detailed configuration of the charge pump 3, FIG. 4 is a diagram showing a flow table of the phase frequency comparison circuit 2,
5 to 8 are signal waveform diagrams showing the operation modes of the phase frequency comparison circuit 2, FIG. 9 is a signal waveform diagram showing the signals of the respective parts of FIG. 1, and FIG. 10 to FIG. 12 are phase frequency comparisons. FIG. 13 is a signal waveform diagram showing signals related to switching of the operation mode of the circuit 2, FIG. 13 is a block diagram showing a second embodiment of the PLL circuit according to the present invention, and FIGS. 14 to 16 show signals of respective parts thereof. It is a signal waveform diagram shown. 1 ... PLL loop, 2 ... Phase frequency comparison circuit, 3 ...
Charge pump, 5 ... Dividing circuit, 6 ... Low-pass filter, 7 ... Voltage-controlled crystal oscillator, 11 ... Reference signal forming circuit, 12 ... Input gate circuit, 14 ... Window signal forming circuit, 17 ... Forced retract control circuit, 31 …… Retract direction switching circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9182-5J H03L 7/08 Z

Claims (1)

[Claims] 1. A phase frequency comparison circuit compares the phase difference and frequency of a reference signal RF and a variable signal VF and controls the oscillation frequency of a voltage controlled crystal oscillator so as to eliminate the difference. A PLL loop that obtains the variable signal VF by dividing the oscillating output of the device using a divider circuit, and a predetermined window section in relation to the reference signal RF.
A window signal forming circuit that generates a window pulse signal WP having T _W, and a phase of the variable signal VF that generates a load signal LD when it is out of the window section T _W of the window pulse signal WP. A forced pull-in control circuit that locks the phase of the variable signal VF to a predetermined phase near the phase of the reference signal RF by performing a load operation on the frequency dividing circuit by using an LD, and the phase of the variable signal VF is When the forced pull-in control circuit deviates from the window section T _W of the window pulse signal WP in the direction opposite to the direction of the predetermined phase that can be locked, the forced pull-in direction of the PLL loop is changed to the forced pull-in direction. And a pull-in direction switching circuit that switches to a direction of the predetermined phase that can be locked by the control circuit.