JPH0793327B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0793327B2 JPH0793327B2 JP62319571A JP31957187A JPH0793327B2 JP H0793327 B2 JPH0793327 B2 JP H0793327B2 JP 62319571 A JP62319571 A JP 62319571A JP 31957187 A JP31957187 A JP 31957187A JP H0793327 B2 JPH0793327 B2 JP H0793327B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- semiconductor element
- gold
- alloy
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置に関し、特に半導体素子のマウン
ト部の構造を改良した半導体装置に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved structure of a mount portion of a semiconductor element.
［従来の技術］ 第２図は例えば、特開昭61−29142号公報に示された従
来の半導体装置を示す断面図であり、図において、１は
シリコン半導体素子２がマウントされるアイランド部、
３は後述する金ワイヤ９がボンディングされるリード部
であり、一部には銀層４が被覆されている。５は半導体
素子２の上面に蒸着されたベース、エミッタなどのアル
ミニウム電極、６は銅、バナジウム、アルミニウム、チ
タニウム、クロム、モリブデン、クロム合金から選ばれ
る１種または２種以上の金属からなる金属層、７はニッ
ケルもしくはコバールなどのニッケル合金からなる第２
金属層、８はゲルマニウムを５〜20％含む金及びゲルマ
ニウムを主成分とし、ろう材の構成材となる第３金属
層、９は半導体素子２のアルミニウム電極５に接地され
る金ワイヤで、他端はリード部３にポストボンディング
されている。なお、半導体素子２はアイランド部１の上
面に第３金属層８、第２金属層７、第１金属層６を介し
てマウントされている。[Prior Art] FIG. 2 is a cross-sectional view showing a conventional semiconductor device disclosed in, for example, Japanese Patent Application Laid-Open No. 61-29142, in which 1 is an island portion on which a silicon semiconductor element 2 is mounted,
Reference numeral 3 is a lead portion to which a gold wire 9 described later is bonded, and a part thereof is covered with a silver layer 4. Reference numeral 5 is an aluminum electrode such as a base or emitter deposited on the upper surface of the semiconductor element 2. Reference numeral 6 is a metal layer made of one or more metals selected from copper, vanadium, aluminum, titanium, chromium, molybdenum and chromium alloys. , 7 is the second made of nickel or nickel alloy such as Kovar
A metal layer, 8 is gold containing germanium in an amount of 5 to 20% and germanium as a main component, and a third metal layer serving as a brazing material, 9 is a gold wire grounded to the aluminum electrode 5 of the semiconductor element 2, and the like. The end is post-bonded to the lead portion 3. The semiconductor element 2 is mounted on the upper surface of the island portion 1 via the third metal layer 8, the second metal layer 7, and the first metal layer 6.
従来の装置は上記のように構成されており、第１及び第
２金属層６、７は、マウント時の熱処理に際し、半導体
素子２を構成するシリコンと第３金属層８とが反応する
のを阻止するものであり、半導体素子２とアイランド部
１の接合部に硬くて脆く、かつ熱抵抗の劣るAu−Cu−Si
の金属間化合物が形成されるのを防止する役目を有す
る。特に、第１金属層６はバリア効果の他に半導体素子
２と第２金属層７とを良好に接着する機能を有する。ま
た、第２金属層７は、バリア効果の他に第１金属層６と
第３金属層８とを良好に接着する機能があり、半導体素
子２に対して、ろう材を一体的に接着できる。The conventional device is configured as described above, and the first and second metal layers 6 and 7 prevent the silicon constituting the semiconductor element 2 from reacting with the third metal layer 8 during the heat treatment during mounting. Au-Cu-Si, which is hard and brittle at the junction between the semiconductor element 2 and the island 1 and has poor thermal resistance.
Has the role of preventing the formation of intermetallic compounds. In particular, the first metal layer 6 has a function of adhering the semiconductor element 2 and the second metal layer 7 well, in addition to the barrier effect. In addition to the barrier effect, the second metal layer 7 has a function of favorably adhering the first metal layer 6 and the third metal layer 8 to each other, so that the brazing material can be integrally adhered to the semiconductor element 2. .
［発明が解決しようとする問題点］ 従来の半導体装置は以上のように構成されているので、
半導体素子裏面より電極を取り出す半導体装置（例えば
小信号トランジスタ）のうち裏面の不純物濃度が低い素
子では、半導体素子と第１金属層とのオーミックコンタ
クト性が良好でないという問題点があった。[Problems to be Solved by the Invention] Since the conventional semiconductor device is configured as described above,
Among semiconductor devices (for example, small-signal transistors) in which electrodes are taken out from the back surface of a semiconductor element, there is a problem that an ohmic contact property between the semiconductor element and the first metal layer is not good in an element having a low back surface impurity concentration.
この発明は、上記のような問題点を解消するためになさ
れたもので、いかなる素子においても、オーミックコン
タクト性が良好となる半導体装置を得ることを目的とし
ている。The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device having good ohmic contact properties in any element.
［問題点を解決するための手段」 この発明に係る半導体装置は、半導体素子におけるマウ
ント面側にガリウムまたはアンチモンを0.01wt％〜30wt
％含む金合金からなり、膜厚が1000〜3000Åの第１金属
層と、ニッケル・ニッケル合金・銀から選ばれる１種ま
たは２種以上の金属からなり、膜厚が1000〜10000Åの
第２金属層と、金とゲルマニウムとの合金であって、上
記ゲルマニウムを5wt％〜20wt％含み、膜厚が0.5〜2.0
μｍの第３金属層とを順次積層した三層構造のろう材を
用い、銅もしくは銅合金の単体からなる基材に上記半導
体素子をマウントしたものである。[Means for Solving the Problems] The semiconductor device according to the present invention has gallium or antimony of 0.01 wt% to 30 wt% on the mount surface side of the semiconductor element.
% Of a gold alloy with a film thickness of 1000 to 3000Å and one or more metals selected from nickel, nickel alloy and silver, and a second metal with a film thickness of 1000 to 10000Å A layer and an alloy of gold and germanium, containing 5 wt% to 20 wt% of the above germanium, and having a film thickness of 0.5 to 2.0.
A brazing material having a three-layer structure in which a third metal layer having a thickness of μm is sequentially laminated is used, and the semiconductor element is mounted on a base material made of a simple substance of copper or copper alloy.
［作用］ この発明において、第１金属層の金に含まれるガリウム
（Ga）またはアンチモン（Sb）は、半導体素子裏面のオ
ーミックコンタクト性を良好にするよう機能する。[Operation] In the present invention, gallium (Ga) or antimony (Sb) contained in gold of the first metal layer functions to improve the ohmic contact property on the back surface of the semiconductor element.
［発明の実施例］ 次に本発明の一実施例を図について説明する。Embodiment of the Invention Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置のマウント後の状態の断面
図であり、図において、10は、例えばNPNバイポーラト
ランジスタ型半導体素子２のコレクタ側、すなわちマウ
ント面に不純物、例えばアンチモン（Sb）を0.04wt％含
む約2000Åの厚さの金被膜を構成する第１金属層、（1
1）は厚さ約3000Åのニッケル層からなる第２金属層、
（12）はゲルマニウム12wt％の厚さ約1.2μｍの金とゲ
ルマニウム合金層からなる第３金属層である。なお、半
導体素子２は第１金属層10、第２金属層11、第３金属層
12の順で積層し、銅単体からなるリードフレームのアイ
ランド部１に加熱押圧によってマウントされている。FIG. 1 is a cross-sectional view of the semiconductor device of the present invention after being mounted. In FIG. 1, reference numeral 10 denotes impurities such as antimony (Sb) on the collector side of the NPN bipolar transistor type semiconductor element 2, that is, the mount surface. The first metal layer forming the gold coating having a thickness of about 2000Å containing 0.04 wt%, (1
1) is a second metal layer consisting of a nickel layer with a thickness of about 3000Å,
(12) is a third metal layer made of germanium 12 wt% and a thickness of about 1.2 μm of gold and a germanium alloy layer. The semiconductor element 2 includes the first metal layer 10, the second metal layer 11, and the third metal layer.
12 layers are stacked in this order and mounted on the island portion 1 of the lead frame made of simple copper by heating and pressing.
上記のように構成されたものにおいては、まず、銅製薄
片板をプレス加工して銅単体からなるリードフレームを
作製する。つづいて複数個のNPNバイポーラトランジス
タが形成されたシリコン基板のマウント面に厚さ約2000
Åの金・アンチモン（Sb0.04wt％）合金層からなる第１
金属層（10）厚さ約3000Åのニッケル層からなる第２金
属層（11）、1.2μｍの金、ゲルマニウム（Ge12wt％）
合金層からなる第３金属層（12）を順次、真空蒸着法に
よって積層して、シリコン基板をその上面（マウント面
と反対側の面）よりスクライブして割断し、第１図に示
す半導体素子２を作製する。この後前述のリードフレー
ムのアイランド部１にマウントし、従来と同様に金ワイ
ヤをボンディングし、更に樹脂封止を施して半導体装置
を造る。In the structure as described above, first, a copper thin plate is pressed to produce a lead frame made of a simple substance of copper. Approximately 2000 thick on the mounting surface of the silicon substrate on which multiple NPN bipolar transistors are formed.
Å Gold-antimony (Sb0.04wt%) alloy layer 1st
Metal layer (10) Second metal layer (11) consisting of a nickel layer with a thickness of about 3000Å, 1.2 μm gold, germanium (Ge12wt%)
A third metal layer (12) made of an alloy layer is sequentially laminated by a vacuum vapor deposition method, and a silicon substrate is scribed and cut from the upper surface (the surface opposite to the mount surface), and the semiconductor element shown in FIG. 2 is produced. After that, the semiconductor device is manufactured by mounting on the island portion 1 of the lead frame described above, bonding a gold wire in the same manner as in the conventional method, and further sealing with a resin.
このように製造した半導体装置は、組立て直後において
も、また、２気圧150℃500時間の苛酷なテストを実施し
たあとでも十分良好な電気特性を保持した。The semiconductor device manufactured in this manner maintained sufficiently good electrical characteristics immediately after assembly and even after a harsh test at 150 ° C. for 2 hours and 500 hours.
なお、この発明は上記実施例に限定されない。例えば第
１金属層の主たる働きは、半導体素子のオーミックコン
タク性を良好にするためのものであるから、半導体素子
裏面がＮ型であればアンチモン（Sb）、Ｐ型であればガ
リウム（Ga）0.01wt％〜30wt％含んだ金被膜であればよ
い。また、それぞれの金属層の厚さは半導体素子への応
力歪を考慮して第１金属層が1000〜3000Å、第２金属層
が1000〜10000Å第３金属層が0.5〜2.0μｍとすること
が望ましいが、付着強度が十分高ければ、自由に選択し
てよい。なお、第３金属層中のゲルマニウムの酸化を防
止するため、この合金層上に更に金を500〜2000Å被覆
してもよい。要は、第３金属層及びこの金被膜全体で、
ゲルマニウム濃度が５〜20wt％であればよい。また更に
第２金属層（11）はニッケル、ニッケル合金、銀から選
ばれる１種または２種以上の金属層であればよい。ま
た、上前金属層の積層方法も真空蒸着法に限られている
訳ではなく、組成変化がなく、膜厚を制御できる装置で
あればどの装置でもよい。The present invention is not limited to the above embodiment. For example, the main function of the first metal layer is to improve the ohmic contact property of the semiconductor element, so if the back surface of the semiconductor element is N type, antimony (Sb), and if it is P type, gallium (Ga). Any gold coating containing 0.01 wt% to 30 wt% may be used. The thickness of each metal layer may be set to 1000 to 3000Å for the first metal layer, 1000 to 10000Å for the second metal layer and 0.5 to 2.0 μm for the third metal layer in consideration of stress strain on the semiconductor element. Although desirable, if the adhesion strength is sufficiently high, it may be freely selected. In order to prevent the oxidation of germanium in the third metal layer, the alloy layer may be further coated with gold in an amount of 500 to 2000 liters. In short, the third metal layer and the entire gold coating,
The germanium concentration may be 5 to 20 wt%. Furthermore, the second metal layer (11) may be one or more metal layers selected from nickel, nickel alloys, and silver. Further, the method of laminating the upper front metal layer is not limited to the vacuum vapor deposition method, and may be any apparatus as long as the composition does not change and the film thickness can be controlled.
本発明における素子配設基材は、酸化されやすいが、還
元されやすく清浄な面を表出し得る銅もしくは銅合金の
単体からなるものである。The element-arranged substrate in the present invention is made of a simple substance of copper or a copper alloy that is easily oxidized but can be easily reduced to expose a clean surface.
［発明の効果］ 以上のように、この発明による半導体装置は、第１金属
層にガリウム（Ga）またはアンチモン（Sb）を含んだ金
被膜を形成しているので、半導体素子裏面とのオーミッ
クコンタクト性が良好で、電気的特性が向上する効果が
ある。As described above, in the semiconductor device according to the present invention, since the gold coating containing gallium (Ga) or antimony (Sb) is formed on the first metal layer, ohmic contact with the back surface of the semiconductor element is achieved. Has good properties and has the effect of improving electrical characteristics.
第１図は本発明の一実施例である半導体素子のマウント
後の状態の断面図、第２図は従来の半導体装置を示す断
面図である。 図中、１はアイランド部、２は半導体素子、３はリード
部、４は銀被膜、５はA1電極、10は第１金属層、11は第
２金属層、12は第３金属層、９は金ワイヤ、10は金・ア
ンチモン層、11はニッケル層、12は金・ゲルマニウム合
金層である。 なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view of a semiconductor element according to an embodiment of the present invention after mounting, and FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, 1 is an island portion, 2 is a semiconductor element, 3 is a lead portion, 4 is a silver coating, 5 is an A1 electrode, 10 is a first metal layer, 11 is a second metal layer, 12 is a third metal layer, 9 Is a gold wire, 10 is a gold-antimony layer, 11 is a nickel layer, and 12 is a gold-germanium alloy layer. The same reference numerals in the drawings indicate the same or corresponding parts.
Claims (1)
金からなり、膜厚が1000〜3000Åの第１金属層と、 ニッケル・ニッケル合金・銀から選ばれる１種または２
種以上の金属からなり、膜厚が1000〜10000Åの第２金
属層と、 金とゲルマニウムとの合金であって、上記ゲルマニウム
を5wt％〜20wt％含み、膜厚が0.5〜2.0μｍの第３金属
層と を順次積層した三層構造のろう材を用い、銅もしくは銅
合金の単体からなる基材に上記半導体素子をマウントし
たことを特徴とする半導体装置。1. A first metal layer of a gold alloy containing 0.01 wt% to 30 wt% of gallium or antimony and having a film thickness of 1000 to 3000 Å and a nickel / nickel alloy / silver on the mount surface side of a semiconductor element. 1 or 2
A second metal layer made of at least one kind of metal and having a film thickness of 1000 to 10000Å and an alloy of gold and germanium, which contains 5 wt% to 20 wt% of the above germanium and has a film thickness of 0.5 to 2.0 μm. A semiconductor device in which the above-mentioned semiconductor element is mounted on a base material made of a simple substance of copper or a copper alloy, using a brazing material having a three-layer structure in which metal layers are sequentially laminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62319571A JPH0793327B2 (en) | 1987-12-16 | 1987-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62319571A JPH0793327B2 (en) | 1987-12-16 | 1987-12-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01160025A JPH01160025A (en) | 1989-06-22 |
| JPH0793327B2 true JPH0793327B2 (en) | 1995-10-09 |
Family
ID=18111749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62319571A Expired - Lifetime JPH0793327B2 (en) | 1987-12-16 | 1987-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793327B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009182209A (en) * | 2008-01-31 | 2009-08-13 | Nissan Motor Co Ltd | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51132968A (en) * | 1975-05-14 | 1976-11-18 | Nec Corp | Semiconductor device |
| JPS53145570A (en) * | 1977-05-25 | 1978-12-18 | Mitsubishi Electric Corp | Die bonding method of semiconductor device |
| JPS6222446A (en) * | 1985-07-22 | 1987-01-30 | Rohm Co Ltd | Forming method of ohmic electrode |
-
1987
- 1987-12-16 JP JP62319571A patent/JPH0793327B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01160025A (en) | 1989-06-22 |
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