JPH0793213A - Bank register setting circuit - Google Patents

Abstract

PURPOSE:To set a bank register with a DSP at high speed. CONSTITUTION:The setting of a bank register 103 is performed by the load of a memory address and a write signal to a memory while using not a data line but an address line from a DSP 101 for the input signal of the bank register 103. Thus, since the number of instruction steps required for setting the bank register 103 can be decreased rather than conventional, when accessing the memory while setting the bank register 103, the more the frequency is increased, the more the processing speed can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bank register setting circuit using a digital signal processor.

[0002]

2. Description of the Related Art Digital signal processors (hereinafter referred to as
The setting of the bank register connected to the system using the DSP) is often by memory mapped I / O. According to this method, bank registers that are originally mapped in the I / O space are mapped in the memory space.

FIG. 6 shows a system using a DSP.
1 shows a conventional bank register setting circuit. In the figure,
A DSP 601 outputs a write signal to the memory, a memory address (a bit) of the bank register, and data (d bit) set in the bank register, and 602 is a DS.
An address that outputs a latch signal for setting the bank register by determining whether to set the bank register based on the memory address (a bit) of the bank register and the write signal to the memory output from P601. Decoding circuit 603 is address decoding circuit 602
Is a bank register that sets the bank address to the bank address setting value (d bits) from the DSP 601 and outputs the d-bit bank address. Figure 9
FIG. 6 is a diagram showing a conventional memory mapping used in this description. In the figure, reference numerals 901 to 907 indicate memory addresses output by the DSP 601, and particularly the memory address FFH indicates a bank register. Further, other memory addresses indicate accesses to other memories than the bank register, that is, other memories. Further, FIG. 8 shows the DSP in the memory mapping of FIG.
The memory address (a bit) output from 601 is 8
6 is a diagram showing a configuration of an address decoding circuit 602 in the case of using bits. FIG. In the figure, reference numeral 801 is a DSP.
Is a write signal to the memory output from 601
In this description, it is a low active signal. Code 8
The reference numerals 02 to 809 represent the bits of the memory address from the DSP 601, and the largest number (a7) represents the MSB of the memory address.

FIG. 7 shows a processing flow of bank register setting in a conventional system using a DSP. The conventional example will be described below assuming that the number of bits of the bank register to be set is 4 bits and the number of bits of the memory address is 8 bits.

The setting of the bank address in the conventional example requires three steps of processing. First, the memory address of the bank register is set in the address line of the output of the DSP 601 (S701). In the case of this conventional example, the memory address of the bank register is 0FFH as shown in FIG.
0FFH is loaded to the address line of P601 output. That is, all the bits 802 to 809 in FIG. 8 are set to High. Secondly, the value set in the bank register is loaded into the data line of the DSP 601 (S702). When the bank register value to be set is 3H, 3H is loaded. When the memory address indicating the bank register is set (loaded) on the address line of the output of the DSP 601, and the data of the bank register setting value is set (loaded) on the data line, the DSP 601 thirdly outputs a write signal (low signal) to the memory. An active signal) is output (S703). That is, the signal of reference numeral 801 is set to Low. When the DSP 601 outputs a write signal to the memory, the output signal of the address decode circuit 602 changes by reference numeral 810, and this signal becomes a latch signal, and the signal of the data line of the DSP 601 in the bank register, that is, the main signal In the conventional example, 3H is set.
Therefore, the conventional bank register setting is S701.
Through S703, that is, three instruction steps in the SDP program.

[0006]

In the conventional bank register setting method in a system using a DSP, it takes three instruction steps to set the bank register. Therefore, when the bank register is set and the memory is accessed. , The more frequently the memory is accessed, the more DSP
There is a problem that the processing speed of is slow.

Therefore, an object of the present invention is to provide a bank register setting circuit which solves the above problems.

[0008]

To achieve the above object, the present invention comprises a digital signal processor for outputting a memory address and a write signal to the memory, a bit signal of a part of the memory address and the memory write signal. An address decode circuit for determining whether to set a bank register and outputting a setting signal for the bank register, the output signal of the address decode circuit and another part of the bit signal of the memory address. The bank address is set by and.

[0009]

The bank register is set by the memory address signal from the DSP and the write signal to the memory.
This reduces the number of steps required to set the bank register and enables high-speed processing.

[0010]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the processing arrangement of the present invention. In the figure, 101 is a DSP,
A write signal (low active signal) to the memory indicated by RITE * and a memory address are output. 102 is DS
An address that determines whether to set the bank register from the write signal to the memory output from P101 and the signal of a part of the bits of the memory address, and outputs the signal necessary for setting the bank address. Decoding circuit,
A bank register 103 outputs a bank address according to an output signal from the address decoding circuit 102 and a memory address signal from the DSP 101.

The processing contents in this embodiment will be described in more detail. Also in the description of this embodiment, the number of bits of the bank register to be set is 4 and the number of bits of the memory address is 8 as in the conventional example. Figure 2
[Fig. 6] is a diagram showing the processing steps of the present embodiment.
1, S202 shows the processing content in each step of this embodiment. Further, FIG. 5 is a diagram showing a memory mapping in the present embodiment, in which reference numeral 501 to reference numeral 5 are used.
06 indicates a memory address, particularly memory address 0F
The memory address between 0H and 0FFH indicates the bank register. FIG. 3 is an example of a circuit configuration of the address decoding circuit 102 in the present invention in the memory mapping of FIG. In the figure, reference numeral 301 is a write signal (low active) from the DSP 101 to the memory, and reference numerals 302 to 305 are some of the bits of the memory address from the DSP 101. Also, 302 to 3
The larger number of 05 indicates closer to MSB.

In this embodiment, when setting the bank register 103, the DSP 101 first sets (loads) a memory address indicating the bank register on the address line. In the present embodiment, since the upper 4 bits of the memory address indicating the bank register are all areas indicating High according to FIG. 5, the upper 4 bits of the memory address are set to High. These 4 bits correspond to the A1 bit in FIG. 1 and are connected to the address decoding circuit 102. The remaining lower 4 bits of the memory address correspond to the A2 bit of FIG. 1 and are connected to the bank register 103. In this embodiment, the value set in the lower 4 bits is the set value of the bank register. That is, the bank register 103 has 3H
In case of setting, 3H is set in the lower 4 bits of the memory address. Therefore, in this example, the DSP
101 sets (loads) 0F3H (11110011 ₂ ) as an 8-bit memory address (S20
1). The DSP 101 then outputs a write signal (low active) to the memory (S202).

At this stage, if the upper 4 bits of the memory address are not High, the DSP 101 does not access the bank register 103. However, in the present description, since the upper 4 bits are set to High, the bank register 103 is accessed. Will be done. When the write signal to the memory is output from the DSP 101, the latch signal for setting the bank register 103 is output by the decoding process of the address decoding circuit 102 (logic gate indicated by reference numeral 306).

FIG. 4 shows an example of the circuit of the bank register 103. In the figure, reference numerals 401 to 404 denote D flip-flops (hereinafter, referred to as DFFs) that latch data of lower 4 bits (a0, a1, a2, a3) of a memory address.
0, BA1, BA2, and Ba3 indicate set bank addresses, and the larger the number, the closer to the MSB. Therefore, the latch signal is the address decode circuit 1
When it is output from 02, the value of the lower 4 bits of the memory address is latched by the DFF 401 to the DFF 404.
That is, the values of a0, a1, a2, a3 are BA0, BA
1, BA2 and BA3 are set. Therefore, in the present embodiment, the lower 4 bits of the 8-bit memory address 0FH, 3H, is set, and the bank register 1
The setting of 03 is completed.

[0016]

According to the present invention, memory mapped I / O
Since the bank register setting in the DSP can be realized by the two instruction steps of loading the memory address and outputting the write signal to the memory, the DSP processing speed can be increased when the DSP memory access frequency is high. Becomes

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow of the embodiment.

FIG. 3 is a diagram showing an example of an address decoding circuit shown in FIG.

FIG. 4 is a diagram showing an example of the bank register circuit shown in FIG.

FIG. 5 is a diagram showing memory mapping in the example.

FIG. 6 is a diagram showing a configuration of a bank register setting circuit in a conventional example.

FIG. 7 is a diagram showing a processing flow in a conventional example.

8 is a diagram showing an example of an address decoding circuit in FIG.

FIG. 9 is a diagram showing memory mapping in a conventional example.

[Explanation of symbols]

 101 Digital Signal Processor 102 Address Decode Circuit 103 Bank Register

Claims (1)

[Claims] 1. A digital signal processor that outputs a memory address and a write signal to the memory, and determines whether to set a bank register from a bit signal of a part of the memory address and the memory write signal. An address decoding circuit that outputs a setting signal of the bank register, and the bank address is set by the output signal of the address decoding circuit and a bit signal of another part of the memory address. Register setting circuit.