JPH0787459A - Noise reduction device - Google Patents

Abstract

PURPOSE:To reduce the noise in a video signal including time base fluctuation with a simple circuit configuration by forming a delay circuit with a variable delay circuit and controlling an output of the variable delay circuit so as to have the same time base fluctuation as that of an input video signal. CONSTITUTION:A synchronizing separator circuit 4 separates a horizontal synchronizing signal 9 from an input video signal 6 and the signal 9 is fed to one input terminal of a phase difference detection circuit 5. A reference horizontal synchronizing signal 9 is inputted to the other input terminal of the phase difference detection circuit 5. The phase difference detection circuit 5 detects a phase difference between the horizontal synchronizing signal 9 and the reference horizontal synchronizing signal 8 to control a delay time of the variable delay circuit 2 based on the result of detection. Thus, an output of the variable delay circuit 2 has time base fluctuation matched with time base fluctuation of an input video signal 6. Thus, it is not required to use a clock whose phase is synchronous with the input video signal and the system is formed by using a fixed clock and the circuit configuration of the noise reduction device is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to noise reduction (hereinafter
(Referred to as NR).

[0002]

2. Description of the Related Art FIG. 11 shows a conventional cyclic NR device.
The input video signal is input to the adder 100 and this adder 100
Is the output of the NR device. The coefficient device 102 for multiplying the fixed delay device 101 and the constant K is in the feedback system, and returns to the adder 100. In this cyclic NR device, the fixed delay circuit is
For example, it is a horizontal synchronization period delay, in which case it is a vertical low-pass filter LPF. Then, by adding the above-mentioned delayed signal to the input video signal in the adder 100,
NR operation is performed. When the fixed delay circuit 101 performs the field delay, the field NR operation is performed, and when the fixed delay circuit 101 performs the frame delay, the frame NR operation is performed.

FIG. 12 shows another conventional NR device. This NR device is a modification of FIG. Second subtraction circuit 110
Subtracts the output signal of the fixed delay circuit 111 from the input video signal. The result of this subtraction is a signal decorrelation component and noise. The amplitude is limited by the amplitude controller LIM112 to extract the noise component. The extracted noise is multiplied by K in a coefficient unit 113 that determines the loop feedback gain, and is supplied to one input terminal of the first subtractor 114. Further, the input video signal is supplied to the other input terminal of the first subtractor 114 via the delay circuit 115 for system delay adjustment. The first subtractor 114 subtracts the noise component from the coefficient multiplier 113 from the video signal from the delay circuit 115, and becomes the output video signal of the NR device. Further, this output video signal is supplied to the fixed delay circuit 111 described above. The decorrelation detection circuit 116 receives the subtraction result of the second subtraction circuit 110 and determines that it is uncorrelated when the input is large. Then, according to the decorrelation level, the coefficient unit 11
By making the coefficient value K of 3 variable, the harmful effect at the time of signal non-correlation is reduced. The fixed delay circuit 111 performs one horizontal synchronization period delay, field delay, and frame delay as described in the NR device of FIG.

Furthermore, H-PLL (Horizontal-Phase Loc)
ked Loop) 117 is a clock C used as a system clock CK when the NR device is configured by a digital circuit.
It is a generator of K and generates a clock CK that is phase-synchronized with the horizontal synchronizing signal of the input video signal.

Next, the jitter of the VTR reproduced video signal will be described. FIG. 13 shows a time axis shift due to jitter.
FIG. 13A shows an input video signal without jitter. In the figure, one square represents one field and the time direction is downward. VTR recorded and played back this input video signal with VTR
The reproduced signal is shown in FIG. 13 (b). The frame is wavy due to jitter. The waveform of the 1-line video signal indicated by the circle in FIG. 13 (b) is shown in FIG. 13 (c). The signal one frame before point B is point A. This VTR reproduction signal has a time axis shifted due to jitter. When these two signals are frame-added, there is a time lag and waveform distortion occurs.

The above-mentioned waveform distortion will be described with reference to FIG. In the figure, the input video signal (corresponding to point B in FIG. 13B) and the output of the fixed delay circuit (corresponding to point B in FIG. 13B) have time lag due to jitter. The result of adding these two signals is the bottom waveform diagram. As shown in the figure, there are two main lines at the portion corresponding to the vertical line, which is what is called two-line blur. In order to avoid this two-point blurring, it is common to use a clock that is phase-synchronized with the horizontal synchronizing signal of the input video signal as the operation clock CK of the frame delay memory that is the fixed delay circuit. Therefore, H-PLL11
7 is needed.

Next, problems in circuit configuration will be described. The input in FIG. 15 is the case of a signal modulated by a color subcarrier, such as a carrier color signal. In this case, the sub-carrier which is the modulation carrier of the VTR reproduced image has the time base fluctuation removed by the double heterodyne method, but the color base band signal such as the color difference signal is basically not subjected to the time base correction. Therefore, as shown in FIG. 15, the first clock CK phase-synchronized with the color burst signal of the input carrier color signal,
Two system clocks CK and a second clock CK that is phase-synchronized with the horizontal synchronizing signal of the input video signal correspond to the time axis fluctuation.

This will be described with reference to FIG. The color burst-PLL 120 generates a first clock CK that is phase-synchronized with the color burst of the input carrier color signal. The H-PLL 123 generates a second clock CK that is phase-synchronized with the horizontal synchronizing signal of the input video signal. The decoder DEC121 uses the clock CK of the above 1
In accordance with the above, the input carrier color signal is decoded and converted into a color difference signal which is a baseband signal. The sample rate converter SRC122 changes the color difference signal from the decoder DEC121 from the first clock CR to the second clock CK. Next, the NR device 124 described above performs NR processing in accordance with the second clock to reduce noise. The sample rate converter 125 changes the clock CK of the color difference signal subjected to the NR process. The operation of the sample rate converter 125 is the reverse of the operation of the sample rate converter 122. Encoding E
The NC 126 re-encodes the color difference signal with the color subcarrier according to the first clock CK and outputs a carrier color signal from which noise has been removed.

As described above, in the NR device that handles the carrier color signal, the sample rate converters 122 and 125 are required, and the color burst-PLL120 and H-PLL123 are required to generate the system clock, so that the circuit scale is increased. Resulting in.

[0010]

The conventional NR device has the following drawbacks.

First, an input video signal having a time base fluctuation is set to N
In order to perform NR processing in the R device, a clock CK that is phase-synchronized with the horizontal synchronizing signal of the input video signal is required, and therefore the H-PLL is indispensable, which increases the circuit scale.

Next, when a carrier color signal or other modulated signal having a time axis fluctuation is handled, as a system clock, as described above, a color subcarrier, that is, a first carrier which is phase-synchronized with a so-called carrier and a color difference signal of an input video signal, respectively. And a second clock is needed. Therefore, burst-PLL and H-PLL
And are required. Further, a sample rate converter SRC for converting the transmission rate because the clock CK needs to be replaced
A sample rate converter SRC, which is inverse to the above, is required for the NR device. As a result, the circuit scale is increased in the NR device such as the carrier color signal.

It is an object of the present invention to provide an NR device that applies NR to a signal with a time base fluctuation with a simple circuit configuration.

[0014]

(Structure Example 1) Addition means for supplying an input video signal to one input terminal and an output video signal to the output terminal, and an output video signal from the output terminal of this adder Variable delay means for delaying the output video signal and the output from the variable delay circuit are inputted, the inputted signal is multiplied by a constant, and the signal is supplied to the other input terminal of the adding means. Coefficient means, a sync separating means for separating a horizontal synchronizing signal from the input video signal, a horizontal synchronizing signal generating means for generating a reference horizontal synchronizing signal, a horizontal synchronizing signal from the synchronizing separating means and the horizontal synchronizing signal. Phase difference detecting means for detecting the phase difference from the reference horizontal synchronizing signal from the generating means and controlling the delay time of the variable delay means based on the detection result, and outputting the output of the variable delay means. Controls to have the same time base fluctuations as the time axis variation of the filling power video signal.

(Structure Example 2) An adding means for supplying an input video signal to one input terminal and an output video signal for an output terminal, and a variable delay means for receiving the input video signal and delaying the input video signal. The output from the variable delay means is inputted, the inputted signal is multiplied by a constant, the coefficient means for supplying a signal to the other input terminal of the adding means, and the horizontal synchronizing signal from the input video signal. Sync separating means for separating, horizontal synchronizing signal generating means for generating a reference horizontal synchronizing signal, and a phase difference between the horizontal synchronizing signal from the synchronizing separating means and the reference horizontal synchronizing signal from the horizontal synchronizing signal generating means. And a phase difference detection means for controlling the delay time of the variable delay means based on the detection result, and the output of the variable delay means is changed to the same time axis fluctuation as the time axis fluctuation of the input video signal. Tsuyo to control.

(Structural Example 3) An input video signal is input, delay means for adjusting the input video signal to the system time, and the input video signal from this delay means is supplied to one input terminal and output terminal is output. First subtracting means for supplying a video signal, variable delay means for receiving the output video signal from the output terminal of the first subtracting means, and delaying the output video signal, and the variable delay from the input video signal Second subtracting means for subtracting the output of the means, amplitude limiting means for limiting the amplitude of the output of the second subtracting means, and output of the amplitude limiting means are input, and the input signal is multiplied by a constant. , A coefficient means for supplying a signal to the other input terminal of the first subtraction means and a signal from the second subtraction means to detect non-correlation, and control the multiplier of the coefficient means based on the detection result. Do Correlation detecting means, sync separating means for separating a horizontal synchronizing signal from the input video signal, horizontal synchronizing signal generating means for generating a reference horizontal synchronizing signal, horizontal synchronizing signal from the synchronizing separating means, and horizontal synchronizing signal generating Means for detecting the phase difference from the reference horizontal synchronizing signal from the means, and controlling the delay time of the variable delay means based on the detection result. The output of the variable delay means is the input image. It is characterized in that it is controlled so as to have the same time-axis fluctuation as the time-axis fluctuation of the signal.

[0017]

By using the variable delay circuit as a variable delay circuit adapted to the time base fluctuation of the input video signal, each output signal of the variable delay circuit such as N line delay, N field delay, or N frame delay is described above. It is assumed that the signal has a time axis fluctuation that matches the time axis fluctuation of the input video signal. For this reason,
There is no problem even if signal processing such as addition or subtraction is performed on the input video signal and the output of the variable delay circuit. As a result, when the NR device has a digital configuration, the system clock CK can be unified, and only one PLL as a clock generator is required. Alternatively, a fixed oscillator may be used. Further, even when the NR is applied to the modulation signal such as the carrier color signal, it is sufficient to use the clock CK locked to the color subcarrier as the system clock CK.
A circuit with a small EC and encoder ENC is sufficient, and the sample rate converter SRC and the inverse sample rate converter SRC are unnecessary.

[0018]

1 shows a cyclic NR device which is a first embodiment of the NR device of the present invention. The adder 1 adds the input video signal 6 and the delayed signal and outputs a video signal 7. The aforementioned delay signal is a feedback signal obtained by passing the output video signal 7 through the variable delay circuit 2 and the coefficient unit 3. The sync separation circuit 4 separates the horizontal sync signal 9 from the input video signal 6 and supplies it to one input terminal of the phase difference detection circuit 5. The reference horizontal synchronization signal 8 is input to the other input terminal of the phase difference detection circuit 5. The phase difference detection circuit 5 detects the phase difference between the horizontal synchronization signal 9 and the reference horizontal synchronization signal 8 and controls the delay time of the variable delay circuit 2 based on the detection result. As a result, the output of the variable delay circuit 2 has a time axis fluctuation that matches the time axis fluctuation of the input video signal 6.

FIG. 2 shows a non-recursive NR device which is a second embodiment of the NR device of the present invention. The adder 10 adds the input video signal 16 and the delay signal. After that, the coefficient unit 11 sets 1
It is multiplied by / (1 + K) and the video signal 17 is output. The delay signal is a signal for inputting the input video signal 16 to the adder 10 via the variable delay circuit 12 and the coefficient unit 13. Sync separation circuit
Reference numeral 14 separates the horizontal synchronizing signal 19 from the input video signal 16 and supplies it to one input terminal of the phase difference detecting circuit 15. The reference horizontal synchronization signal 18 is input to the other input terminal of the phase difference detection circuit 15. The phase difference detection circuit 15 uses the horizontal sync signal 19
And the reference horizontal synchronizing signal 18 are detected, and the delay time of the variable delay circuit 12 is controlled based on the detection result. As a result, the output of the variable delay circuit 12 has a time axis fluctuation that matches the time axis fluctuation of the input video signal 16.

FIG. 3 shows a modification of the cyclic NR device which is the third embodiment of the NR device of the present invention. Second subtractor 20
Subtracts the delay signal from the input video signal 29 to extract the non-correlation component and noise of the signal. The subtraction signal becomes a noise component having a small amplitude level via the amplitude limiter LIM21 and the coefficient unit 22, and is supplied to one input terminal of the first subtractor 24. The input video signal 29 is supplied to the first subtractor 24 via the delay circuit 23 for adjusting the system time.

The first subtractor 24 subtracts noise from the input video signal from the delay circuit 23, and this output becomes the output video signal 30 of the NR device. This output is delayed by the variable delay circuit 25 and becomes the above-mentioned delayed signal which is the input of the second subtractor 20. The sync separation circuit 26 separates the horizontal sync signal 32 from the input video signal 29 and supplies it to one input terminal of the phase difference detection circuit 27. The reference horizontal synchronization signal 31 is input to the other input terminal of the phase difference detection circuit 27. Phase difference detection circuit 27
Detects the phase difference between the horizontal synchronizing signal 32 and the reference horizontal synchronizing signal 31, and controls the delay time of the variable delay circuit 25 based on the detection result. As a result, the output of the variable delay circuit 25 is
It has a time axis variation that matches the time axis variation of the input video signal 29. Further, the decorrelation detection circuit 28 receives the subtraction result of the second subtraction circuit 20, and when the input is large, determines that the correlation is uncorrelated. Then, depending on the decorrelation level, the multiplication value K of the coefficient unit 22 is changed to reduce the harmful effects at the time of signal decorrelation.

Although three examples of the NR device of the present invention have been described above, these use a variable delay circuit. As described above, the output signal of the variable delay circuit is changed with respect to the time base fluctuation of the input video signal. This is to make the NR processing correct by matching the time axis fluctuation amounts. Therefore, when these NR devices are configured by digital circuits, a single clock CK may be used as the system clock CK, which is one of the problems in the conventional example, that is, color burst-PLL and H-PLL.
Two clock CK generators can be deleted. Further, even if the fixed clock CK generator is used to generate the system clock CK, there is no systematic problem.

Next, the case of the NR processing of the carrier color signal, which is the second problem, will be described. FIG. 4 shows a circuit configuration when a carrier color signal is input. Decoder DEC41
Decodes the input carrier color signal into a baseband signal of the color difference signal. As the NR device 42, the one shown in the first to third embodiments is adopted, and the NR process of the color difference signal is carried out. The concoder ENC43 again encodes the color difference signal after the NR processing with the color subcarrier, and outputs the carrier color signal from which noise is removed. Since the variable delay circuit of the present invention is adopted in the NR device, when this system is configured by a digital circuit, the system clock CK for operating the decoder DEC41, the NR device 42 and the encoder ENC43 may have one clock generator 40. . Decoder DEC
Since the 41 and the encoder ENC43 can be configured by the simplest exclusive-OR EOR, the clock CK of the clock generator 40 may be the frequency of the quadruple color subcarrier, which simplifies the circuit configuration. . Instead of the clock generator 40, a clock having a quadruple color sub-carrier frequency may be generated in phase synchronization with the color burst of the input carrier color signal.

Next, some embodiments of the variable delay circuit will be shown. FIG. 5 shows the case of an analog circuit configuration, in which the CCD delay circuit 50 is used as the variable delay circuit. still,
The input video signal 56 of the CCD delay circuit 50 corresponds to the output video signal 7 in the embodiment of FIG. 1, the input video signal 16 in the embodiment of FIG. 2, and the output video signal 30 in the embodiment of FIG. Equivalent to. The output of the CCD delay circuit 50 corresponds to each output of the variable delay circuits of the first to third embodiments. CC
The D delay circuit 50 operates as a variable delay circuit and outputs an output video signal 57 having the same time-axis fluctuation amount as the input video signal 56.

To control the CCD as a variable delay circuit, the operation clock of the CCD delay circuit 50 may be controlled. The clock CK control will be described in detail below.
The first sync separation circuit A51 separates the first horizontal sync signal 58 from the input video signal 56 and supplies it to one input terminal of the phase difference detection circuit 53. The second sync separation circuit B52 separates the second horizontal sync signal 59 from the output video signal 57 and supplies it to the other input terminal of the phase difference detection circuit 53. Phase difference detection circuit
53 detects the phase difference between the two horizontal synchronizing signals and limits the detection result by a loop filter 54 to obtain a control signal. The control signal controls the VCO 55 to obtain the operation clock of the CCD delay circuit 50. In this way, a feedback loop is applied to control the delay time so as to match the fluctuation of the input video signal on the time axis. This is an analog variable delay circuit using a CCD.

It should be noted that one of the first and second horizontal synchronizing signals 58 and 59 becomes the above-mentioned reference horizontal synchronizing signal in the relationship of the embodiments of FIGS.

Next, the structure of a variable delay circuit using a digital memory will be described. The following description is a control method with the system clock CK as one unit. No correction is made for the delay time within one clock, but there are few problems when actually used as an NR device. However, if the delay time within 1 clock CK becomes a problem, it is possible to further control the delay time within 1 clock CK,
It will be described later.

FIG. 6 shows a second embodiment of a variable delay circuit using a digital memory. The input video signal 64 of the memory 60 corresponds to the output video signal 7 in the embodiment of FIG.
In the embodiment of FIG. 2, it corresponds to the input video signal 16, and in the embodiment of FIG. 3, it corresponds to the output video signal 30. The output of the memory 60 is
These correspond to the outputs of the variable delay circuits of the first to third embodiments.

The memory 60 performs write side processing with a write clock (write clock) and write address (write address), and performs read side processing with a read clock (read clock) and read address (read address). Here, the write clock and the read clock are implemented by the same system clock CK to control the address side. First, regarding the address control method, the write side divides the write address counter 61 into upper and lower sides. The address counter is divided into upper and lower
This is for performing signal writing / reading with the memory map shown in FIG. 7. First, FIG. 7 will be described. Figure 7
Is a two-dimensional memory map, and lower addresses relate to horizontal processing of video signals. This handles signals on a pixel-by-pixel basis. The upper address relates to the vertical processing of the video signal. This is a process for each line in the vertical direction on the TV screen. Therefore, the lower address writes / reads the video signal of each line from the predetermined address.

Returning to FIG. 6, the logic circuit 62 sets the address counter to a predetermined address from the horizontal synchronizing signal 66 of the input video signal. The above is the configuration of the variable delay circuit using the digital memory.

The above will be described in detail with reference to FIG. Figure 8
The light set signal of 1 is generated in the horizontal unit of the video signal in this example. In the memory writing video signal, the first pixel of the horizontal synchronizing signal is written in a predetermined lower address, and pixel information is written in the memory in the following order. The a0 pixel (nth line) in FIG. 8 is written in the upper left address on the memory map. At the next a1, the lower address is incremented by 1 and written. Since the light set signal is output on the next line, the write video signal is b0 ((n +
1) Write line 1) to the lower address of the default address. However, in this case, the upper address is advanced by one. b1
Writes at an address obtained by advancing the lower address by one with the same upper address. Similarly, the reading side uses the read set signal obtained from the horizontal synchronizing signal of the input video signal as a reference when reading the n-th line. When the read set signal is output, the read counter is changed to the default lower address and a0 is set.
Read pixels. The following a1 pixels are read in order. (N
At the (+1) th line, a read set signal is newly output, so the lower address is set as the default address and the upper address is incremented by one. This address is read and the b0 pixel is read. The (n + 1) th line is read out in the following order.

Although signals are written to the memory for a certain period of time, discontinuity occurs in the memory write / read signals at the time of write set or read set. This gives the same time base fluctuation to the output of the variable delay circuit with respect to the time base fluctuation of the input video signal, and is not a system problem. If this is utilized, it is not necessary to write / read all pixels in the video signal. It is not necessary to write to or read from the memory during the horizontal / vertical blanking period, and the memory capacity can be reduced.

The configuration of the variable delay circuit using the memory has been described above. The delay time of the variable delay circuit used here is one horizontal synchronization period or a plurality of horizontal synchronization periods. Further, it includes field unit delay, frame unit delay, and the like.

Next, a delay time correction method within 1 clock CK will be described. FIG. 9 shows an embodiment of a time axis correction method within 1 clock CK. The input video signal 73 corresponds to the output video signal 7 in the embodiment of FIG. 1, the input video signal 16 in the embodiment of FIG. 2, and the output video signal in the embodiment of FIG.
Equivalent to 30. The output video signal 74 corresponds to each output of the variable delay circuits of the first to third embodiments.

In FIG. 9, the first variable delay circuit A70
Is a variable delay circuit using the memory of FIG. Second
The variable delay circuit B71 of is a circuit that corrects the time base fluctuation within one clock CK. The phase difference detection circuit 72 detects the phase difference between the horizontal synchronizing signal 75 of the input video signal and the reference horizontal synchronizing signal 76. Then, the detected phase difference is set to the system clock C.
It is divided into K units (time is a time unit of 1 / CK frequency) and a time axis fluctuation amount within 1 clock CK. The phase difference control for each clock CK is performed by the first variable delay circuit A70. The phase correction within 1 clock CK is performed by the second variable delay circuit B71 which is a phase shifter.

FIG. 10 shows a configuration example of the second variable delay circuit B71. This is a coefficient variable filter, and the time axis fluctuation is corrected by controlling the coefficient with the component 80 within one clock of the phase difference detection signal. The configuration includes minute delay circuits 81 to 85 that delay the input video signal for a certain period, coefficient units 86 to 91 that multiply the output of each delay circuit by a filter coefficient, and an adder 92. Then, the output of the adder 92 becomes the output video signal 74. The coefficient k0 to k (n + 1) of the coefficient unit is the phase control signal 80
Control with. As described above, by configuring the second variable delay circuit B71, it is possible to cope with the time axis fluctuation within 1 clock CK. In the case of digital signal processing, the circuit configuration described above can be a system configuration with the fixed clock CK. Further, in the case of the carrier color signal, the system operation can be performed with a single clock CK that is a clock for the color subcarrier.

[0037]

As described above, since the delay circuit is constituted by the variable delay circuit, it is necessary to use the clock CK that is phase-synchronized with the input video signal even if the input video signal with time axis fluctuation is input. The system can be assembled with a fixed clock. Further, it becomes possible to configure the system with a single clock CK in which a modulation signal such as a carrier color signal is phase-synchronized with a color subcarrier. Therefore, the circuit configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of an NR device of the present invention.

FIG. 2 is a diagram showing a configuration of a second embodiment of the NR device of the present invention.

FIG. 3 is a diagram showing a configuration of a third embodiment of the NR device of the present invention.

FIG. 4 is a diagram in which the NR device of the present invention is used for NR of a carrier color signal.

FIG. 5 is a diagram showing a configuration of an embodiment of a variable delay circuit used in the NR device of the present invention.

FIG. 6 is a diagram showing a configuration of an embodiment of a variable delay circuit used in the NR device of the present invention.

7 is a memory map for explaining the operation of the variable delay circuit of FIG.

8 is a waveform diagram illustrating an operation of the variable delay circuit of FIG.

FIG. 9 is a diagram showing a configuration of an embodiment of a variable delay circuit used in the NR device of the present invention.

10 is a diagram showing a configuration of a second variable delay circuit B of FIG.

FIG. 11 is a diagram showing a configuration of a conventional NR device.

FIG. 12 is a diagram showing a configuration of a conventional NR device.

FIG. 13 is a diagram illustrating an operation of a conventional NR device.

FIG. 14 is a diagram illustrating an operation of a conventional NR device.

FIG. 15 is a diagram in which a conventional NR device is adopted for NR of a carrier color signal.

[Explanation of symbols]

1, 10 ... Adder, 2, 12 ... Variable delay circuit, 3, 13 ... Coefficient device, 11 ... Coefficient device, 4, 14 ... Sync separation circuit, 5, 15 ... Phase difference detection circuit, 20 ... Second subtraction Vessel, 21 ... Amplitude limiter LI
M, 22 ... Coefficient multiplier, 23 ... Delay circuit, 24 ... First subtractor, 25
... Variable delay circuit, 26 ... Sync separation circuit, 27 ... Phase difference detection circuit, 28 ... Correlation detection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Koga 8 Shinsita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture

Claims (10)

[Claims] 1. An adding means for supplying an input video signal to one input terminal and an output video signal for an output terminal, and an output video signal from an output terminal of the adder,
Variable delay means for delaying the output video signal, and coefficient means for receiving the output from the variable delay circuit, multiplying the input signal by a constant, and supplying the signal to the other input terminal of the adding means. A sync separator for separating a horizontal sync signal from the input video signal; a horizontal sync signal generator for generating a reference horizontal sync signal; a horizontal sync signal from the sync separator and a reference from the horizontal sync signal generator; A phase difference detecting means for detecting a phase difference from a horizontal synchronizing signal and controlling the delay time of the variable delay means based on the detection result, wherein the output of the variable delay means is the time axis of the input video signal. A noise reduction device characterized by controlling so as to have the same time-axis fluctuation as fluctuation. 2. An addition means for supplying an input video signal to one input terminal and an output video signal for an output terminal, and a variable delay means for receiving the input video signal and delaying the input video signal. An output from the variable delay means is inputted, the inputted signal is multiplied by a constant, and a coefficient means for supplying a signal to the other input terminal of the adding means, and a synchronization for separating a horizontal synchronizing signal from the input video signal. Separating means, horizontal synchronizing signal generating means for generating a reference horizontal synchronizing signal, phase difference between the horizontal synchronizing signal from the synchronizing separating means and the reference horizontal synchronizing signal from the horizontal synchronizing signal generating means, and this detection Phase difference detection means for controlling the delay time of the variable delay means based on the result, and the output of the variable delay means has the same time axis fluctuation as the time axis fluctuation of the input video signal. Noise reduction apparatus characterized by Gosuru. 3. An input video signal is input, a delay means for adjusting the input video signal to the system time, the input video signal from the delay means is supplied to one input terminal, and an output terminal outputs the output video signal. First subtracting means for supplying, variable delay means for inputting an output video signal from an output terminal of the first subtracting means, delaying the output video signal, and output of the variable delay means from the input video signal A second subtracting means for subtracting, an amplitude limiting means for limiting the amplitude of the output of the second subtracting means, and an output of the amplitude limiting means are inputted, and the inputted signal is multiplied by a constant, A coefficient means for supplying a signal to the other input terminal of the first subtraction means; and a signal from the second subtraction means to detect decorrelation,
A decorrelation detecting means for controlling a multiplier of the coefficient means based on the detection result, a sync separating means for separating a horizontal synchronizing signal from the input video signal, a horizontal synchronizing signal generating means for generating a reference horizontal synchronizing signal, Phase difference detecting means for detecting the phase difference between the horizontal synchronizing signal from the synchronizing separating means and the reference horizontal synchronizing signal from the horizontal synchronizing signal generating means, and controlling the delay time of the variable delay means based on the detection result. And a control circuit for controlling the output of the variable delay means so as to have the same time-axis fluctuation as the time-axis fluctuation of the input video signal. 4. The variable delay means is composed of a CCD delay means, and a clock frequency of the CCD delay means is controlled by a time base fluctuation amount of the input video signal. Noise reduction device. 5. The variable delay means comprises a memory,
The noise reduction device according to claim 1, 2 or 3, wherein a write address and a read address of the memory are controlled by a time-axis fluctuation amount of the input video signal. 6. The variable delay means is composed of a memory and a signal phase shifter, and the phase difference detecting means for detecting the amount of phase fluctuation of the input video signal, and the detection result of the phase difference detecting means are stored in the system clock time. A dividing unit for dividing the value into an integer multiple and a value below the decimal point, controlling the write address and the read address of the memory at an integral multiple of the system clock time which is the detection result of the phase difference detecting unit, and 4. The noise reduction device according to claim 1, wherein the signal phase shifter is controlled based on the decimal point of the detection result of the phase difference detection means. 7. A decoder means for decoding the carrier color signal in the input video signal to convert it into a color difference signal, supplying the color difference signal to the adding means, and remodulating the color difference signal from the adding means. 2. The noise reduction device according to claim 1, further comprising an encoder means and a clock generating means for generating a clock which is an integral multiple of the color subcarrier and supplying the clock to the decoder means and the encoder means. 8. A decoder means for decoding a carrier color signal in the input video signal to convert it into a color difference signal and supplying the color difference signal to the adding means and the variable delay means, and a color difference signal from the adding means. 3. The noise according to claim 2, further comprising: encoder means for re-modulating the signal, and clock generating means for generating a clock that is an integral multiple of the color sub-carrier wave and supplying the clock to the decoder means and the encoder means. Reduction device. 9. Decoder means for decoding the carrier color signal in the input video signal to convert it into a color difference signal, and supplying this color difference signal to the delay means and the first subtraction means, and the first subtraction. 4. An encoder means for remodulating a color difference signal from the means, and a clock generating means for generating a clock which is an integral multiple of a color subcarrier and supplying the clock to the decoder means and the encoder means. The described noise reduction device. 10. A noise reduction device for performing signal processing in a basic cycle of a video signal, a detection means for detecting a time base fluctuation of an input video signal, a variable delay means for controlling a delay time by the detection output, An addition means for generating an output video signal by adding an input video signal and an output of the variable delay means, wherein the variable delay means has the same time axis fluctuation as the time axis fluctuation of the input video signal. Noise reduction device characterized by controlling.