JPH0870463A - Circuit for processing video signal - Google Patents

Abstract

PURPOSE: To embody the function of burst-lock/line-lock conversion and horizontal compression/extension by using a circuit and a memory device in common by using TBC(time base collector) used in a video set at present in a television receiver. CONSTITUTION: A luminance signal and a color difference signal are respectively inputted by a clock synchronized with a burst signal and written in memory devices 32 and 36 and reading from the memory devices 43 is executed by the stable clock generated in a digital PLL circuit 38 where line-lock is executed. Then, a skew is corrected by skew filters 13 and 17 through the use of the phase difference data(skew data) of the horizontal synchronizing signal with the burst-lock clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time base collector (hereinafter referred to as TBC) processing for correcting fluctuation of a video signal, a clock conversion processing from burst lock to line lock (hereinafter referred to as clock conversion), and horizontal compression. It is about processing.

[0002]

2. Description of the Related Art A conventional example is shown in FIG. 21 (ITEJ Technical Report Vol.
3, No. 38, PP17-22).

In FIG. 17, 97 is a color signal input terminal,
Reference numeral 98 is a luminance signal input terminal, 99 is a color demodulation circuit, 100 is a color difference signal multiplexing circuit, 101 is an A / D converter, 102 is a line memory, 103 is a D / A converter, 104 is a color modulation circuit, and 105 is A. / D converter, 106 is a line memory, 107 is a D / A converter, 108 is a synchronous switching circuit, 109 is an adaptive sync separation circuit, 110 is a feed-forward clock generation circuit, 111 is a memory control circuit, and 112 is a synchronization signal. Generation circuit, 113 is oscillator, 11
Reference numeral 4 is an LPF, 115 is a phase comparison circuit, and 116 is a luminance signal output terminal.

Next, the operation of FIG. 21 will be described. In FIG. 21, the luminance and color signals inputted from the luminance signal input terminal 98 and the color signal input terminal 97 are A / D of 105 and 101, respectively.
The signals are A / D converted by the conversion circuit and input to the line memories 106 and 102, respectively.

The write clock and the read clock are 109
This is performed by each clock created by comparing the phase with the horizontal synchronization signal separated by the adaptive synchronization separation circuit of.

The signal output from the memory is 111,1
It is converted into an analog signal by the D / A converter 13 and output.

[0007]

However, since the above-mentioned structure is mainly developed for video, it is wasteful and costly to use the circuit and RAM shown in FIG. 17 only for the TBC function.

In view of the above problems, the present invention provides a circuit of TBC most suitable to be built in a television receiver this time,
Also, the circuit will be shared with other functions.

[0009]

In order to solve the above problems, a video signal processing circuit of the present invention includes a luminance signal input terminal sampled at a clock synchronized with a color burst signal and a sampling at a clock synchronized with a color burst signal. A color difference signal input terminal, a compression rate data input terminal for inputting a compression rate of horizontal compression, and a skew data input terminal for inputting skew data which is a phase error of a clock synchronized with a horizontal synchronization signal and a color burst signal, An H pulse input terminal latched with a clock synchronized with the color burst signal, a burst lock clock input terminal,
A PLL hold signal input terminal that holds the PLL for a certain period, a clock unit skew filter circuit that corrects a phase error greater than a clock in a color difference signal input from the color difference signal input terminal, and a compression input from the compression rate input terminal. A write control signal synchronized with a color burst signal for a luminance memory device and a color difference memory device, which will be described later, and a read control signal synchronized with a clock generated by the PLL circuit, according to the rate data; A control circuit that creates interpolation data for a horizontal interpolation circuit that performs horizontal compression, and a signal that is input from a luminance signal input terminal that is sampled with a clock that is synchronized with the color burst signal is written with the clock that is synchronized with the color burst signal. With the H pulse reproduced by the circuit, the data of the address (n) and the address ( The memory device for luminance which reads out two data of +1) and the signal output from the clock unit skew filter circuit are written by the clock synchronized with the color burst signal, and the address (n ) Data and address (n +
2) a color difference memory device for reading out two data, and a luminance horizontal interpolation circuit for performing horizontal compression processing by interpolating two output signals of the luminance memory device with the interpolation data generated by the control circuit. A horizontal interpolation circuit for color difference that interpolates two output signals of the memory device for color difference with interpolation data generated in the control circuit and performs horizontal compression processing; and skew data input from the skew data input terminal, The skew filter circuit that corrects the spatial position of the luminance signal output from the luminance horizontal interpolation circuit and the skew data input from the skew data input terminal, and the space of the color difference signal output from the color difference horizontal interpolation circuit. Of the skew filter circuit that corrects the target position and the phase of the H pulse input from the H pulse input terminal Tsu play the click and the line locked H pulse can hold PLL in PLL hold signal input from the PLL hold signal input terminal PL
An L circuit, an output terminal for outputting the output signal of the horizontal interpolation circuit for the luminance, and an output terminal for outputting an output signal of the horizontal interpolation circuit for the color difference are provided to realize TBC, clock conversion, and horizontal compression / expansion. It was done.

[0010]

According to the present invention, the TBC function is realized by making the LPF of the line-locked PLL circuit heavy by the above-mentioned configuration, and the writing of the memory device is performed by the burst-locked clock, and the reading is reproduced by the PLL circuit. The TBC and the clock conversion can be realized by the skew filter using the skew data which is the phase error between the horizontal sync signal and the burst lock clock. Further, the horizontal compression / expansion is performed by the horizontal interpolation circuit using the control signal of the memory device and the interpolation data according to the compression rate data generated by the control circuit of the memory device.

[0011]

【Example】

(Embodiment 1) A video signal processing circuit according to Embodiment 1 of the present invention will be described below with reference to FIG.

1 is a composite video input terminal, 2 is A
/ D conversion, Y / C separation, color demodulation, synchronous separation, burst lock clock generation First signal processing circuit that operates with clock synchronized with color burst signal, 3 is line lock clock generation, burst lock to line lock Second signal processing circuit that performs clock conversion to / time base collector, 4 scan line interpolation processing, vertical expansion processing, D /
A third signal processing circuit operating with a clock synchronized with a horizontal synchronizing signal for A conversion, 5 is a luminance signal output terminal output from the third signal processing circuit, and 6 is output from the third signal processing circuit. A color difference signal output terminal, and 7 is a synchronizing signal output terminal.

Next, the operation will be described with reference to FIG.
In FIG. 1, the first signal processing circuit 2 is based on the composite video signal input from the composite video input terminal 1.
, Clock generation synchronized with color burst signal, sync separation, A / D conversion with burst lock clock, Y / C
Color signal processing such as separation and color demodulation is performed by the burst lock clock. The luminance signal, the color difference signal, and the synchronization signal output from the first signal processing circuit 2 are transferred to the second signal processing circuit 3
The line lock clock generation, the burst lock to line lock clock conversion, and the time base collector are performed at the same time, and the third signal processing circuit 4 operates in the vertical direction such as scanning line interpolation processing, vertical expansion processing, and D / A. The conversion process and the like are performed by the line lock clock.

By taking such a structure, Y /
By performing processing with a burst lock clock that is easy to perform color signal processing such as C separation and color demodulation processing, and with line lock that is easy to perform processing such as scanning line interpolation processing and vertical expansion processing, signal processing is simplified. Further, by processing with a clock system that is easy to process, it is possible to obtain a higher quality image than signal processing with only burst lock or line lock. Also, by performing the time base corrector at the same time as the clock conversion, the synchronization performance at the time of VCR reproduction is dramatically improved.

(Embodiment 2) 9 is a luminance signal input terminal sampled with a clock synchronized with a color burst signal, 10 is a color difference signal input terminal sampled with a clock synchronized with a color burst signal, and 8 is a horizontal synchronization signal. A skew data input terminal for inputting skew data which is a phase error of a clock synchronized with the color burst signal, 11 is an H pulse input terminal latched with a clock synchronized with the color burst signal, and 16 is the H pulse HB
The PLL circuit which outputs the H pulse HL line-locked with the line-locked clock by comparing the phase with the Write with H pulse HB
A memory device for luminance which is read out by the H pulse HL reproduced by the LL circuit, and 15 is an H pulse HB in which the signal input from the color difference signal input terminal sampled by the clock synchronized with the color burst signal is latched by the burst lock clock And a memory device for color difference that is read by the H pulse HL reproduced by the PLL circuit, and 13 is spatial data of the brightness signal output from the memory device for brightness by the skew data input from the skew data input terminal. A skew filter circuit for correcting the position, 17 is a skew filter circuit for correcting the spatial position of the color difference signal output from the memory device for the color difference with the skew data input from the skew data input terminal, 14
Is a control circuit for generating a write control signal synchronized with a color burst signal for controlling the memory device for luminance and a memory device for color difference, and a read control signal synchronized with a clock generated in the PLL circuit. Is an output terminal for outputting the output signal of the luminance skew filter circuit, and 19 is an output terminal for outputting the output signal of the color difference skew filter circuit.

The operation of this embodiment will be described with reference to FIGS. 2, 3 and 4. As shown in FIG. 3A, the H pulse HB latched by the burst lock clock is (T + Δt1), (T−Δt2), (T
+ Δt3), the luminance memory device 12 and the color difference memory device 15 shown in FIG.
Input as shown in. The H pulse HL reproduced by the PLL circuit 16 shown in FIG. 2 is stably reproduced at the cycle T of the horizontal synchronizing signal with a half cycle difference from the H pulse HB latched by the burst lock clock as shown in FIG. 3C. It Then, as shown in FIG. 3D, this reproduced H pulse H
When data is read from memory by L, T
BC is realized.

Next, the operation of the skew filter will be described with reference to FIG. In FIG. 4, FIG. 4A shows a horizontal synchronizing signal of the video signal, and a phase error between this horizontal synchronizing signal and the burst lock clock (FIG. 4B) is obtained, and as shown in FIG. Use as skew data. At this time, if the clock is divided into 32, the skew data SK becomes 4/32. Since the H pulse HB is latched by the burst lock clock, it becomes as shown in FIG. 4D, and the spatial position is shifted by (1-SK) from the actual horizontal synchronizing signal (FIG. 4A). ing. Further, since writing to the memory device is performed by the burst lock clock, it is input as shown in FIG.

Next, the H pulse HL reproduced based on the H pulse HB latched by the burst lock clock in the PLL circuit 16 of FIG. 2 is as shown in FIG.
The line lock clock reproduced by the PLL circuit 16 is synchronized with FIG. Output data from the memory device at this time is shown in FIG. Since the H pulse HL which is the reference signal for reading the memory device is reproduced with the H pulse HB latched by the burst lock clock as the reference, the spatial position is (1-SK) apart from the actual synchronization signal. Deviated. Therefore, the skew filter uses the skew data to interpolate the output signal from the memory device to correct the spatial position of (1-SK) (FIG. 4 (i)).

The effect of the TBC thus realized will be described with reference to FIG. When a signal such as a VCR is reproduced, the synchronization is disturbed as shown in FIG. 5A, and top curl jitter occurs. According to the TBC circuit of this embodiment, FIG.
It is possible to reproduce a high-quality image in which synchronization is not disturbed as in (b).

(Embodiment 3) Reference numeral 20 is a reference H pulse input terminal for phase comparison, 21 is a PLL hold signal input terminal for holding the PLL for a certain period, 25 is an oscillator for oscillating a clock, and 26 is the oscillator. Frequency divider circuit that divides the generated clock to reproduce H pulse and phase data, 2
Reference numeral 2 denotes a phase comparison circuit that compares the phase data generated by the frequency divider circuit with the reference H pulse input from the reference H pulse input terminal, and 23 determines the response of the PLL circuit, which is input from the PLL hold signal input terminal. LPF for holding data with a signal to be generated, 24 a D / A converter for converting the output of the LPF to analog, 27 a reproduction H pulse output terminal for outputting a reproduction H pulse reproduced by the frequency dividing circuit, 28 Is a line lock clock output terminal for outputting a line lock clock.

Next, the operation of the third embodiment will be described with reference to FIG. In the NTSC video signal shown in FIG. 7A, the horizontal synchronizing signal is disturbed in the equivalent pulse section of the vertical synchronizing period, and a stable clock cannot be reproduced. Therefore, a PLL hold signal as shown in FIG. 7B is input during the vertical synchronization period,
The data of the LPF 23 of FIG. 6 is held (FIG.
By (c)), disturbance of synchronization is prevented.

Conventionally, when vertical enlargement is performed as shown in FIG. 8 (a), the image portion is subjected to the above vertical synchronization period.
There is a problem that the synchronization is disturbed as in (b). However, according to this embodiment, as shown in FIG. 8C, high-quality video can be reproduced without disturbing the synchronization even during the vertical synchronization period.

(Embodiment 4) 9 is a luminance signal input terminal sampled by a clock synchronized with a color burst signal, 10 is a color difference signal input terminal sampled by a clock synchronized with a color burst signal, and 29 is a horizontal compression compression. A compression rate data input terminal for inputting a rate, 8 is a skew data input terminal for inputting skew data which is a phase error of a clock synchronized with a horizontal synchronization signal and a color burst signal, and 11 is latched with a clock synchronized with a color burst signal. H pulse input terminal, 30 is a burst lock clock input terminal, 31 is a PLL hold signal input terminal that holds the PLL for a certain period, and 35 is a phase difference of a clock or more in the color difference signal input from the color difference signal input terminal. Clock unit skew filter circuit, 3
Reference numeral 4 denotes a write control signal synchronized with a color burst signal for controlling a memory device for luminance described later and a memory device for color difference described later according to the compression ratio data input from the compression ratio input terminal, and the PLL. A read control signal synchronized with the clock generated by the circuit and a control circuit for generating interpolation data of a horizontal interpolation circuit for horizontal compression, 32 is a signal input from a luminance signal input terminal sampled with a clock synchronized with the color burst signal Is written with the H pulse HB latched by the burst lock clock, and the address (n) is written with the H pulse HL reproduced by the PLL circuit.
And a memory device for luminance that reads out two data of address (n + 1), 36 is a signal input from a color difference signal input terminal sampled by a clock synchronized with a color burst signal and latched by a burst lock clock A memory device for color difference that writes in H pulse HB and reads out two data of address (n) and address (n + 2) by H pulse HL reproduced by the PLL circuit. 33 is a memory device for luminance. A horizontal interpolation circuit for luminance that interpolates two output signals with the interpolation data generated by the control circuit to perform horizontal compression processing, and 37 interpolates two output signals of the memory device for color difference with the interpolation data generated by the control circuit. A horizontal interpolation circuit for color difference for performing horizontal compression processing, and 13 is a skew data input from the skew data input terminal. Is a skew filter circuit for correcting the spatial position of the luminance signal output from the horizontal interpolation circuit for luminance, and 17 is skew data input from the skew data input terminal, which is output from the horizontal interpolation circuit for color difference. A skew filter circuit for correcting the spatial position of the color difference signal, 38 compares the phase with the H pulse HB input from the H pulse input terminal to reproduce the line locked clock and the line locked H pulse HL, and the P pulse
A digital PLL circuit that can hold the PLL with a PLL hold signal input from the LL hold signal input terminal, 18 is an output terminal that outputs the output signal of the horizontal interpolation circuit of the luminance, and 19 is an output signal of the horizontal interpolation circuit of the color difference. It is an output terminal for outputting.

Next, the operation of this embodiment will be described with reference to FIGS. 10, 11 and 12. FIG. 10 shows the operation of the clock unit skew filter circuit. 10B shows the basic clock, and FIG. 10C shows the color difference signal input from the color difference signal input terminal. Here, the relationship between the color discrimination clock shown in FIG. 10D and the H pulse HB latched by the burst lock clock is one of the relationships shown in FIGS. H latched by burst lock clock for each line
The relationship between the pulse HB and the color determination clock is determined and the color difference signal is interpolated in FIG.

Next, the operation of the horizontal interpolation circuit will be described with reference to FIG. FIG. 11A shows the H pulse HB latched by the burst lock clock, and data is input to the memory device at the address shown in FIG. 11C as shown in FIG. 11B in synchronization with this signal. Here, if the compression rate is 3/4, the compression rate data input from the compression rate input terminal of FIG. 9 becomes 2/3 (FIG. 11 (d)). Digital PL of FIG.
The H pulse HL reproduced by the L circuit 38 (FIG. 11 (e))
The control circuit 34 of FIG. 8 outputs a control signal corresponding to the interpolation data of FIG. 11 (f) and the address shown in FIG. 11 (g) on the basis of FIG. Data from the output (n + 1) of the memory device from FIG.
Output the data of (i). In the horizontal interpolation circuit 33 shown in FIG. 9, the interpolation data shown in FIG. 11 (f) and the outputs from the memory device shown in FIGS. 11 (h) and 11 (i) to 11 (j).
The interpolated data shown in (1) is created and horizontal compression processing is performed.

FIG. 12 shows an example of horizontal compression. 12
(A) is the case where horizontal compression is not performed and the compression rate data is 1/2
Is. FIG. 12B shows a case where 3/4 horizontal compression is performed, and the compression rate data is 2/3. In FIG. 13C, nonlinear compression is possible by changing the compression rate data according to the horizontal position.

As described above, the horizontal compression function can be realized without increasing the cost by sharing the clock conversion, the TBC line memory, and the horizontal compression line memory.

(Embodiment 5) 9 is a luminance signal input terminal sampled by a clock synchronized with a color burst signal, 10 is a color difference signal input terminal sampled by a clock synchronized with a color burst signal signal, and 29 is a horizontal compression. A compression rate data input terminal for inputting a compression rate, 8 is a skew data input terminal for inputting skew data which is a phase error between clocks synchronized with the horizontal synchronization signal and the color burst signal, and 11 is a latch synchronized with the color burst signal H pulse input terminal, 30 is a burst lock clock input terminal, 31 is a PLL hold signal input terminal that holds the PLL for a certain period, and 35 is a phase error that is greater than or equal to the clock in the color difference signal input from the color difference signal input terminal. Clock unit skew filter circuit for controlling, 39 is the compression ratio The color burst signal for controlling the luminance memory device described later and the color difference memory device described later according to the compression ratio data input from the input terminal and the skew data input from the skew data input terminal. A synchronized write control signal, a read control signal synchronized with the clock generated in the PLL circuit,
A control circuit that creates interpolation data for a horizontal interpolation circuit that performs horizontal compression, 32 is an H pulse HB latched by a burst lock clock for a signal input from a luminance signal input terminal sampled by a clock synchronized with a color burst signal. H pulse H written and reproduced by the above PLL circuit
L at address (n) data and address (n + 1) 2
A memory device for luminance that reads out one data, 36 writes a signal input from a color difference signal input terminal sampled with a clock synchronized with a color burst signal with an H pulse HB latched with a burst lock clock,
A memory device for color difference that reads out two data at address (n) and two data at address (n + 2) by H pulse HL reproduced by the PLL circuit, and 33 controls the two output signals of the memory device for luminance. A luminance horizontal interpolation circuit for performing horizontal compression processing by interpolating with the interpolation data generated by the circuit, 37 is a horizontal compression processing and skew by interpolating two output signals of the memory device for the color difference with the interpolation data generated by the control circuit. A color difference horizontal interpolation circuit for correction, 38
Can reproduce the H pulse HL line-locked with the line lock clock by comparing the phase with the H pulse HB input from the H pulse input terminal, and hold the PLL with the PLL hold signal input from the PLL hold signal input terminal. A digital PLL circuit, 18 is an output terminal for outputting an output signal of the luminance horizontal interpolation circuit, and 19 is an output terminal for outputting an output signal of the color difference horizontal interpolation circuit.

FIG. 14 shows an operation diagram of the fifth embodiment. FIG. 14A shows the H pulse HB latched by the burst lock clock and the H pulse HB synchronized with this signal.
Data is input to the address shown in FIG. 14C as shown in FIG. Here, if the compression rate is 3/4, the compression rate data input from the compression rate input terminal of FIG. 9 becomes 2/3 (FIG. 14 (d)). In addition, here, the skew data input terminal 8
The skew data input from is set to 1/6 as shown in FIG. 14 based on the H pulse HL (FIG. 14 (f)) reproduced by the digital PLL circuit 38 of FIG.
The compression ratio data of (d), the skew data of FIG. 14 (e), the control circuit 34 of FIG. 13 outputs the interpolation data of FIG. 14 (g) and a control signal corresponding to the address shown in FIG. 14 (h). The control signal from the control circuit 34 of FIG. 13 outputs the data of FIG. 14 (i) from the output (n) of the memory device and the data of FIG. 14 (j) from the output (n + 1) of the memory device. . The horizontal interpolation circuit 33 in FIG. 13 creates the interpolated data shown in FIG. 14 (k) and performs horizontal compression processing.

By inputting the skew data to the control circuit and outputting the control signal of the memory device and the interpolation data according to the skew data as in the present embodiment, the horizontal interpolation circuit and the skew filter can be shared. The circuit is small and TBC, clock conversion, and horizontal compression can be realized.

(Embodiment 6) 40 is a video signal input terminal, 4
Reference numeral 1 is a skew data input terminal for inputting skew data which is a phase error of a clock synchronized with a horizontal synchronizing signal and a color burst signal, and 42 is a space for correcting a spatial position according to the skew data input from the skew data input terminal. An alignment filter circuit, 43 is a decoder for creating a gain of a multiplier described later according to the skew data input from the skew data input terminal, 44 is a BPF for extracting only a certain frequency component of the output of the spatial alignment filter circuit, Reference numeral 45 is a multiplier for multiplying the output signal of the BPF by the output signal of the decoder, 46 is an adder for adding the output of the multiplier and the output of the spatial alignment filter circuit, and 47 is a video signal output terminal.

The skew filter circuit of this embodiment is shown in FIG.
This will be described using 5. In FIG. 15, a video signal is input from the video signal input terminal 41. The spatial position of the input video signal is corrected by the skew data input from the skew data input terminal 40 by the spatial alignment filter circuit. As shown in FIG. 16A, the corrected data has different frequency characteristics according to each skew data. Therefore, the BPF 44, the multiplier 45 and the adder 46 form a peaking circuit. In this peaking circuit, the skew data is decoded by the decoder 43, and changes according to the skew data.

The output signal of the skew filter circuit according to the present embodiment is as shown in FIG.
The frequency characteristic is improved as compared with the frequency characteristic of (a), and the horizontal noise in the horizontal high frequency region can be reduced.

[0034]

In the video signal processing circuit according to the first aspect of the present invention, processing is performed with a burst lock clock that facilitates color signal processing such as Y / C separation and color demodulation processing, and scanning line interpolation processing and vertical expansion processing are performed. By performing the line lock that is easy to process, the signal processing becomes simple, and by processing with the clock system that is easy to process, it is possible to obtain a higher quality image than signal processing only with burst lock or line lock. You can Also, by performing the time base corrector at the same time as the clock conversion, the synchronization performance at the time of VCR reproduction is dramatically improved.

In the video signal processing circuit of the second invention,
When a signal such as a VCR is reproduced, synchronization is disturbed and top curl or jitter occurs. According to the TBC circuit of the present embodiment, it is possible to reproduce a high quality image in which synchronization is not disturbed.

In the digital PLL circuit of the third invention, there is a problem that when the vertical expansion is performed, the video portion is subjected to the vertical synchronization period and the synchronization is disturbed. But,
According to the present invention, high-quality images can be reproduced without disturbing synchronization even during the vertical synchronization period.

In the video signal processing circuit of the fourth invention,
The horizontal compression function can be realized without increasing the cost by sharing the clock conversion and TBC line memory with the horizontal compression line memory.

In the video signal processing circuit of the fifth invention,
By inputting the skew data to the control circuit and outputting the memory control signal and the interpolation data according to the skew data, the horizontal interpolation circuit and the skew filter can be shared, and the circuit is smaller than the fourth invention and the TBC / clock conversion is performed.・ Horizontal compression can be realized.

In the video signal processing circuit of the sixth invention,
The frequency characteristic of the output signal of the skew filter circuit is improved as compared with the conventional frequency characteristic, and the horizontal noise in the horizontal high frequency region can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a block diagram of a second embodiment.

[Fig. 3] Operation diagram of TBC

FIG. 4 is an operation diagram of the skew filter circuit.

FIG. 5 is a diagram showing the effect of TBC.

FIG. 6 is a block diagram of a third embodiment.

FIG. 7 is a vertical synchronization period mask timing chart.

FIG. 8 is a diagram showing a masking effect during a vertical synchronization period.

FIG. 9 is a block diagram of a fourth embodiment.

FIG. 10 is an operation diagram of a clock unit skew filter circuit.

FIG. 11: Horizontal interpolation circuit operation diagram

FIG. 12 is a diagram showing an example of horizontal compression display.

FIG. 13 is a block diagram of a fifth embodiment.

FIG. 14 is an operation diagram of the fifth embodiment.

FIG. 15 is a block diagram of a sixth embodiment.

FIG. 16: Frequency characteristics of skew filter circuit

FIG. 17 is a block diagram showing an example of a conventional TBC.

[Explanation of symbols]

 1 Composite video signal input terminal 2, 3, 4 Signal processing circuit 5, 18 Luminance signal output terminal 6, 19 Color difference signal output terminal 7 Sync signal output terminal 8, 40 Skew data input terminal 9 Luminance signal input terminal 10 Color difference signal input terminal 11 H pulse input terminal 12, 15, 32, 36 Memory device 13, 17 Skew filter circuit 14, 34, 39 Control circuit 16, 38 Digital PLL circuit 20 Reference H pulse input terminal 21, 31 PLL hold signal input terminal 22 Phase comparison Circuit 23 LPF 24 D / A converter 25 Oscillator 26 Frequency divider circuit 27 Reproduction H pulse output terminal 28 Line lock clock output terminal 29 Compression rate data input terminal 30 Burst lock clock input terminal 33, 37 Horizontal interpolation circuit 35 Clock unit skew filter Circuit 41 Image signal input terminal 42 Spatial alignment filter circuit 43 Decoder 44 BPF 45 Multiplier 46 Adder 47 Video signal output terminal 97 Color signal input terminal 98 Brightness signal input terminal 99 Color demodulation circuit 100 Color difference signal multiplexing circuit 101, 105 A / D Converter 102,106 Line memory 103,107 D / A converter 104 Color modulation circuit 108 Synchronous replacement circuit 109 Adaptive sync separation circuit 110 Feedforward clock generation circuit 111 Memory control circuit 112 Synchronous signal generation circuit 113 Oscillator 114 LPF 115 Phase Comparison circuit 116 Luminance signal output terminal 117 Color difference signal output terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Yamaguchi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (7)

[Claims] 1. A composite video input terminal and an A / D
Conversion, Y / C separation, color demodulation, synchronous separation, burst lock clock generation First signal processing circuit that operates with a clock synchronized with a color burst signal, and line lock clock generation / burst lock to line lock clock conversion A second signal processing circuit that performs a time base collector, a third signal processing circuit that operates with a clock synchronized with a horizontal synchronizing signal that performs scanning line interpolation processing, vertical expansion processing, and D / A conversion, and the third signal processing circuit described above. The luminance signal output terminal output from the signal processing circuit of No. 3, the color difference signal output terminal output from the third signal processing circuit, and the synchronization signal output terminal are provided, and colors such as Y / C separation and color demodulation are provided. The signal processing is operated by the clock that is synchronized with the color burst signal, and the second signal processing circuit performs the clock conversion and the time base collector at the same time. Calculated video signal processing circuit, characterized in that the clock signal is generated by the horizontal synchronizing signal synchronization. 2. The video signal processing circuit according to claim 1, wherein horizontal arbitrary compression processing is simultaneously performed by the second signal processing circuit. 3. A luminance signal input terminal sampled by a clock synchronized with a color burst signal, a color difference signal input terminal sampled by a clock synchronized with a color burst signal, and a clock synchronized with a horizontal synchronization signal and a color burst signal. Skew data input terminal for inputting skew data which is the phase error of H, H pulse input terminal latched by the clock synchronized with the color burst signal, and H pulse line locked with the line lock clock by comparing the phase with the above H pulse. A PLL circuit that outputs
A luminance memory device for writing a signal input from a luminance signal input terminal sampled with a clock synchronized with a color burst signal with an H pulse latched with a burst lock clock and reading with an H pulse reproduced by the PLL circuit, A memory device for color difference in which a signal input from a color difference signal input terminal sampled with a clock synchronized with a color burst signal is written by an H pulse latched by a burst lock clock and read by an H pulse reproduced by the PLL circuit. A skew filter circuit that corrects the spatial position of the luminance signal output from the memory device for luminance with the skew data input from the skew data input terminal, and the color difference using the skew data input from the skew data input terminal. Output from the memory device for The skew filter circuit for correcting the spatial position of the color difference signal, the write control signal synchronized with the color burst signal for controlling the luminance memory device and the color difference memory device, and the clock generated by the PLL circuit are used. A control circuit for generating a synchronized read control signal, an output terminal for outputting an output signal of the luminance skew filter circuit, and an output terminal for outputting an output signal of the color difference skew filter circuit. And a video signal processing circuit that performs clock conversion from burst lock to line lock with a time base collector (TBC). 4. A reference H pulse input terminal for phase comparison, a PLL hold signal input terminal for holding a PLL for a certain period, an oscillator for oscillating a clock, and an H pulse for dividing the clock oscillated by the oscillator. And a frequency dividing circuit for reproducing phase data, and phase H generated by the frequency dividing circuit, which is a reference H pulse input from the reference H pulse input terminal.
A phase comparison circuit for phase comparison with pulses, an LPF for deciding the response of the PLL circuit and holding data with a signal input from the PLL hold signal input terminal, and a D / A converter for converting the output of the LPF to analog. And a reproduction H pulse output terminal for outputting a reproduction H pulse reproduced by the frequency dividing circuit, and a line lock clock output terminal for outputting a line lock clock.
A video signal processing circuit, which holds LPF data with an L hold signal and prevents the PLL from being disturbed in an equivalent pulse section of a vertical synchronizing signal portion. 5. A luminance signal input terminal sampled by a clock synchronized with a color burst signal, a color difference signal input terminal sampled by a clock synchronized with a color burst signal, and compression rate data for inputting a compression rate for horizontal compression. Input terminal, horizontal sync signal and color burst signal, synchronous output terminal Skew data input terminal for inputting skew data which is phase error of clock, H pulse input terminal latched by clock synchronized with color burst signal, burst A lock clock input terminal, a PLL hold signal input terminal that holds the PLL for a certain period, a clock unit skew filter circuit that corrects a phase error of a color difference signal input from the color difference signal input terminal that is greater than a clock, and the compression ratio input. Depending on the compression rate data input from the terminal, Horizontal compression is performed with a write control signal synchronized with a color burst signal for controlling the memory device for luminance described above and a memory device for color difference described later, a read control signal synchronized with a clock generated in the PLL circuit. The control circuit for creating the interpolation data of the horizontal interpolation circuit and the signal inputted from the luminance signal input terminal sampled by the clock synchronized with the color burst signal are written by the H pulse latched by the burst lock clock, and the PLL circuit is used. A memory device for luminance that reads out the data of address (n) and two data of address (n + 1) by the reproduced H pulse, and the signal input from the color difference signal input terminal sampled by the clock synchronized with the color burst signal. Is written by the H pulse latched by the burst lock clock, and the PLL Data and address of the address (n) in the H pulse reproduced by road (n
+2) a color difference memory device for reading out two data, and a luminance horizontal interpolation circuit for performing horizontal compression processing by interpolating two output signals of the luminance memory device with the interpolation data generated by the control circuit. A horizontal interpolation circuit for color difference that interpolates two output signals of the memory device for color difference with interpolation data generated in the control circuit and performs horizontal compression processing; and skew data input from the skew data input terminal, The skew filter circuit that corrects the spatial position of the luminance signal output from the luminance horizontal interpolation circuit and the skew data input from the skew data input terminal, and the space of the color difference signal output from the color difference horizontal interpolation circuit. Line lock by comparing the phase of the H pulse input from the H pulse input terminal with the skew filter circuit that corrects the dynamic position A digital PLL circuit capable of reproducing the locked and line-locked H pulse and holding the PLL with a PLL hold signal input from the PLL hold signal input terminal; and an output terminal for outputting an output signal of the horizontal interpolation circuit of the luminance. An output terminal for outputting the output signal of the color difference horizontal interpolation circuit is provided, and the memory device for brightness and the memory device for color difference used for the clock conversion from burst lock to line lock and the time base collector are A video signal processing circuit, which is also used as a memory device for arbitrary horizontal compression of each color difference. 6. A luminance signal input terminal sampled by a clock synchronized with a color burst signal, a color difference signal input terminal sampled by a clock synchronized with a color burst signal, and compression rate data for inputting a compression rate for horizontal compression. An input terminal, a skew data input terminal for inputting skew data that is a phase error between clocks synchronized with the horizontal synchronization signal and the color burst signal, an H pulse input terminal latched with a clock synchronized with the color burst signal, and a burst lock A clock input terminal, a PLL hold signal input terminal that holds the PLL for a certain period, a clock unit skew filter circuit that corrects a phase error of a color difference signal input from the color difference signal input terminal that is greater than or equal to a clock, and the compression ratio input terminal. The compression rate data input from A write control signal synchronized with a color burst signal signal for controlling a luminance memory device described later and a color difference memory device described later according to skew data input from a data input terminal, and the PLL.
Read control signal synchronized with the clock generated by the circuit, control circuit that creates the interpolation data of the horizontal interpolation circuit that performs horizontal compression, and the signal input from the luminance signal input terminal sampled with the clock that is synchronized with the color burst signal Is latched by the burst lock clock and written by H pulse, and the H pulse reproduced by the PLL circuit reads out the data at address (n) and the two data at address (n + 1), and the color burst signal. The signal inputted from the color difference signal input terminal sampled by the clock synchronized with the clock is written by the H pulse latched by the burst lock clock, and the data of the address (n) and the address (n + 2) are written by the H pulse reproduced by the PLL circuit. Memory device for color difference that reads two data of A horizontal interpolation circuit for luminance that interpolates two output signals of the memory device with the interpolation data generated by the control circuit and performs horizontal compression processing, and an interpolation generated by the control circuit for two output signals of the memory device for color difference. A color difference horizontal interpolation circuit that interpolates with data to perform horizontal compression processing and skew correction, and compares the phase of the H pulse input from the H pulse input terminal to reproduce the line-locked clock and the line-locked H pulse, and reproduces the PLL. A digital PLL circuit that can hold the PLL with a PLL hold signal input from the hold signal input terminal, an output terminal that outputs the output signal of the horizontal interpolation circuit of the luminance, and an output that outputs the output signal of the horizontal interpolation circuit of the color difference. And a terminal for inputting skew data to the control circuit, and the control circuit responds to the skew data of the memory device. Video signal processing circuit and performing skew correction even horizontal interpolation circuit by outputting the interpolated data of the control signal and the horizontal interpolation circuit. 7. A video signal input terminal, and a skew data input terminal for inputting skew data which is a phase error of a clock synchronized with a horizontal synchronizing signal and a color burst signal,
A spatial alignment filter circuit that corrects the spatial position according to the skew data input from the skew data input terminal, and a decoder that creates a gain of a multiplier described later according to the skew data input from the skew data input terminal. A BPF for extracting only a certain frequency component of the output of the spatial alignment filter circuit;
It has a multiplier for multiplying the output of the PF and the output signal of the decoder, an adder for adding the output of the multiplier and the output of the spatial alignment filter circuit, and a video signal output terminal, which varies from line to line. A video signal processing circuit, characterized in that a spatial alignment filter circuit that is calculated according to skew data corrects frequency characteristics that vary from line to line by changing the peaking amount according to skew data.