JP4423980B2 - Video signal processing circuit - Google Patents

Description

  The present invention includes horizontal jitter correction from burst lock processing necessary for decoding a composite video signal into a Y signal, an RY signal, and a BY signal in a matrix drive type display device such as a liquid crystal panel. The present invention relates to a video signal processing circuit that realizes the line lock process and the drive process only with a clock frequency corresponding to a panel drive condition.

Conventionally, when a composite video signal is YC separated and a C signal is decoded into an RY signal and a BY signal, a system using both a burst lock clock synchronized with a burst signal and a line lock clock synchronized with a horizontal synchronization signal has been used. It has been devised. (For example, video signal processing circuit disclosed in Japanese Patent Laid-Open No. 10-164618)
The burst lock clock at this time is often set to 4 times the color subcarrier frequency (fsc) (4 fsc≈14.3 MHz, hereinafter referred to as 4 fsc) or 8 times (8 fsc≈28.6 MHz, hereinafter referred to as 8 fsc). . Further, in order not to generate a beat to the video signal due to the mixture of the burst lock clock and the line lock clock, Japanese Patent Laid-Open No. 2001-112016 “Video signal processing” is disclosed as a method for operating the burst lock processing and the line lock processing with a single clock. An apparatus "is disclosed.

  FIG. 14 is a diagram showing a configuration of a video signal processing apparatus described in Patent Document 1 below. The operation will be described below. The A / D conversion circuit 152 samples the NTSC composite video signal input from the input terminal 151 in synchronization with the 27 MHz clock generated from the free-run clock generation circuit 155. The burst lock interpolation circuit 153 converts the data sampled at 27 MHz into 4 fsc sampling data using a digital interpolation filter. At this time, the data interpolation position is controlled according to the burst phase error fed back from the burst phase detection circuit 154.

  The burst phase detection circuit 154 extracts the burst signal portion from the output data of the burst lock interpolation circuit and determines how much the sampling point is deviated from the 0 °, 90 °, 180 °, and 270 ° points of the burst signal. Detect and output as burst phase error. The burst lock interpolation circuit 153 adjusts the generation position of the interpolation data so that the burst phase error becomes zero. In this way, the data of the free-run 27 MHz sampling is converted into the data of the burst lock 4fsc sampling by the loop of the burst lock interpolation circuit 153 and the burst phase detection circuit 154.

The signal output from the burst lock interpolation circuit 153 is separated into a Y signal and a C signal by a YC separation circuit 156, and the C signal is decoded into an RY signal and a BY signal by a chroma decoding circuit 157. The line lock interpolation circuit 158 converts the Y signal, RY signal, and BY signal of burst lock 4fsc sampling into a Y signal, RY signal, and BY signal of line lock 13.5 MHz sampling.
JP 2001-112016 A

  However, when the above technique is used for a matrix drive type display device such as a liquid crystal panel that cannot be displayed unless it is driven at a frequency higher than 4 fsc, the data sampled by the panel drive clock is lower than the drive clock frequency. Since the horizontal synchronization part of the Y signal converted to 4 fsc sampling data is phase-detected and line-locked, the phase error in the horizontal direction cannot be corrected with an accuracy within one clock of the drive clock, and one clock or more is displayed on the panel screen. Horizontal jitter occurs and image quality performance deteriorates.

  The present invention solves the above-described conventional problems, and provides a video signal processing circuit capable of decoding a composite signal only with a panel driving clock and correcting a horizontal phase error with accuracy within one clock of the driving clock. The purpose is to provide.

  In order to solve the above problems, a first video signal processing circuit according to the present invention includes a clock generation circuit that can be set to an arbitrary frequency, and an analog video signal that is digitally synchronized with a clock output from the clock generation circuit. A / D conversion circuit that converts to a signal, an interpolation circuit that interpolates data in a phase different from the sampling phase of the signal output from the A / D conversion circuit, and a burst phase error in the signal output from the interpolation circuit A burst phase detection circuit for controlling the interpolation circuit, a synchronization processing circuit for inputting a signal output from the A / D conversion circuit and outputting a phase error between the horizontal / vertical reference signal and the horizontal synchronization signal, and a burst phase detection circuit A phase error calculation circuit that inputs and calculates the phase error of the burst phase error that is output and the phase error of the horizontal synchronization signal that is output from the synchronization processing circuit, and that is output from the interpolation circuit R, G, and B signals that convert signals into R, G, and B signals, and R, G, and B signals that are output from the RGB conversion circuits and a phase that corrects the signals according to the phase error output from the phase error calculation circuit It has a configuration of an error correction circuit and a drive circuit that inputs the output of the phase error correction circuit and drives a matrix drive display device such as a liquid crystal panel.

  In order to achieve this object, a second video signal processing circuit according to the present invention is synchronized with a first clock and a clock generation circuit for generating first and second clocks having a multiplication or division relationship. An A / D conversion circuit that converts an analog video signal into a digital signal, an interpolation circuit that interpolates data in a phase different from the sampling phase of the signal output from the A / D conversion circuit, and an output from the interpolation circuit A burst phase detection circuit that detects a burst phase error of a signal and controls an interpolation circuit, and a synchronization processing circuit that inputs a signal output from an A / D conversion circuit and outputs a phase error between a horizontal / vertical reference signal and a horizontal synchronization signal A phase error calculation circuit that inputs and calculates the burst phase error output from the burst phase detection circuit and the phase error of the horizontal synchronization signal output from the synchronization processing circuit, and an interpolation circuit. The RGB conversion circuit that converts the input signal into R, G, and B signals, and the R, G, and B signals that are output from the RGB conversion circuit are input in synchronization with the first clock and output from the phase error calculation circuit. A phase error correction circuit that corrects the signal in accordance with the phase error to be output and outputs the signal in synchronization with the second clock; and a matrix drive type such as a liquid crystal panel that receives the output of the phase error correction circuit by inputting the output of the phase error correction circuit It has a structure of a drive circuit for driving the display device.

  Preferably, in the video signal processing circuit, the phase error calculation circuit includes a coefficient generation circuit that outputs a coefficient corresponding to a frequency of a clock output from the clock generation circuit, and a burst phase error output from the burst phase detection circuit. Jitter correction value for calculating the jitter correction value based on the coefficient output from the coefficient generation circuit, the horizontal reference signal output from the synchronization processing circuit, and the phase error between the horizontal synchronization signal and the clock output from the clock generation circuit A calculation circuit, a display rate control circuit for generating a decimation coefficient corresponding to the horizontal display rate of the video signal, an interpolation coefficient control circuit for generating a phase error and a write enable signal from the output of the jitter correction value calculation circuit and the decimation coefficient, and Is provided.

  Preferably, in the video signal processing circuit, the phase error correction circuit interpolates the video signal to a sample phase within one clock according to the phase error output from the phase error calculation circuit, and the interpolation filter circuit And a plurality of line memories that absorb a phase error of one clock unit or more by controlling writing and perform data thinning in the horizontal direction, and a horizontal jitter correction process and a read cycle of the plurality of line memories. The vertical resizing process is performed by changing.

  The video signal processing circuit according to the present invention is capable of line locking with burst lock signal processing and jitter accuracy within one clock using only an arbitrary clock according to the driving conditions of the panel or two kinds of clocks having a relationship of multiplication or division. Processing and driving processing can be realized. Therefore, there is an effect that the image quality performance is greatly improved as compared with the prior art. Furthermore, when building a clock system that takes into account the entire system configuration such as a liquid crystal TV, the clock frequency can be set arbitrarily, so that it is possible to prevent interference to the TV tuner and car navigation GPS. There is.

  Hereinafter, embodiments of the present invention will be described in the case where a liquid crystal panel to be used is a wide VGA panel of 800 pixels × 480 lines, for example, with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of a video signal processing circuit according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an analog video signal input terminal to which an NTSC composite video signal is input. Reference numeral 11 denotes a liquid crystal panel. Reference numeral 10 denotes a clock generation circuit which generates a 33.2 MHz clock (hereinafter referred to as CLK) which is a driving frequency of the liquid crystal panel 11.

  An A / D conversion circuit 2 converts an analog signal input from the analog video signal input terminal 1 into digital data in synchronization with CLK. An interpolation circuit 3 converts data from the A / D conversion circuit 2 into burst-locked 8 fsc sampling data. A burst phase detection circuit 4 detects a burst phase error from the data of the interpolation circuit 3 and feeds back the burst phase error to the interpolation circuit 3.

  A synchronization processing circuit 5 generates a phase error between the horizontal / vertical reference signal and the horizontal synchronization signal from the data output from the A / D conversion circuit 2. An RGB conversion circuit 6 separates the data from the interpolation circuit 3 into a Y signal and a C signal, and then decodes the C signal into an RY signal and a BY signal. The Y signal, the RY signal, and the BY signal are decoded. R, G, and B signals are generated from the signals. A phase error calculation circuit 7 calculates a burst phase error and a phase error of the horizontal synchronization signal.

  A phase error correction circuit 8 corrects the R, G, and B signals according to the phase error from the phase error calculation circuit. A drive circuit 9 drives the liquid crystal panel 11.

  In the video signal processing circuit configured as described above, FIGS. 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are used. The operation will be described.

  As shown in FIGS. 1 and 4, the video signal (waveform 40) input from the analog input terminal 1 is 33.2 MHz which is the driving frequency of the liquid crystal panel generated by the clock generation circuit 10 in the A / D conversion circuit 2. Is quantized into a digital video signal sampled in synchronization with the clock (waveform 41) (a cross mark of the waveform 40) and output from the A / D conversion circuit 2. After that, the data is converted into burst lock data (circle mark of the waveform 40) by the interpolation circuit 3 and the burst phase detection circuit 4 capable of interpolating data to a phase of 8 fsc.

  The burst phase detection circuit 4 outputs a phase reference pulse (waveform 42, hereinafter referred to as an LH pulse) of the burst lock data and a burst lock phase error (waveform 43, BL) to the phase error calculation circuit 7. The synchronization processing circuit 5 detects a composite synchronization signal from the digital video signal output from the A / D conversion circuit 2. Thus, in this embodiment, since the composite synchronization signal is detected directly from the output data of the A / D converter 2 quantized at 33.2 MHz, the conventional 4 fsc rate is used as shown in the schematic diagram of FIG. Therefore, it is possible to detect the composite synchronization with higher accuracy than when the composite synchronization is detected (error A <error B).

  In the synchronization processing circuit 5, an internal horizontal synchronization signal is generated by a countdown circuit, and a phase difference correction process between the internal horizontal synchronization signal and the detected composite synchronization signal is performed. As shown in FIG. 6, the phase difference 63 between the composite synchronizing signal 51 and the internal horizontal synchronizing signal 62 is divided into an integer part in clock units and a decimal part below the clock unit, and the integer part is fed back to the countdown circuit. It is output as a synchronous phase error (waveform 45, HL). The countdown circuit outputs a horizontal reference signal (waveform 44, HRST) whose phase is corrected with the value of the integer part of the phase error.

  FIG. 3 shows an example of the configuration of the phase error calculation circuit 7. In FIG. 3, reference numeral 31 denotes a coefficient generation circuit which outputs a clock coefficient 34 corresponding to the frequency of the clock output from the clock generation circuit 10 and the data interpolation rate in the interpolation circuit 3. A jitter correction value calculation circuit 30 is a burst phase error (BL) output from the burst phase detection circuit 4, a synchronization phase error (HL) output from the synchronization processing circuit 5, and a clock output from the coefficient generation circuit 31. Based on the coefficient 34, an offset value 35 and a jitter correction value 36 are calculated. A display rate control circuit 32 generates a thinning coefficient 37 corresponding to the horizontal display rate of the video signal. An interpolation coefficient control circuit 33 generates a phase error (CNTRL) and a write enable signal (WE) from the offset value 35, the jitter correction value 36, and the thinning coefficient 37.

  The coefficient generation circuit 31 has a clock coefficient of 8 fsc / 33.2 MHz based on the ratio of the data interpolation rate (8 fsc) in the interpolation circuit 3 and the frequency (33.2 MHz) of the clock output from the clock generation circuit 10. The clock coefficient 34 for rate conversion of the burst phase error (BL) and the synchronous phase error (HL) is calculated by the calculation formula.

  Next, the display rate control circuit 32 will be described. The display rate control circuit 32 is based on the data interpolation rate (8 fsc) in the interpolation circuit 3, the number of video display pixels on the liquid crystal panel (800 pixels), and the video display period (NTSC time ≈50 μs). The thinning coefficient for horizontal resizing is calculated by a calculation formula of 8 fsc × 50 μs). In this way, by generating a clock coefficient and decimation coefficient having arbitrary values according to the data interpolation rate, clock frequency, etc., jitter correction value calculation processing and horizontal resizing can be performed with a single circuit configuration for any clock frequency. Thinning-out processing is possible.

  Next, the jitter correction calculation circuit 30 will be described. The jitter correction calculation circuit 30 multiplies each of the burst phase error (BL) and the synchronization phase error (HL) by the clock coefficient 34, and the data value of the LH rate (8 fsc) from the data value of the clock rate (33.2 M). Coefficient conversion to (BL1 and HL1). BL1 is latched and calculated by the horizontal reference signal (HRST) and added to HL1, and the integer part of the addition result is used as an offset value 35 for the write enable signal, and the decimal part is used as a jitter correction value 36 for line lock conversion. Output.

  Next, the interpolation coefficient control circuit 33 will be described with reference to FIG. FIG. 7 is a diagram simply showing the circuit operation. For convenience, the LH1 pulse is fixed to H, the thinning coefficient for horizontal resizing is 2/3, and the jitter correction value is 1/6. The interpolation coefficient control circuit 33 applies an offset process by masking the input LH pulse according to the offset value 35 output from the jitter correction value calculation circuit 30 (the LH pulse after the offset is set as an LH1 pulse). The thinning coefficient 37 for horizontal resizing output from the display rate control circuit 32 is added to the decimal part 73 of the previous addition result fed back by the adder (waveform 72), and the addition result is an integer. If not, the LH1 pulse is thinned (waveform 74). Further, the decimal part 73 of the addition result is subjected to coefficient conversion according to the thinning coefficient 37 for horizontal resizing separately from the feedback to the adder (waveform 75). Thereafter, the LH1 pulse (waveform 74) and the decimal part (waveform 75) of the coefficient-processed addition result are offset by the value of the jitter correction value 36, and the phase error 76 (CNTRL) for line lock and the line memory to be described later The write enable signal 77 (WE) for 81 to 83 is output to the phase error output circuit 8.

  FIG. 8 is a configuration example of the phase error correction circuit 8. In FIG. 8, 80 is an interpolation filter circuit, 81 to 83 are line memories, 84 is a write control circuit, 85 is a read control circuit, 86 to 88 are selection circuits, 89 is a selection signal generation circuit, 90 to 92 are multipliers, 93 is a coefficient generating circuit, and 94 and 95 are adders. FIG. 9 is a configuration example of the interpolation filter circuit 80. In FIG. 9, reference numerals 100 to 104 denote load hold type flip-flops, 105 to 109 denote multipliers, 110 denotes an interpolation coefficient generation circuit, and 111 denotes an adder.

  The interpolation filter 80 shown in FIG. 9 receives R, G, and B signals, and the data T1 to T5 latched when the LH signal is “H” in the flip-flops 100 to 104 and the interpolation coefficient generation circuit 110 based on the CNTRL signal. The output coefficients K1 to K5 are multiplied and summed by multipliers 105 to 109 and adder 111 and output. FIG. 10 is an example of an impulse response of the interpolation filter 80, and is a diagram illustrating a case where the data is classified into coefficients K1 to K5 and data is interpolated with a quarter phase accuracy of CLK. The coefficients K1 to K5 have four kinds of coefficients, ◯ mark, Δ mark, □ mark, and ● mark, respectively, and are selected according to the CNTRL value. Phase correction is performed by interpolating data to the same phase at CLK and ◯, 1/4 phase at Δ, ½ phase at □, and 3/4 phase at ●. The operation is the same whether the CLK frequency is higher or lower than 33.2 MHz. Further, the interpolation filter circuit 80 includes a filter for interpolating the data of ○ and outputting □, a filter for interpolating the data of ○ and □ and outputting △ and ●, respectively, It is also possible to adopt a configuration for switching between. Further, by increasing the types of coefficients each of the coefficients K1 to K5, the phase accuracy of interpolation can be improved according to the number of coefficient types 1/8, 1/16, 1/32 of CLK. . Further, the frequency characteristics of the interpolation filter can be changed by changing the impulse response of the interpolation filter 80.

  Next, an operation of interlace / progressive conversion (hereinafter referred to as I / P conversion), which is an example of vertical resizing processing, will be described with reference to an operation waveform diagram shown in FIG. The I / P conversion displays the NTSC signal (horizontal frequency ≈ 15.734 KHz) as an input interlace signal on the wide VGA panel (horizontal frequency ≈ 31.4 KHz) which is a progressive display. This is done by setting it to 1/2 (31.75 μs) of the write cycle (63.5 μs). The line memories 81 to 83 receive R, G, and B signals that have been phase-corrected by the interpolation filter 80, and a WE signal and a write address (hereinafter referred to as WADR) corresponding to the horizontal display ratio output from the write control circuit 84. It is controlled by the signal, written at CLKF = CLK, and read at CLKR = CLK in accordance with a read address (hereinafter referred to as RADR) signal output from the read control circuit 85.

  As shown in FIG. 11, WE_0 in Line_1, WE_1 in Line_2, and WE_2 in Line_3 are each “H” active (in FIG. 11, the “H” is fixed for convenience. “L” and “L” occur alternately, and the data of the “L” period is thinned out), and the line memory 81 writes the data of Line_1 according to WADR_0 and reads it according to RADR_0. The line memory 82 writes the data of Line_2 according to WADR_1 and reads it according to RADR_1. The line memory 83 writes the data of Line_3 according to WADR_2 and reads it according to RADR_2.

  As a result, the line memory 81 reads Line_1 until Line_4 is written next. Similarly, the line memory 82 and the line memory 83 respectively read Line_2 and Line_3 until data is written next. The selection circuit 86, the selection circuit 87, and the selection circuit 88 receive the output signal LM_0 of the line memory 81, the output signal LM_1 of the line memory 82, and the output signal LM_2 of the line memory 83, respectively, and are signals output from the selection signal generation circuit 89. Select and output according to LM_SEL. The coefficient generation circuit 93 outputs coefficients K_0, K_1, and K_2 for vertical resizing.

  The multiplier 90 multiplies the output signal SEL_0 of the selection circuit 86 and the coefficient K_0. The multiplier 91 multiplies the output signal SEL_1 of the selection circuit 87 and the coefficient K_1. The multiplier 92 multiplies the output signal SEL_2 of the selection circuit 88 and the coefficient K_2. The adder 94 adds the output signal of the multiplier 90 and the output signal of the multiplier 91. The adder 95 adds the output signal of the adder 94 and the output signal of the multiplier 92. When K_0 is 1 and K_1 and K_2 are 0, the same line is read twice, resulting in I / P conversion. When K_0 and K_1 are ½ and K_2 is 0, I / P conversion is performed by linearly interpolating two lines. When K_0 is 2/4 and K_1 and K_2 are -1/4, the I / P conversion is performed with an aperture in the vertical direction.

  Next, the vertical zoom operation as an example of the vertical resize processing will be described with reference to the schematic diagram shown in FIG. 12 and the operation waveform diagram shown in FIG. The vertical zoom is a function that is used when a 4: 3 video signal is displayed on a wide panel, and is displayed on the panel by expanding the video signal by 4/3 times in the vertical direction. As shown in the schematic diagram of FIG. 12, the vertical zoom simultaneously performs I / P conversion and 4/3 times vertical enlargement. Therefore, 8/3 times vertical enlargement is performed by setting the line memory read cycle to the write cycle (63. 5/8) to 3/8 (23.8 μs).

  Also, two-line linear interpolation is performed with the coefficients shown in the figure to reduce the jagged feeling of diagonal lines. However, in this case, if CLK remains at 33.2 MHz, the number of clocks in the readout period becomes 790, which is less than the number of effective pixels 800, and the drive condition is not satisfied and display on the panel cannot be performed. Therefore, the frequency of CLK output from the clock generation circuit 10 is set to 44.3 MHz, which is 4/3 times. As a result, the number of clocks in the readout period is 1054, which satisfies the driving conditions.

As shown in FIG. 13, writing to the line memories 81 to 83 is the same as the above-described I / P conversion operation. The difference from the I / P conversion is the read cycle, the LM_SEL signal, and the coefficients K_0 and K_1 (K_2 is always 0 and is not shown in the figure), and operates so as to perform linear interpolation of two lines. . The output signal is
Line_1 = Line_0 × 8/8 + Line_1 × 0,
Line_2 = Line_0 × 5/8 + Line_1 × 3/8,
Line — 3 = Line — 0 × 2/8 + Line — 1 × 6/8,
Line — 4 = Line — 1 × 7/8 + Line — 2 × 1/8,
Line — 5 = Line — 1 × 4/8 + Line — 2 × 4/8,
Line — 6 = Line — 1 × 1/8 + Line — 2 × 7/8,
Line — 7 = Line — 2 × 6/8 + Line — 3 × 2/8,
Line_8 = Line_2 × 3/8 + Line_3 × 5/8
This is consistent with the schematic diagram shown in FIG.

  Further, although the magnification of the vertical zoom is 4/3 times, it is not limited to this magnification.

  As described above, the R, G, and B signals that have been subjected to I / P conversion or vertical zoom are input to the drive circuit 9 together with the HRST_O signal that serves as the horizontal reference for drive.

  The drive circuit 9 receives the output signal of the phase error correction circuit 8 and outputs drive pulses and R, G, and B signals necessary for driving the liquid crystal panel 11.

  As described above, burst lock signal processing, I / P conversion and vertical zoom processing, and driving processing can be realized with jitter correction accuracy within one clock only with a clock frequency corresponding to the panel driving conditions. Therefore, there is an effect that the image quality performance is greatly improved as compared with the prior art. Furthermore, when building a clock system that takes into account the entire system configuration such as a liquid crystal TV, the clock frequency can be set arbitrarily, so that it is possible to prevent interference to the TV tuner and car navigation GPS. There is.

(Embodiment 2)
FIG. 2 is a block diagram showing a configuration of a video signal processing circuit according to the second embodiment of the present invention. In FIG. 2, reference numeral 1 denotes an analog video signal input terminal to which an NTSC composite video signal is input. Reference numeral 11 denotes a liquid crystal panel. A clock generation circuit 12 generates CLKR obtained by multiplying CLKF and CLKF. An A / D conversion circuit 2 converts an analog signal input from the analog video signal input terminal 1 into digital data in synchronization with CLKF. An interpolation circuit 3 converts data from the A / D conversion circuit 2 into burst-locked 8 fsc sampling data.

  A burst phase detection circuit 4 detects a burst phase error from the data of the interpolation circuit 3 and feeds back the burst phase error to the interpolation circuit 3. A synchronization processing circuit 5 generates a phase error between the horizontal / vertical reference signal and the horizontal synchronization signal from the data output from the A / D conversion circuit 2. An RGB conversion circuit 6 separates the data from the interpolation circuit 3 into a Y signal and a C signal, and then decodes the C signal into an RY signal and a BY signal. The Y signal, the RY signal, and the BY signal are decoded. R, G, and B signals are generated from the signals. A phase error calculation circuit 7 calculates a burst phase error and a phase error of the horizontal synchronization signal.

  A phase error correction circuit 8 corrects the R, G, and B signals according to the phase error from the phase error calculation circuit. A drive circuit 9 drives the liquid crystal panel 11.

  The operation of the video signal processing circuit configured as described above will be described with reference to FIG. 2 only for parts different from the first embodiment. 1 differs from the configuration of FIG. 1 in that 12 clock generation circuits generate CLKR obtained by multiplying CLKF and CLKF, and a line memory 81 that constitutes a phase error correction circuit 8 from the A / D conversion circuit 2. The process up to writing of .about.83 is performed with CLKF, and the process after reading is performed with CLKR.

  The operation of the video signal processing circuit configured as described above will be described below. In the first embodiment, when performing vertical zoom, the frequency of CLK is increased from 33.2 MHz at the time of I / P conversion to 44.3 MHz which is 4/3 times, and the entire circuit is operated. 2, CLKF = 33.2 MHz and CLKR = CLKF × 4/3 = 44.3 MHz are generated from the clock generation circuit 12, and the A / D conversion circuit 2, the interpolation circuit 3, the burst phase detection circuit 4, and the synchronization processing circuit 5 are generated. The write operation of the line memories 81 to 83 constituting the RGB error conversion circuit 6, the phase error calculation circuit 7 and the phase error correction circuit 8 is operated by CLKF, and the read operation from the line memories 81 to 83 to the drive circuit 9 is operated by CLKR. Let The block operating at CLKF operates in the same manner as described in the explanation of the I / P conversion in the first embodiment. The block operating at CLKR operates in the same manner as described in the description of the vertical zoom processing of the first embodiment.

  As described above, the vertical zoom process can be realized by increasing the clock frequency corresponding to the vertical zoom after reading from the line memories 81 to 83 without increasing the clock frequency of the entire circuit. Therefore, in addition to the effect of the first embodiment, there is an effect that current consumption of the entire circuit can be reduced.

  In the above description, the example in which the line memory is composed of three lines is shown, but it is possible to realize it with four or more line memories.

  The video signal processing circuit according to the present invention uses only arbitrary clocks according to the driving conditions of the panel or two kinds of clocks having a multiplication or division relationship, and is capable of line-up with burst lock signal processing and jitter accuracy within one clock. Lock processing and drive processing can be realized.

  Therefore, when building a clock system in view of the effect that the image quality performance is greatly improved as compared with the conventional system and further the entire system configuration such as a liquid crystal TV, the clock frequency can be arbitrarily set, so that the TV tuner is disturbed. In the matrix drive display device such as a liquid crystal panel, the composite video signal is decoded into a Y signal, an RY signal, and a BY signal. The present invention is useful as a video signal processing circuit that realizes everything from burst lock processing necessary for the case to line lock processing including horizontal jitter correction and drive processing at only the clock frequency corresponding to the drive conditions of the panel.

1 is a block diagram showing a configuration of a video signal processing circuit according to Embodiment 1 of the present invention. The block diagram which shows the structure of the video signal processing circuit in Embodiment 2 of this invention. Block diagram showing the configuration of the phase error calculation circuit Waveform diagram for explaining the input signal of the phase error calculation circuit Schematic diagram for explaining the composite synchronization detection accuracy of the synchronization processing circuit Schematic diagram for explaining the phase difference detection operation of the synchronization processing circuit Waveform diagram for explaining the operation of the interpolation coefficient control circuit Block diagram showing the configuration of the phase error correction circuit Block diagram showing the configuration of the interpolation filter circuit The figure which shows an example of the impulse response of an interpolation filter circuit Operation waveform diagram for explaining operation of I / P conversion in the embodiment of the present invention Schematic diagram showing the operation of vertical zoom in the embodiment of the present invention. Operation waveform diagram for explaining the operation of vertical zoom in the embodiment of the present invention The block diagram which shows the structure of the video signal processing apparatus of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Analog video signal input terminal 2 A / D conversion circuit 3 Interpolation circuit 4 Burst phase detection circuit 5 Synchronization processing circuit 6 RGB conversion circuit 7 Phase error calculation circuit 8 Phase error correction circuit 9 Drive circuit 10, 12 Clock generation circuit 11 Liquid crystal panel 30 Jitter correction value calculation circuit 31 Coefficient generation circuit 32 Display rate control circuit 33 Interpolation coefficient control circuit 34 Clock coefficient 35 Offset value 36 Jitter correction value 37 Decimation coefficient 40 Composite video signal 41 Clock 42 Phase reference pulse 43 Burst lock phase error 44 Horizontal Reference signal 45 Sync phase error 51 Composite sync signal 52 4 fsc rate signal 62 Internal horizontal sync signal 71 Phase reference pulse after offset processing 72 Addition value of jitter correction value 73 Decimal part of addition value 72 Phase reference pulse 71 after decimation
75 Coefficient conversion value of waveform 73 76 Phase error 77 Write enable signal 80 Interpolation filter circuit 81, 82, 83 Line memory 84 Write control circuit 85 Read control circuit 86, 87, 88 Select circuit 89 Select signal generation circuit 90, 91, 92 Multiplier 93 Coefficient generation circuit 94, 95 Adder 100, 101, 102, 103, 104 Flip-flop 105, 106, 107, 108, 109 Multiplier 110 Interpolation coefficient generation circuit 111 Adder

Claims (4)

A clock generator that can be set to any frequency;
An A / D conversion circuit that converts an analog video signal into a digital signal in synchronization with a clock that is an output of the clock generation circuit;
An interpolation circuit that interpolates data in a phase different from the sampling phase of the digital signal that is the output of the A / D conversion circuit;
A burst phase detection circuit that detects a burst phase error of a signal that is an output of the interpolation circuit and controls an interpolation phase in the interpolation circuit;
A synchronous processing circuit for outputting a phase error between the composite synchronizing signal and the internal horizontal synchronizing signal detected based on the digital signal output of the A / D converter circuit,
A phase error calculation circuit that calculates a phase error based on a burst phase error that is an output of the burst phase detection circuit and a phase error of an internal horizontal synchronization signal that is an output of the synchronization processing circuit;
An RGB conversion circuit that converts a signal that is an output of the interpolation circuit into an R, G, B signal;
A phase error correction circuit for correcting R, G, wherein based on the phase error which is a type of B signal output of said phase error calculation circuit R, G, the phase of the B signal which is the output of the RGB converter,
A drive circuit that inputs an output of the phase error correction circuit and drives a matrix drive type display device in synchronization with a clock output from the clock generation circuit ;
A video signal processing circuit comprising: A clock generation circuit for generating first and second clocks having a multiplication or division relationship;
An A / D conversion circuit for converting an analog video signal into a digital signal in synchronization with the first clock;
An interpolation circuit that interpolates data in a phase different from the sampling phase of the digital signal that is the output of the A / D conversion circuit;
A burst phase detection circuit that detects a burst phase error of a signal that is an output of the interpolation circuit and controls an interpolation phase in the interpolation circuit;
A synchronous processing circuit for outputting a phase error between the composite synchronizing signal and the internal horizontal synchronizing signal detected based on the digital signal output of the A / D converter circuit,
A phase error calculation circuit that calculates a phase error based on a burst phase error that is an output of the burst phase detection circuit and a phase error of an internal horizontal synchronization signal that is an output of the synchronization processing circuit;
An RGB conversion circuit that converts a signal that is an output of the interpolation circuit into an R, G, B signal;
The R, G, B signals output from the RGB conversion circuit are input in synchronization with the first clock, and the phases of the R, G, B signals are determined based on the phase error output from the phase error calculation circuit. corrected, the phase error correction circuit for force out to synchronize the correction signal to the second clock,
A drive circuit for inputting the output of the phase error correction circuit and driving the matrix drive type display device in synchronization with the second clock ;
A video signal processing circuit comprising: The phase error calculation circuit includes:
A coefficient generation circuit that outputs a clock coefficient based on a frequency of a clock that is an output of the clock generation circuit and an interpolation rate in the interpolation circuit;
Write enable is used in the burst phase is the output burst phase error detection circuit, the line memory of the phase error correction circuit in which based on the clock coefficient output of which is the output synchronizing phase error and the coefficient generation circuit of the synchronous processing circuit A jitter correction value calculating circuit for calculating a signal offset value and a jitter correction value for line lock conversion ;
A display rate control circuit for generating a thinning coefficient based on the horizontal display rate of the video signal;
An interpolation coefficient control circuit that generates a line lock phase error and a write enable signal for a line memory of the phase error correction circuit based on the output of the jitter correction value calculation circuit and the thinning coefficient ;
The video signal processing circuit according to claim 1, further comprising: The phase error correction circuit includes:
An interpolation filter circuit that interpolates a video signal to a sample phase within one clock based on a phase error that is an output of the phase error calculation circuit;
And a plurality of line memories for performing input Rimizu horizontal direction of the data thinning by the control of writing the output of the interpolation filter circuit,
3. The video signal processing circuit according to claim 1, wherein a vertical resizing process is performed by varying a jitter correction process in a horizontal direction and a read cycle of the plurality of line memories.

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