JP3555486B2 - Digital video signal processor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital zoom circuit that expands and contracts a video signal in the horizontal direction by digital signal processing, and more particularly to a time such as jitter or skew generated by sampling an input analog signal with an unlocked sampling clock. The present invention relates to a digital video signal processing circuit in a case where an axis fluctuation occurs.
[0002]
[Prior art]
In recent years, digital zoom circuits in video signal processing are used not only for electronic zoom of video cameras, but also for display modes such as aspect conversion for wide display screens, image reduction processing for multi-screen display, and the like. It has become an indispensable processing circuit in digital video signal processing. A clock configuration usually used in digital video signal processing is to lock to an input video signal using a PLL circuit, and to use a burst lock clock system based on a color burst signal or a line based on a horizontal synchronization signal. Lock clock systems and the like are commonly used.
[0003]
First, as a conventional technique for performing horizontal scaling of a video signal by digital signal processing, a reduction interpolation circuit is used at the time of reduction using a memory, and a scaling interpolation circuit is used at the time of enlargement. Examples of the operation are shown in JP-A-8-223479 and JP-A-9-83960. Further, a conventional example in which enlargement / reduction is performed by one interpolation circuit is disclosed in Japanese Patent Application Laid-Open No. 9-166988. This is shown in FIG.
[0004]
In FIG. 14, after the data is latched by the input clock in the data input circuit 1, the interpolation operation is performed by the interpolation operation circuit 2 with the write clock Wclk which is twice as fast as the clock by an amount corresponding to a necessary magnification, and the write control circuit is operated. 5, writing is performed in the memory 3 and the read control circuit 6 reads and controls the read clock Rclk corresponding to the input clock. It is assumed that the input signal is sampled and signal-processed by the PLL means 8 using a clock locked to the input signal.
[0005]
Next, as a digital signal processing system for correcting jitter contained in an input video signal, for example, as shown in Japanese Patent Application Laid-Open No. 6-189277, writing to a circuit for performing an aspect conversion process using PLL means is described. In addition to a system that controls a clock and a read clock, many systems that perform time base correction using a PLL unit and a memory are also shown as TBC processes. Japanese Patent Application Laid-Open No. 9-275575 discloses a jitter correction video signal processing apparatus that corrects a phase difference detected by a phase shifter without using a PLL means by using a center-of-gravity shift circuit. I have. This is shown in FIG.
[0006]
In FIG. 15, one sampling of a synchronizing signal generated when performing YC separation and demodulation processing in digital signal processing is obtained from the phase of the synchronizing signal included in the analog composite color signal and the phase of the synchronizing signal captured by the digital circuit. The phase difference detection circuit 6 detects a time axis error within a cycle, calculates a coefficient in accordance with the phase difference, controls the center of gravity shift circuit 3, and performs a correction operation to shift the center of gravity of the image portion.
[0007]
In the prior art, the PLL means also controls clocks for adjusting a slight shift of a horizontal cycle due to a difference in an input video signal, adjusting an effective image range during one horizontal period accompanying the horizontal cycle, that is, adjusting a horizontal display rate. This was realized by adjusting the frequency.
[0008]
As described above, when the digital signal processing circuit performs a process such as a horizontal enlargement / reduction process or an aspect conversion, it is generally performed by a digital signal process which operates by a clock locked to a synchronization signal of an input signal by a PLL means. there were.
[0009]
[Problems to be solved by the invention]
However, in a two-screen display television or the like that simultaneously displays asynchronous two-system video signals, the clock configuration of the entire system is simplified for the purpose of reducing and rationalizing noise and crosstalk, and one of the two-system video signals is provided. In a video signal processing system that omits PLL means for the purpose of rationalizing the clock configuration circuit in signal processing on the unlocked side in a system that processes with only one locked clock system and other video signal processing, horizontal expansion is performed. In order to suitably perform signal processing such as reduction processing and aspect conversion, a jitter correction processing for correcting a time-axis deviation is indispensable and separately required.
[0010]
Further, in the conventional example of the jitter correction processing described in Japanese Patent Application Laid-Open No. 9-275575, correction of jitter contained in a composite color signal is performed, and only detection and correction of a time axis error within one sampling period of a synchronization signal can be performed. Therefore, in a signal processing system for a two-screen display television configured with only one system clock or a digital video signal processing system in which the PLL means is omitted, the time axis shift over one sampling period or more of the synchronizing signal may occur. It cannot be used because it occurs easily. In addition, when the horizontal enlargement / reduction processing is performed in this conventional example, an interpolation circuit is further required, and the deterioration of the signal is increased.
[0011]
On the other hand, in a system having no PLL means as described above, or in a signal processing not locking to an input, adjustment of a horizontal cycle or correction of a variation depending on an input signal is performed during one horizontal scanning period accompanying the horizontal cycle. It is necessary to perform the adjustment of the effective image range, that is, the control of the horizontal display ratio by a method other than the PLL means.
The present invention solves the problems of jitter correction and horizontal display rate adjustment in digital signal processing in such a clock system, and has a simple circuit configuration including only one interpolation operation circuit (interpolation filter). An object of the present invention is to realize a process of correcting a shift of a time axis over one sampling period or more, a process of scaling in a horizontal direction, and a control of a display ratio of a video in a horizontal direction.
[0012]
[Means for Solving the Problems]
In order to solve such a problem, a digital video signal processing device of the present invention oversamples an input analog signal at a sampling rate of a predetermined multiple of a clock rate to be output, and performs interpolation calculation processing at the sampling rate. A thinning-out write control to a memory is performed, and an interpolation processing circuit for performing horizontal scaling of a video signal by reading at the output clock rate is basically provided. In addition to this, a synchronization signal of the sampling digital video signal and the A jitter component is detected from an internal counter that operates with a sampling clock, and the jitter amount is divided into an integer component and a decimal component of the sampling rate from the detection result, and an interpolation coefficient calculation circuit that controls an interpolation operation for the integer component. Of the interpolation coefficient calculation circuit. A horizontal display ratio control circuit that controls the coefficient calculation to perform offset correction and simultaneously detects the horizontal display ratio by means similar to the jitter detection, and controls the magnification setting of the interpolation coefficient calculation circuit. Is provided.
[0013]
Thereby, the horizontal enlargement / reduction processing, the jitter correction processing, and the horizontal display rate control of the video signal can be processed at a time by one interpolation circuit, so that a suitable video signal processing with less image quality deterioration can be minimized. It can be obtained depending on the circuit scale.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Claims of the inventionIn oneThe described invention is a digital video signal processing apparatus for sampling an analog input video signal with a sampling clock that is not synchronized with the input signal and scaling the digital video signal in the horizontal direction. An interpolation operation circuit that performs horizontal scaling processing by performing an interpolation operation with a write clock of a predetermined multiple frequency clock of a clock rate, a memory that can operate writing and reading with different clocks, and A write control circuit for controlling the operation with a write clock, a read control circuit for reading at the output clock rate, an interpolation coefficient calculation circuit for performing an interpolation control operation on the interpolation arithmetic circuit and the write control circuit, Synchronizing signal of sampling digital video signal and said sampling signal A jitter detection circuit that detects a jitter component for each line from an internal counter that operates with a clock and controls an interpolation coefficient calculation circuit with the write clock; and operates with a synchronization signal of the digital video signal for sampling and the sampling clock. A horizontal display ratio control circuit for detecting the horizontal display ratio from the internal counter and controlling the interpolation coefficient calculation circuit, and performs a horizontal enlargement / reduction process, a jitter correction process, and a horizontal display ratio control of the video signal. This is a digital video signal processing device characterized by processing all at once with one interpolation circuit. Even in a system that performs digital signal processing by sampling with a clock that is not locked to the input video signal, It is easy to use small-scale interpolation processing for horizontal scaling performed for conversion and other purposes. In road construction, an effect that the control of the correction processing and horizontal display ratio of jitter carried out without increasing the picture quality deterioration by these correction.
[0015]
Claims of the inventionTo twoIn the digital video signal processing apparatus according to the present invention, the jitter detection circuit divides an amount of generated jitter for each line into an integer part and a decimal part of an operation clock of the jitter detection circuit. Is corrected by controlling the horizontal reference signal of the interpolation coefficient calculation circuit, and the decimal amount, that is, the phase amount of one clock or less, is corrected by offset control of the interpolation coefficient of the interpolation coefficient calculation circuit. The digital video signal processing apparatus is characterized in that the horizontal reference signal, which is a reference of the interpolation start position in the interpolation coefficient calculation circuit, is temporally shifted back and forth. Correction is performed by adjusting, and for the decimal part (phase component), the leading interpolation coefficient at the start of interpolation in the interpolation coefficient calculation circuit becomes the phase component. By controlling, with the effect that 1 even jitter amount for over a sampling period, can be corrected easily with little increase in circuit scale with respect to jitter correction.
[0019]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
(Embodiment 1)
FIG. 1 is a block diagram of a digital video signal processing device according to the first embodiment of the present invention. In FIG. 1, the digital video signal processing device AD-inputs an input analog video signal with an unlocked sampling clock Wclk. An AD converter 1, an interpolation coefficient calculation circuit 6 operating on the Wclk, a write control circuit 4 linked therewith, and an interpolation operation circuit 2 performing an interpolation operation process. A memory 3 operating at a required output clock rate Rclk, a read control circuit 5 operating at the Rclk, a synchronizing signal of a digital video signal A / D converted by the AD converter 1 and an internal counter operating at Wclk include: A jitter detection circuit 7 for detecting a jitter component for each line and controlling an interpolation coefficient calculation circuit 6; Detecting a horizontal display rate by the same means as the output circuit 7, and a horizontal display rate control circuit 8 which controls the interpolation coefficient calculation circuit 6.
[0021]
The operation of the digital video signal processing device configured as described above will be described with reference to FIG. 1, FIG. 5, and FIG.
[0022]
Here, the relationship between Wclk and Rclk is such that Rclk is determined from a required output clock rate, and Wclk is set to a predetermined multiple frequency of Rclk from a required range of horizontal magnification, and the purpose here is to improve jitter detection accuracy. And Wclk is three times Rclk.
[0023]
First, the input analog video signal is sampled by the A / D converter 1 at Wclk. Here, it is assumed that Wclk is not locked with respect to the input signal. It is a thing. This digital video signal is input to the interpolation arithmetic circuit 2 after necessary signal processing corresponding to the video signal form is performed with jitter. In the interpolation operation circuit 2, the interpolation coefficient is controlled by the interpolation coefficient calculation circuit 6 to perform the reduced interpolation operation, and the write control circuit 4 linked with the interpolation coefficient calculation circuit 6 performs the thinning-out writing to the memory 3.You.
[0024]
The jitter detection circuit 7 compares the horizontal synchronization signal included in the digital signal AD-converted by the AD converter 1 with a value created by a reference counter circuit provided in the jitter detection circuit 7 to calculate a digitized signal. , And outputs a jitter correction signal for each line. Further, the horizontal display rate control circuit 8 outputs a display rate signal for adjusting the length of one horizontal cycle of the digitized signal to a specified value for each line by means similar to the jitter detection circuit. The interpolation coefficient calculation circuit 6 calculates an interpolation coefficient such that the interpolation calculation circuit 2 performs an interpolation operation at a horizontal enlargement / reduction ratio controlled by the display ratio and with a correction by a jitter correction signal. Then, the operation of calculating the write control signal is performed.
[0025]
Hereinafter, a processing algorithm of the horizontal zoom + jitter processing by the above-described reduction interpolation processing will be described with reference to FIGS. The concept of pitch in FIG. 5 indicates the concept of operation pitch, which is a parameter for setting the interpolation operation magnification. This pitch is subtracted by one for each clock, and the pitch becomes 1 ≦ pitch <2. , The thinning-out operation is performed, and the decimal part at that time corresponds to the interpolation coefficient. By repeating the same operation while accumulating the operation pitch to the decimal part, the operation is performed to control the interpolation coefficient and the write signal.
[0026]
In the example of "1 time" in FIG. 5, since Wclk is three times Rclk, a 1 / 3-fold reduction operation is actually performed. In this case, the operation pitch is 3.0 and the interpolation coefficient is always 0. , The total interpolation is the same as 1/3 simple thinning. Similarly, to perform a 2 / 7-fold reduction operation, the operation pitch is set to 3.5. In this case, the interpolation coefficients are 0 and 0.5 (32 because the interpolation coefficient = 1 is actually 64). It is repeated alternately, and the total magnification becomes about 0.85 times.
[0027]
Also, as shown in the example of "1.2 times", if the calculation pitch is 2.5 and the 2/5 times reduction operation is performed, the total magnification becomes 1.2 times, and the enlargement processing is performed as a result. It becomes. Since FIG. 5 shows a case where no jitter is present, the first interpolation coefficient at the start of the interpolation starts from 0. FIG. 6 shows an example in which there is a jitter corresponding to the phase indicated by OFS with respect to the operation explanation example of each magnification described in FIG. 5, and as shown in FIG. By offsetting in the positive direction, the interpolation coefficient is offset and calculated. As a result, in the interpolation processing, an operation is performed so as to shift the phase horizontally rightward to correct the jitter.
[0028]
On the other hand, as for the horizontal display ratio, the above-mentioned calculation pitch is adjusted by the obtained display ratio (multiplying the display ratio obtained by setting the reference display ratio to 100%) to control the increase / decrease of the horizontal magnification, thereby controlling one line of the video signal. The display ratio control for each can be realized.
[0029]
As explained above, horizontal interpolation zoom processing, correction of jitter, and automatic adjustment of the horizontal display rate due to horizontal cycle fluctuation can be easily realized by one interpolation operation by one interpolation operation circuit. can do.
[0030]
(Embodiment 2)
FIG. 2 is a block diagram of a digital video signal processing device according to a second embodiment of the present invention. In FIG. 2, the digital video signal processing device AD-inputs an input analog video signal using an unlocked sampling clock Wclk. An AD converter 1, an interpolation coefficient calculation circuit 6 operating on the Wclk, a write control circuit 4 linked therewith, and an interpolation operation circuit 2 performing a scaling interpolation operation process, and writing operates on the Wclk. The reading is performed by a memory 3 operating at Rclk, which is a required output clock rate, a read control circuit 5 operating at Rclk, a synchronizing signal of a digital video signal AD output by the AD converter 1, and an internal counter operating at Wclk. From this, the jitter component of each line is detected, and only the integer of one clock or more of the jitter is detected. A jitter integer part control circuit 9 for controlling and controlling a horizontal reference signal for the interpolation coefficient calculation circuit 6, similarly detecting only the phase of the jitter of one clock or less, and generating a jitter correction signal for the interpolation coefficient calculation circuit 6. It comprises a jitter fraction part control circuit 10 for controlling, and a horizontal display rate control circuit 8 for detecting a horizontal display rate by means similar to the jitter detection and controlling the interpolation coefficient calculation circuit 6.
[0031]
The operation of the digital video signal processing device configured as described above will be described with reference to FIGS. 6, 7, and 8. FIG.
[0032]
In FIG. 6, the phase control based on the jitter is performed as described in the first embodiment. However, in the description of FIG. 6, the phase control is performed for one clock or less in Wclk and in the + direction (time direction backward with respect to the reference position). It only describes jitter correction. However, actually, since the jitter can be before and after the reference position and the jitter width can be one clock or more, the detected jitter amount is divided into an integer part and a decimal part (phase part) in the clock width, and the detected jitter amount is divided by the integer part. Is corrected by adjusting the horizontal reference position in the interpolation coefficient calculation circuit, and for decimals, the jitter is corrected by controlling the interpolation coefficient to be offset and output as described in the first embodiment. is there.
[0033]
Hereinafter, a specific description will be given with reference to FIGS.
[0034]
FIG. 7 is a circuit configuration diagram of the interpolation coefficient calculation circuit according to the present embodiment, which is a circuit that implements the interpolation control algorithm shown in FIG. In FIG. 7, the interpolation enable signal is a signal corrected by the horizontal reference signal controlled by the jitter integer part control circuit 9, and sets the start position of the interpolation operation described in FIG.
[0035]
The adder is an adder that accumulates the operation pitch at the timing when the write control signal of FIG. 6 is output, and the interpolation control subtraction counter is synchronized with the interpolation enable signal controlled by the jitter integer part control circuit 9. At the timing, a jitter correction offset value output from the jitter fraction part control circuit 10 of FIG. 2 is loaded, and the countdown operation is started using the offset value as the initial value of the counter, that is, the initial value of the interpolation coefficient. Thus, the operation of the algorithm shown in FIG. 6 is performed. Here, in order to simplify the counter circuit, the offset value for jitter correction, which is the initial value of the interpolation control subtraction counter, has an algorithm in which only the positive direction is set in the time axis direction as shown in FIG. For this reason, with respect to the jitter in the negative direction in the time axis direction, the horizontal reference position is output one clock before the jitter integer part control circuit, and the jitter amount control circuit 10 sets the phase amount in the positive direction. Therefore, an operation of outputting the opposite phase of the calculated phase amount as a jitter correction value is performed.
[0036]
The above description will be described with reference to the conceptual diagram of jitter correction in FIG.
[0037]
FIG. 8 schematically shows the concept of the correction for jitter including the case of one sampling period or more, and the numerical values of the input signals in FIG. 8 do not indicate the specific signal values, but the signal positions. It shows the concept and does not show the absolute time relationship in the interpolation result column.
[0038]
In FIG. 8, the example of jitter ± 0 is equivalent to the example of 1.0 times (1/3 simple thinning) of FIG. 5, and the interpolation result as shown in the interpolation result column for the input signal is obtained. This indicates that the operation is performed to thin out and write the signal at the position “W”.
[0039]
The example of the jitter of + ジ ッ タ phase in FIG. 8 is equivalent to the example of 1.0 times in FIG. 6, and the correction of the integer part is ± 0 (the interpolation coefficient calculation circuit actually uses the HRST signal indicated by the dotted line). (The image to be controlled), the decimal part correction value is reduced to 1/4, and an interpolation calculation result is output as shown in the figure. In the example of the jitter of +3/2 phase, the integer part correction is +1 and the decimal part correction value is ２, so that an interpolation operation result as shown is output, and the jitter correction in the positive direction is performed. .
[0040]
On the other hand, in the example of the jitter of −−１ phase, the integer part correction is −1 (an image in which the interpolation coefficient calculation circuit is actually controlled by the HRST signal indicated by the dotted line), and the decimal part correction value is 1-1 / 4. = 3/4, and an interpolation operation result as shown in the figure is output. Similarly, in the example of the jitter of -4/3 phase, the integer part correction is -2 and the phase correction value is 1-1 / 3 = 2/3, and the interpolation calculation result as shown is output. , Jitter correction in the negative direction is performed.
[0041]
As described above, the jitter detection is divided into an integer part and a decimal part, and different control is performed on the jitter detection circuit side depending on the direction of the jitter generation, so that the interpolation coefficient calculation circuit and the interpolation calculation circuit (that is, the correction processing) are performed. Side), the same simple configuration as when no jitter correction is performed, it is possible to easily correct even positive and negative jitter over one clock by interpolation.
[0042]
(Embodiment 3)
FIG. 3 is a block diagram of a digital video signal processing device according to a third embodiment of the present invention. In FIG. 3, the digital video signal processing device AD-inputs an input analog video signal with an unlocked sampling clock Wclk. An AD converter 1, an interpolation coefficient calculation circuit 6 operating on the Wclk, a write control circuit 4 linked therewith, and an interpolation operation circuit 2 performing a scaling interpolation operation process, and writing operates on the Wclk. The reading is performed by a memory 3 operating at Rclk, which is a required output clock rate, a read control circuit 5 operating at Rclk, a synchronizing signal of a digital video signal AD output by the AD converter 1, and an internal counter operating at Wclk. A jitter detection circuit 7 that detects a jitter component for each line and controls an interpolation coefficient calculation circuit 6 A horizontal display ratio control circuit 8 for detecting the horizontal display ratio by the same means as the jitter detection circuit 7 and controlling the interpolation coefficient calculation circuit 6, provided at a stage preceding the interpolation operation circuit, and adapted in accordance with the interpolation coefficient And an adaptive aperture circuit 9 for controlling the aperture.
[0043]
The operation of the digital video signal processing device configured as described above will be described with reference to FIG. 3, FIG. 9, FIG. 10, and FIG.
[0044]
FIG. 9 is a block diagram showing the configuration of the adaptive aperture circuit 9 in FIG. In FIG. 9, a band-pass filter is a band-pass filter for generating an aperture signal, and its frequency characteristics can be selected as necessary according to a video signal, a horizontal zoom magnification, and the like.
[0045]
Since primary interpolation is performed in the interpolation operation circuit 2 in FIG. 3, as shown in FIG. 11, the signal deterioration due to the interpolation operation is greatest when the interpolation coefficient = 0.5, and the interpolation coefficient = 0.5. Since the degree of deterioration differs according to the interpolation coefficient such that there is no deterioration in the case of 0, the gain control of the aperture signal is performed according to the interpolation coefficient. The characteristic of the gain control with respect to the interpolation coefficient is such that conversion as shown in FIG. 10 is performed by an interpolation coefficient → gain control signal conversion circuit.
[0046]
The timing of the interpolation coefficient input to the adaptive aperture circuit is adjusted with the coefficient calculated by the interpolation calculation circuit. As a result, as shown in FIG. 11, the aperture control is performed in advance to compensate for the deterioration of the frequency characteristic due to the interpolation operation.
[0047]
As described above, in one operation performed by one interpolation operation circuit, the horizontal enlargement / reduction zoom processing, the correction of the jitter, and the automatic adjustment of the horizontal display rate due to the horizontal cycle fluctuation are performed. Since the aperture can be controlled by the total interpolation coefficient performed by the arithmetic circuit, it is possible to efficiently compensate for jitter correction and horizontal display rate adjustment with the same circuit scale as in the case of horizontal scaling only, It is possible to obtain a good video signal in which the deterioration of the frequency characteristic due to the interpolation is suppressed.
[0048]
(Embodiment 4)
FIG. 4 is a block diagram of a digital video signal processing device according to a fourth embodiment of the present invention. In FIG. 4, the digital video signal processing device AD-inputs an input analog video signal using an unlocked sampling clock Wclk. An AD converter 1, an interpolation coefficient calculation circuit 6 operating on the Wclk, a write control circuit 4 linked therewith, and an interpolation operation circuit 2 performing a scaling interpolation operation process, and writing operates on the Wclk. The reading is performed by a memory 3 operating at Rclk, which is a required output clock rate, a read control circuit 5 operating at Rclk, a synchronizing signal of a digital video signal AD output by the AD converter 1, and an internal counter operating at Wclk. A jitter detection circuit 7 that detects a jitter component for each line and controls an interpolation coefficient calculation circuit 6 A horizontal display ratio control circuit 8 for detecting the horizontal display ratio by the same means as the jitter detection circuit 7 and controlling the interpolation coefficient calculation circuit 6, provided at a stage preceding the interpolation operation circuit, and adapted in accordance with the interpolation coefficient An adaptive aperture circuit 9 for controlling the aperture and an enlargement / reduction ratio setting circuit 10 for setting a zoom ratio arbitrarily according to the pixel position of the input signal.
[0049]
The digital video signal processing device configured as described above will be described with reference to FIG. 4, FIG. 12, and FIG. FIG. 12 is a block diagram showing the configuration of the enlargement / reduction ratio setting circuit 10 in FIG. In FIG. 12, the H-direction pixel position counter receives the horizontal reference signal controlled by the control of the integer part of the jitter according to the second, third, and fourth embodiments, and outputs a pixel number rate (output signal rate), that is, a read clock. By performing a count operation at the rate of Rclk, the pixel position signal is input to the decoder circuit as a pixel position signal on which the integer part of the jitter has been corrected.
[0050]
Accordingly, the pixel position rate is a predetermined multiple of the clock rate Wclk in the jitter detection unit (three times in the first, second, and third embodiments). , A correction in units of 1/3 phase is added, and an interpolation enable signal corresponding to the correction is output.
[0051]
The interpolation coefficient calculation pitch calculation counter circuit arbitrarily sets the value of the calculation pitch described in the second embodiment in the horizontal direction in units of the output signal rate, and the center of the input signal of the normal aspect is almost a perfect circle. The pixel position information (horizontal position information) for controlling this counter is a signal that has been subjected to the above-mentioned integer correction of jitter, and is used for aspect conversion processing for converting the image into a wide aspect by enlarging the periphery. Also, it outputs magnification information (interpolation coefficient calculation pitch) for the horizontal position in which the jitter has been correctly corrected.
[0052]
Then, by controlling the interpolation coefficient calculation pitch counter circuit in accordance with the horizontal display rate calculated by the horizontal display rate control circuit 8 in FIG. Automatic control can be realized. This will be described with reference to FIG. FIG. 13 shows an example of the above-described aspect conversion, which is a magnification setting curve in which the left and right ends of the video signal are enlarged, the central portion is reduced so as to be substantially a perfect circle, and the interval is linearly changed. Simply multiplying this curve results in the two-dot chain line in FIG. 13. In this case, it is difficult to set the total magnification between one line to be always constant (generally 1). Therefore, for example, as shown by the one-dot chain line in FIG. 13, by performing control to change the inclination of the reduction / enlargement section or change the section width in accordance with the horizontal display rate, even if the horizontal display rate is changed, 1 is obtained. Control can be performed such that the total magnification between lines is always constant.
[0053]
As for the horizontal display ratio, not only the adjustment of the display ratio due to the fluctuation of the horizontal cycle for each line due to the jitter, but also, as shown in FIG. The display ratio as the adjustment of the horizontal effective image width which differs according to the setting is also set.
[0054]
Needless to say, in the case of a fixed magnification in the horizontal direction, the calculation pitch calculation counter is fixed so as to obtain the corresponding magnification, and the display ratio adjustment can be realized by simply multiplying the display ratio.
[0055]
As described above, not only in the case of the fixed magnification in the horizontal direction but also in the case of changing the magnification in one line, such as in the aspect conversion processing, without changing the total magnification in one line, A horizontal zoom with a jitter correction function that can adjust the display ratio can be realized.
[0056]
【The invention's effect】
As is apparent from the above description, according to the present invention, the width of one sampling period or more is substantially the same as the circuit configuration of the horizontal scale interpolation processing in the conventional aspect conversion, digital zoom, and the like. The time axis correction processing such as jitter and skew with the fluctuation and the horizontal display rate correction and adjustment accompanying the fluctuation of the horizontal period and the adjustment of the effective image range width due to the jitter are easily and accurately performed. A horizontal digital zoom circuit in which the enlargement / reduction ratio can be arbitrarily set for each pixel can be realized while suppressing the deterioration of the frequency characteristic due to the interpolation operation.
[0057]
This makes it possible to simplify the clock configuration of the entire system in a dual-screen display television or the like that simultaneously displays asynchronous two-system video signals, and to perform circuit scale processing in the non-locking system signal processing of a system that processes only one system clock. It is possible to realize signal processing such as horizontal zoom processing and aspect conversion that can simultaneously perform horizontal display ratio adjustment while correcting jitter while suppressing image distortion.
[0058]
Also, in other video signal processing, a video signal processing system in which a PLL means is omitted for the purpose of rationalizing a clock configuration circuit and reducing the number of adjustments.It can be.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a digital video signal processing device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a digital video signal processing device according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a digital video signal processing device according to a third embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a digital video signal processing device according to a fourth embodiment of the present invention.
FIG. 5 is a schematic diagram for explaining an operation of the reduced interpolation control algorithm according to the first and second embodiments of the present invention in the case of no jitter.
FIG. 6 is a schematic diagram for explaining an operation at the time of jitter correction of the reduced interpolation control algorithm according to the first and second embodiments of the present invention.
FIG. 7 is a block diagram illustrating a configuration of an interpolation coefficient calculation circuit that performs a jitter correction method according to a second embodiment of the present invention;
FIG. 8 is a schematic diagram showing a concept of a jitter correction method according to a second embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of an adaptive aperture circuit according to a third embodiment of the present invention.
FIG. 10 is a conversion characteristic diagram of interpolation coefficients and gain control in the adaptive aperture circuit according to the third embodiment of the present invention.
FIG. 11 is a frequency characteristic diagram illustrating the concept of an adaptive aperture operation in the adaptive aperture circuit according to the third embodiment of the present invention.
FIG. 12 is a block diagram showing a configuration of a scaling factor setting circuit according to a fourth embodiment of the present invention;
FIG. 13 is an explanatory diagram showing an adjustment example of horizontal display ratio control in aspect conversion zoom according to the fourth embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of a conventional horizontal enlargement / reduction processing circuit.
FIG. 15 is a block diagram showing a configuration of a conventional composite color signal jitter correction circuit.
[Explanation of symbols]
1. . . A / D converter
2. . . Interpolation circuit
3. . . memory
4. . . Write control circuit
5. . . Read control circuit
6. . . Interpolation coefficient calculation circuit
7. . . Jitter detection circuit
8. . . Horizontal display ratio control circuit

Claims (2)

A digital video signal processing device for sampling an analog input video signal with a sampling clock that is not synchronized with the input signal and scaling the digital video signal in the horizontal direction, wherein the digital video signal of the sampling is multiplied by a predetermined multiple of the output clock rate. An interpolation operation circuit that performs horizontal scaling processing by performing an interpolation operation with a write clock of a frequency clock, a memory that can operate write and read with different clocks, and operates the memory with the write clock. A write control circuit for controlling; a read control circuit for reading at the output clock rate; an interpolation coefficient calculation circuit for performing an interpolation control operation on the interpolation arithmetic circuit and the write control circuit; and a digital video signal for sampling. Clock signal and the sampling clock. A jitter detection circuit for detecting a jitter component for each line from an internal counter to be operated and controlling an interpolation coefficient calculation circuit with the write clock; and an internal counter operating with a synchronization signal of the sampling digital video signal and the sampling clock. A horizontal display ratio control circuit for detecting the horizontal display ratio from the above, and controlling the interpolation coefficient calculation circuit. A digital video signal processing apparatus characterized in that processing is performed at once by an insertion circuit. The jitter detection circuit divides an amount of jitter generated for each line into an integer component and a decimal component of an operation clock of the jitter detection circuit, and controls a horizontal reference signal of the interpolation coefficient calculation circuit for the integer component. 2. A digital video signal processing apparatus according to claim 1, wherein the correction is performed, and the phase amount of a fractional number, that is, one clock or less, is corrected by offset control of the interpolation coefficient of the interpolation coefficient calculation circuit. .

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