JP3412454B2 - Video signal horizontal scaling circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic zoom circuit for enlarging and reducing a video signal in the horizontal direction by digital signal processing, and more particularly to enlarging or reducing an input video signal in one line depending on the image position. The present invention relates to a video signal horizontal enlargement / reduction circuit for performing the digital zoom calculation.

[0002]

2. Description of the Related Art In recent years, digital zoom circuits in video signal processing have been used not only for electronic zoom of video cameras,
It has also been used for supporting display modes such as aspect conversion for wide display screens and for image reduction processing for multi-screen display.

A conventional video signal horizontal scaling circuit will be described below. In the prior art, when the image signal processing circuit performs both enlargement and reduction of an image, only the enlargement process is performed in the digital signal process and the deflection current for driving the display unit of the display unit is corrected for the reduction process. However, there is an example in which the video signal displayed on the display unit is enlarged or reduced by changing the correction amount. This is shown, for example, in Japanese Patent Laid-Open No. 7-7723.

Further, as an example of aspect conversion in the case of a liquid crystal display device as a display means, an example of performing aspect conversion by switching a reference clock to control a liquid crystal drive circuit is disclosed in Japanese Patent Laid-Open No. 9-93518. Has been done. Further, if a system in which both enlargement and reduction are performed by digital signal processing is shown by a conventional technique, it is as shown in FIG.

In FIG. 9, the input signal is SW when enlarged.
3 on the enlargement side while being written in the memory 4 while being controlled by the write control circuit 5 and being read and controlled by the read control circuit 6 in accordance with the enlargement interpolation coefficient, the enlargement interpolation coefficient calculation circuit 8 The enlargement interpolation calculation circuit 7 performs the enlargement interpolation calculation with the calculated enlargement interpolation coefficient, and the SW9 operates so as to be output on the enlargement side.

At the time of reduction, the reduction interpolation calculation circuit 1 uses the reduction interpolation coefficient calculated by the reduction interpolation coefficient calculation circuit 2 for the input signal.
Reduced interpolation calculation is performed by the following, and SW3 is set to the reduction side and written in the memory 4 while being controlled by the write control circuit 5, and read out while being controlled by the read control circuit 6 according to the reduced interpolation coefficient and SW9 is reduced side. The enlargement processing and the reduction processing are realized by operating so as to be output as.

A system for performing horizontal enlargement / reduction processing by digital signal processing as described above is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-223479 or Japanese Patent Application Laid-Open No. 9-83.
No. 960 publication. Regarding the method of performing enlargement and reduction processing by digital signal processing in the horizontal direction as described above, FIG. 10 is a schematic diagram for explaining the operation of the horizontal enlargement processing of 5/4 times as an example, and FIG.
The schematic diagram explaining operation | movement of 5 times horizontal reduction processing is each shown.

[0008]

However, in the configuration in which the reduction process is performed by correcting the deflection current of the display means, the control of the display means is necessary, and it is realized by the control of the liquid crystal drive circuit in the case of the display on the liquid crystal display device. Even when
A control circuit for the liquid crystal drive circuit is required, and it depends largely on the display means.

Even if the enlargement / reduction processing is all performed by digital signal processing, in the conventional configuration as shown in FIG. 9, an interpolation calculation circuit and an interpolation coefficient control circuit for horizontal enlargement processing, Since an interpolating operation circuit and an interpolating coefficient control circuit for horizontal reduction processing, which have almost the same circuit scale, and an enlarging / reducing path switching and its control means are required, a redundant and large-scale circuit configuration is required. Was becoming.

Further, in order to adjust the image position and timing to make the enlarged / reduced image a natural image when switching between enlargement and reduction in an actual circuit, delay adjustment and its control circuit are necessary. Even if the enlargement / reduction is switched within a certain range during one line cycle, the control is complicated, and it is impossible or extremely difficult to arbitrarily set the enlargement / reduction for each pixel.

The present invention solves such a conventional problem, and one interpolation calculation circuit (interpolation filter)
It is an object of the present invention to provide a video signal horizontal enlargement / reduction circuit capable of performing both horizontal enlargement processing and horizontal reduction processing at an arbitrary magnification for each pixel with a simple circuit configuration.

[0012]

In order to solve this problem, the video signal horizontal scaling circuit of the present invention is capable of scaling the input signal once latched at the input clock rate (actual sampling clock rate). The input clock rate (actual sampling clock) is oversampled at a speed (double speed) faster than the input clock rate (actual sampling clock), and interpolation calculation processing and memory write control are performed at that oversampling rate. ), The enlarging / reducing process is performed.

As a result, all the interpolation calculation processing can be performed only by the reduction calculation processing (one interpolation calculation circuit), and the enlargement processing can be actually performed, and at the same time, the magnification can be set at any magnification for each pixel. A video signal horizontal scaling circuit that can be performed is obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention comprises a data input circuit for holding data of a digital video input signal at the input clock rate, and a digital video signal held by the data input circuit. An interpolation calculation circuit that performs horizontal expansion processing and horizontal reduction processing up to the predetermined multiple by performing reduction interpolation processing with a write clock having a frequency that is a predetermined multiple of the input clock, and writing and reading that has a size of a predetermined value or more. Capable of operating with different clocks, a write control circuit for controlling the write operation to the memory with the write clock, a read control circuit for controlling the read operation with a read clock of the input clock rate, Interpolation control operation with the write clock for the interpolation calculation circuit and the write control circuit And a interpolation coefficient calculation circuit among performed,
An image signal horizontal enlargement / reduction circuit characterized by performing enlargement processing and reduction processing up to a predetermined multiple in the horizontal direction of a video signal, wherein a digital video input signal is held at least once at the input clock rate. After that, by performing the reduced interpolation calculation processing while performing the oversampling operation with the write clock of the predetermined times, there is an effect that only the reduction interpolation calculation processing is performed and the enlargement operation up to the predetermined times is also performed.

According to the second and third aspects of the present invention, in the video signal horizontal scaling circuit according to the first aspect, the interpolation coefficient calculating circuit and the write control circuit are provided with respect to the second aspect. An enlargement / reduction ratio setting circuit for setting the magnification setting value by the described calculation method as an interpolation coefficient calculation pitch at the input clock rate is provided, and the interpolation coefficient calculation circuit is set by the enlargement / reduction ratio setting circuit. As a counter configured to integrate the insertion coefficient calculation pitch, the enlargement ratio and the reduction ratio up to the predetermined ratio are set to 1 in the horizontal direction during one line period of the digital video signal.
This is a video signal horizontal enlargement / reduction circuit characterized in that it can be set in pixel units, and the predetermined multiple (oversampling magnification) is set as the maximum enlargement magnification required by the system, and the actual enlargement / reduction magnification value is the predetermined multiple. By setting by the value divided by, it is possible to set the interpolation coefficient setting of the operation smoothly between expansion and contraction without any distinction between expansion and contraction, and according to the calculation magnification calculated in this way. By setting the interpolation coefficient calculation pitch for the actual control in units of the input clock rate (for each pixel) in the scaling interpolation coefficient calculation circuit, The operating interpolation coefficient calculation circuit is controlled so as to correspond to the magnification of the interpolation calculation for each pixel, and the magnification can be arbitrarily changed at the one-pixel rate. It has an effect of performing the processing and reduction processing.

According to a fourth aspect of the present invention, in the video signal horizontal enlargement / reduction circuit according to the third aspect, the enlargement / reduction magnification setting circuit sequentially counts the number of horizontal pixels of the digital image input signal. It has counter means for outputting the image position and conversion means for converting into a predetermined enlargement / reduction ratio according to the image position outputted from the counter means, and the interpolation coefficient calculation pitch which is the magnification setting value is set in the horizontal direction. To 1
A video signal horizontal enlarging / reducing circuit characterized by being linearly changed and set in pixel units, wherein the enlarging / reducing ratio setting circuit is responsive to a horizontal pixel position of a digital image input signal. A control circuit for setting the scaling factor value (that is, the interpolation coefficient calculation pitch) to be changed linearly is provided, and the digital video input signal is compressed / expanded in the horizontal direction by setting it accurately in one line cycle. To perform good horizontal scaling processing that is not unnatural due to the pixel position in the horizontal direction.

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a video signal horizontal scaling circuit according to a first embodiment of the present invention. In FIG. 1, the video signal horizontal scaling circuit uses the input clock of an input digital video signal. Data input circuit 1 that operates
And a scaling interpolation coefficient calculation circuit 4 that operates with a write clock that is a predetermined multiple of the input clock, a write control circuit 5 that is controlled in conjunction with the scaling interpolation coefficient calculation circuit 4, and a reduction interpolation calculation process. An interpolation calculation circuit 2 to be performed,
The write operation is performed by the write clock multiplied by the predetermined number, and includes a memory 3 that operates by the read clock of the input clock and a read control circuit 6 that operates by the input clock.

The operation of the video signal horizontal scaling circuit configured as described above will be described with reference to FIGS. 1, 4 and 5. The data input circuit 1 is a circuit that latches an input video signal at least once with the input clock (indicated as 1 / 2Wclk in FIG. 1). In an actual circuit system, for example, signal deterioration due to interpolation is reduced. This is a pre-stage process of passing an LPF circuit or the like as necessary. The input video signal is subjected to necessary processing at the input clock rate by this data input circuit, then output, and input to the interpolation calculation circuit 2. In the interpolation calculation circuit 2, the interpolation coefficient is controlled by the enlargement / reduction interpolation coefficient calculation circuit 4, the reduction interpolation operation of the input video signal is performed, and the write control circuit 5 interlocked with the enlargement / reduction interpolation coefficient calculation circuit 4 is executed. The write control is performed by the write operation to write to the memory 3. This series of operations corresponding to the portion surrounded by the dotted line in FIG. 1 is performed with a write clock that is a predetermined multiple (hereinafter X times) of the input clock in the data input circuit.

Therefore, in the interpolation calculation circuit 2, the input signal is X
Since an operation of performing oversampling at a multiplication factor of 2 and performing an interpolating operation at the same time is performed, the interpolating operation at the X times clock is m = n / X, where n is the actual scaling factor and m is the interpolating computation rate.
It is only necessary to perform the interpolation calculation processing corresponding to the above, and perform the write control to the memory according to the interpolation calculation processing. Therefore,
By keeping the maximum magnification n _max = X required as enlargement arithmetic processing may be carried out enlargement processing up to n _max at reduced interpolation processing.

The above-mentioned processing will be described below with reference to FIGS. 4 and 5, which schematically show the flow of signal processing. In Figure 4,
In the case of X = 2, an example of reduction of horizontal reduction ratio = 3/4 times is shown. The input signal is processed by the data input circuit 1 at the input clock rate and is sequentially 0, 1, 2, 3, 4, ...
・ And output the data. In the interpolation processing circuit which operates this at double speed (X = 2), 2 is over-sampled as shown in (a), and the scaling factor calculation circuit 4 performs 0, 0, 1 / order as shown in FIG. 3,1 / 3,2 / 3,2 / 3,
0,0,0,0,1 / 3,1 / 3 ... and 3/4 times interpolation coefficients are sequentially input by overlapping XT (2T), and the interpolation operation is performed in XT (2T) units. Then, as shown in the figure, (b) is calculated. The write control circuit 5 that works in conjunction with the scaling interpolation coefficient calculation circuit 4 converts this into 4 pixel data (8
Stop writing 1 pixel (2T) to T) (actually 2
Since the control is performed in units of T, in this example, the write operation is always stopped at the odd-numbered clock), and the 3T write operation in 8T is performed. Needless to say, this may be considered as 3/8 times reduction processing.

On the other hand, the read control circuit 6 is controlled by the input clock so that the write address and the read address are not overtaken, and as shown in FIG.
It is read out as shown in (c), and a reduction processing signal of horizontal 3/4 times is obtained as shown in FIG. 4 (c). In FIG. 5, X = 2
In this case, an example of horizontal enlargement magnification = 4/3 times is shown. Basically, the same applies to the case of enlargement, but the interpolation calculation coefficient is 0, 3/4, 2/4, 2/4, 1/4 in order from the enlargement / reduction interpolation coefficient calculation circuit 4 as shown in the figure. , 1/4, 0, 3
/ 4, 2/4 ... and only the portion where the addition of the interpolation coefficient is carried overlaps (in this example, 2/4 and 1/4)
The interpolation coefficients are sequentially input, and the interpolation calculation is performed as shown in FIG. 5 to calculate FIG. 5 (b). The write control circuit 5 that works in conjunction with the enlargement / reduction interpolation coefficient calculation circuit 4 performs a 4T write operation in 6T so as to stop writing twice (2T) in 3 pixel data (6T). The readout is processed in the same manner to obtain the enlarged processed signal of FIG.

Here, in the example shown in FIGS. 4 and 5,
Regarding the interpolation coefficient string and the write control, an example is shown in which the write control is performed by calculating with the interpolation coefficient of 3/4 times and the interpolation coefficient of 4/3 times in the case of the operation at the same clock, respectively. For 3/4 reduction, m = n / X = 3/4/4 = 3/8 times For 4/3 magnification, m = n / X = 4/3/2 = 4/6 times Even when the calculation is performed by performing the insertion coefficient sequence and the write control, the calculation data written in the memory is the same, and the same output results as shown in FIGS. 4C and 5C are obtained.

As described above, one interpolation operation circuit can perform the enlargement processing up to a predetermined magnification and the reduction processing by the same algorithm without distinction between enlargement and reduction. (Embodiment 2) FIG. 2 is a block diagram of a video signal horizontal scaling circuit according to a second embodiment of the present invention. In FIG. 2, the video signal horizontal scaling circuit uses the input clock of an input digital video signal. Data input circuit 1 that operates
And a scaling interpolation coefficient calculation circuit 4 that operates with a write clock that is a predetermined multiple of the input clock, a write control circuit 5 that is controlled in conjunction with the scaling interpolation coefficient calculation circuit 4, and a reduction interpolation calculation process. An interpolation calculation circuit 2 to be performed,
The write operation is performed by the write clock multiplied by the predetermined number, and is operated by the read clock of the input clock, the memory 3, the read control circuit 6 operated by the input clock, and the operation by the input clock within the scaling. The interpolation coefficient calculation circuit 4 is composed of an enlargement / reduction ratio setting circuit 7 for controlling the enlargement / reduction ratio in units of one pixel.

The operation of the video signal horizontal scaling circuit configured as described above will be described with reference to FIGS. 2, 4, 5 and 6. FIG. 6 is a diagram for explaining the scaling interpolation coefficient calculation circuit 4, the write control circuit 5, and the scaling ratio setting circuit 7 in FIG. In FIG. 6, the interpolation coefficient calculation counter is a counter that counts up by the interpolation coefficient calculation pitch within the specified horizontal calculation range, and its operation is shown in the integration of the interpolation coefficients in FIGS. 4 and 5. However, the counter value corresponds to the interpolation coefficient k in FIGS. 4, 5, and 6. Further, the carry signal of the counter is input to the write control circuit at the same time when the counter itself is controlled,
And is output as the / WE signal in FIGS.

The enlargement / reduction ratio setting circuit 7 is a circuit for controlling the interpolation coefficient calculation pitch, which is the count pitch of the interpolation coefficient calculation counter, and the input clock (in the example of the predetermined ratio = X = 2, the double speed). If the operating unit is the master clock of the system, it corresponds to a 1/2 frequency-divided clock), so that the interpolation coefficient calculation counter operating at the write clock can be set to a calculation magnification corresponding to one pixel unit. Is to do.

Here, the interpolation coefficient calculation counter is set to 6b.
If it is an it counter, the interpolation coefficient calculation pitch is 7 bits.
The MSB 1 bit indicates whether the enlargement or reduction is performed, and the write control circuit and the interpolation coefficient calculation counter are controlled. If the interpolation coefficient calculation pitch is p and the actual enlargement / reduction ratio is n, then p = 64 / n 2 in this example.

In the example of FIG. 4, p = 64 / (3/4) = 256/3 In the example of FIG. 5, p = 64 / (4/3) = 48. Therefore, in this case, MSB = 1 is reduced and MSB = 0 is enlarged. In the scaling ratio setting circuit, the interpolation coefficient calculation pitch p calculated in this way is set to a, b, c, d, e.
... and selectively set at the input clock rate. As a result, the interpolation coefficient calculation counter is set to 1
The interpolation coefficient k is calculated so as to correspond to the calculation magnification in pixel units, the interpolation coefficient is set as shown in the interpolation coefficient k in FIGS. 4 and 5, and the calculation magnification at one pixel rate is set. It is possible to operate so as to correspond to the setting (variable) of.

It should be noted that by the algorithm that the scaling factor is set at the calculation pitch p calculated as described above, the calculation pitch becomes the integrated value of the counter, and the counter is not reset within the 1H cycle. Even if you do not change the magnification gradually, the counter smoothly integrates at the point of switching from enlargement to reduction, so special exception handling is not required and smooth magnification change can be realized. it can.

(Third Embodiment) FIG. 3 is a block diagram of a video signal horizontal scaling circuit according to a third embodiment of the present invention. In FIG. 3, the video signal horizontal scaling circuit is a block diagram of an input digital video signal. A data input circuit 1 that operates with an input clock, a scaling interpolation coefficient calculation circuit 4 that operates with a write clock that is a predetermined multiple of the input clock, and a write control circuit that is interlocked with and controlled by the scaling interpolation coefficient calculation circuit 4. 5, an interpolation calculation circuit 2 for performing a reduced interpolation calculation process, a memory 3 for a write operation that operates with the write clock that is the predetermined multiple, and a read operation that operates with a read clock of the input clock, and the input clock. For the read control circuit that operates and the scaling interpolation coefficient calculation circuit 4 that operates by the input clock, one image is displayed according to the horizontal pixel position. And scaling linear magnification setting circuit 7 for controlling the scale factor linearly in the unit composed of H direction pixel position output circuit 8 for outputting the horizontal pixel position from the horizontal reference position of the input video signal.

The operation of the video signal horizontal scaling circuit configured as described above will be described with reference to FIGS. 3, 7, and 8. FIG. 7 is a diagram illustrating the scaling linear magnification control circuit 7 and the H-direction pixel position output circuit 8 in FIG. The H-direction pixel position counter is a counter that is reset by the H reference signal of the input video signal and counts up in 1 pixel units. If the counter value is within the interpolation range set by the control microcomputer or the like, the interpolation is performed. The range signal is output to the scaling factor calculation circuit. Also,
The counter value of the H-direction pixel position counter, that is, the pixel position signal, is converted into the interpolation coefficient calculation pitch p by the conversion circuit that linearly changes the interpolation coefficient calculation pitch according to the pixel position. It is input as the count-up value of the interpolation coefficient calculation counter described.

Here, an example of the interpolation coefficient calculation pitch setting for the horizontal pixel position in the conversion circuit is shown in FIG. H
When the interpolation coefficient calculation pitch as shown in FIG. 8 is input to the direction pixel position in the interpolation coefficient calculation counter, the enlargement ratio of the interpolation calculation decreases from the left side of the screen to the center of the screen. In the area, the image is fixed at a certain reduction ratio, and increases in a constant symmetrical manner in the right direction of the screen and returns to the maximum ratio at the rightmost end of the screen, resulting in an image with a change in magnification.

For example, if the input signal before enlargement / reduction is a diagonal slant signal from the lower left corner of the screen to the upper right corner of the screen, after this zoom calculation processing, the center of the diagonal line is a straight line and the lower left and upper right corners are S-shaped. It is converted into a curved image. The conversion circuit will be described with reference to the example of FIG. 8. By parameterizing the maximum magnification value, the magnification reduction section pixel number, the magnification fixed section pixel number, the magnification increase section pixel number, the magnification increase / decrease coefficient, etc. Asymmetrical and other arbitrary settings are possible. An example of the configuration of this conversion circuit is shown in the dotted line portion of FIG.

As described above, since the magnification can be linearly changed by horizontal zoom in aspect conversion or the like, it is possible to obtain a natural image with no discomfort.

[0034]

As is apparent from the above description, according to the present invention, the circuit scale is similar to the conventional circuit configuration only for horizontal enlargement processing or reduction processing, but up to several times in the horizontal direction. It is possible to realize a digital zoom circuit which can support both the enlargement processing and the horizontal reduction processing and which arbitrarily changes and sets the enlargement / reduction magnification for each pixel at the minimum.

With this arrangement, it is possible to smoothly set any desired enlargement / reduction digital zoom in the horizontal direction on a pixel-by-pixel basis without distinction of enlargement / reduction, and greatly improve the degree of freedom in setting the digital zoom. Also, for application to aspect conversion and the like, it is possible to easily perform natural and favorable image aspect conversion without a feeling of strangeness.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a video signal horizontal scaling circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a video signal horizontal scaling circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration block diagram of a video signal horizontal scaling circuit according to a third embodiment of the present invention.

FIG. 4 is a system explanatory view showing a 3/4 times reduction operation according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a method showing a 4/3 times enlargement operation of the same.

FIG. 6 is a configuration block diagram of a scaling interpolation control unit according to a second embodiment of the present invention.

FIG. 7 is a configuration block diagram of an enlargement / reduction linear magnification control unit according to a third embodiment of the present invention.

FIG. 8 is a pixel position / interpolation coefficient calculation pitch conversion characteristic diagram according to the third embodiment of the present invention.

FIG. 9 is a block diagram of a configuration of a conventional horizontal scaling circuit.

FIG. 10 is a schematic diagram illustrating an operation during horizontal enlargement processing of a conventional example.

FIG. 11 is a schematic diagram illustrating an operation during horizontal reduction processing of a conventional example.

[Explanation of symbols]

1 Data input (hold) circuit 2 Scale interpolation circuit 3 memory 4 Enlargement / reduction interpolation coefficient calculation circuit 5 Write control circuit 6 Read control circuit 7 Enlargement / reduction ratio setting circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-210111 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 5/00-5/42 H04N 5 / 14 H04N 5/228 H04N 5/262

Claims (5)

(57) [Claims] 1. A data input circuit for holding data of a digital video input signal at the input clock rate, and a digital video signal held by the data input circuit reduced by a write clock having a frequency of a predetermined multiple of the input clock. An interpolation operation circuit for performing horizontal expansion processing and horizontal reduction processing up to the predetermined times by performing the insertion processing, a memory having a size equal to or larger than a predetermined value and capable of operating writing and reading with different clocks, and the memory. A write control circuit for controlling a write operation with the write clock, a read control circuit for controlling a read operation with a read clock having the input clock rate, and the write for the interpolation operation circuit and the write control circuit. An interpolation coefficient calculation circuit that performs an interpolation control operation with a clock, and a video signal Video signal horizontal scaling circuit, which comprises carrying out the reduction processing and enlargement processing to the predetermined times in the horizontal direction. 2. The video signal horizontal enlargement / reduction circuit according to claim 1, wherein the interpolation coefficient calculation circuit and the interpolation operation circuit have only reduction interpolation processing means up to 1 time,
An interpolation coefficient is calculated based on a value obtained by dividing the actually required scaling factor by the predetermined multiple, that is, a scaling factor of 1 or less,
A video signal horizontal enlargement / reduction circuit characterized by controlling the interpolation operation circuit and the write control circuit. 3. The video signal horizontal enlargement / reduction circuit according to claim 1, wherein the interpolation coefficient calculation circuit and the write control circuit are provided with a magnification setting value obtained by the calculation method according to claim 2 as an interpolation coefficient. An enlargement / reduction ratio setting circuit is set as the operation pitch at the input clock rate, and the interpolation coefficient calculation circuit is composed of a counter that integrates the interpolation coefficient operation pitch set by the enlargement / reduction ratio setting circuit. An image signal horizontal enlargement / reduction circuit characterized in that an enlargement factor and a reduction factor up to the predetermined magnification can be set in units of one pixel in the horizontal direction during one line period of a digital image signal. 4. A video signal horizontal enlargement / reduction circuit according to claim 3, wherein said enlargement / reduction ratio setting circuit counts the number of horizontal pixels of said digital video input signal sequentially and outputs an image position, A conversion unit for converting the image data output from the counter unit into a predetermined enlargement / reduction ratio, and linearly changing the interpolation coefficient calculation pitch, which is the magnification setting value, in units of one pixel in the horizontal direction. Video signal horizontal scaling circuit characterized by setting. 5. The video signal horizontal enlargement / reduction circuit according to claim 4, wherein the interpolation coefficient calculation pitch, which is the magnification setting value linearly changed according to the image position, is input to the display means. A video signal horizontal scaling circuit characterized by being determined according to the aspect ratio of the video in.