JPH0787248B2 - Method of forming thin film transistor - Google Patents
Method of forming thin film transistorInfo
- Publication number
- JPH0787248B2 JPH0787248B2 JP61245039A JP24503986A JPH0787248B2 JP H0787248 B2 JPH0787248 B2 JP H0787248B2 JP 61245039 A JP61245039 A JP 61245039A JP 24503986 A JP24503986 A JP 24503986A JP H0787248 B2 JPH0787248 B2 JP H0787248B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor layer
- thin film
- film transistor
- operating semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 claims description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 19
- 239000011810 insulating material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 150000003377 silicon compounds Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 11
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 11
- 230000007547 defect Effects 0.000 description 7
- 238000004381 surface treatment Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は逆スタガード型薄膜トランジスタのゲート絶縁
膜を、動作半導体層の表面処理に用いる弗酸(HF)溶液
で溶解されない絶縁材料からなる下層絶縁膜と、シリコ
ン化合物からなる上層絶縁膜とからなる積層構造とし
て、HF系溶液によるエッチング工程でゲート電極とソー
ス電極またはドレイン電極間の短絡発生を防止するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention provides a gate insulating film of an inverted staggered thin film transistor, a lower insulating film made of an insulating material which is not dissolved by a hydrofluoric acid (HF) solution used for surface treatment of an operating semiconductor layer, and a silicon film. As a laminated structure including an upper insulating film made of a compound, a short circuit between the gate electrode and the source electrode or the drain electrode is prevented in an etching process using an HF-based solution.
本発明は、薄膜トランジスタの形成方法に関する。 The present invention relates to a method for forming a thin film transistor.
薄膜トランジスタをマトリクス配列した液晶表示装置
(LCD)等のアクティブマトリクス型の表示パネルで
は、各画素に1個の薄膜トランジスタ素子が必要であ
る。従って、1個のパネルには数百×数百の素子が設け
られることとなり、しかもこれらを無欠陥で形成しなけ
ればならない。In an active matrix type display panel such as a liquid crystal display (LCD) in which thin film transistors are arranged in matrix, one thin film transistor element is required for each pixel. Therefore, one panel is provided with several hundreds × several hundreds of elements, and these must be formed without defects.
もしゲート電極と、ソース電極またはドレイン電極間に
1個所でも短絡欠陥が存在すると、単にその画素のみが
不良となる点欠陥ではおさまらず、この欠陥を有するバ
スラインに接続する画素全部が不良となる、いわゆる線
欠陥となり、表示装置としては致命的な不良となってし
まう。If there is a short-circuit defect even at one location between the gate electrode and the source or drain electrode, it is not limited to the point defect in which only that pixel is defective, but all pixels connected to the bus line having this defect are defective. The so-called line defect causes a fatal defect in the display device.
従来の薄膜トランジスタの構造を第2図に示す。The structure of a conventional thin film transistor is shown in FIG.
同図において、1はガラス基板、2はクロム(Cr)等の
導電性材料よりなるゲート電極、3はSiO2からなるゲー
ト絶縁膜、4はアモルファスシリコン(a−Si)よりな
る動作半導体層、5,5′はアルミニウム(Al)等の導電
性材料よりなるソース及びドレイン電極である。In the figure, 1 is a glass substrate, 2 is a gate electrode made of a conductive material such as chromium (Cr), 3 is a gate insulating film made of SiO 2 , 4 is an operating semiconductor layer made of amorphous silicon (a-Si), Reference numerals 5 and 5'represent source and drain electrodes made of a conductive material such as aluminum (Al).
上記構造において、ゲート絶縁膜3は必ずしもSiO2であ
る必要はないが、その上層に形成される動作半導体層4
との界面特性を良好に保つには、動作半導体層4と同系
の材料を用いることが望ましい。かかる理由により動作
半導体層4としてa−Si層を用いた場合には、ゲート絶
縁膜3として通常シリコン(Si)の化合物が用いられ
る。In the above structure, the gate insulating film 3 is not necessarily made of SiO 2 , but the operating semiconductor layer 4 formed thereabove.
It is desirable to use the same material as that of the operating semiconductor layer 4 in order to maintain good interface characteristics with. For this reason, when the a-Si layer is used as the operating semiconductor layer 4, a compound of silicon (Si) is usually used as the gate insulating film 3.
このゲート絶縁膜3の上に動作半導体層4と、その上に
ソース電極5及びドレイン電極5′を罫線して、逆スタ
ガード型薄膜トランジスタが完成する。The operating semiconductor layer 4 and the source electrode 5 and the drain electrode 5 ′ on the gate insulating film 3 are ruled to complete the inverted staggered thin film transistor.
なお、上記ソース電極5及びドレイン電極5′を形成す
るに先立って、下層の動作半導体層4と良好な接触を得
るため、動作半導体層4にはHF系のエッチング液により
表面処理を施す。Prior to forming the source electrode 5 and the drain electrode 5 ′, the operating semiconductor layer 4 is surface-treated with an HF-based etching solution in order to obtain good contact with the underlying operating semiconductor layer 4.
ところが上記従来の構造では、動作半導体層4にピンホ
ールが存在すると、上述の表面処理工程において、その
下層のゲート絶縁膜3の上記ピンホールに連なる部分が
エッチングされてゲート電極2に到達する貫通孔が形成
され、この開口貫通孔内にソース電極5及びドレイン電
極5′の形成工程で、Al等の導電材料が充填されてしま
う。そのため、ゲート電極2とソース電極5またはドレ
イン電極5′間の短絡が発生する。However, in the above-described conventional structure, when a pinhole exists in the operating semiconductor layer 4, a portion of the gate insulating film 3 thereunder, which is continuous with the pinhole, is etched to reach the gate electrode 2 in the surface treatment step. A hole is formed, and a conductive material such as Al is filled in the opening through hole in the process of forming the source electrode 5 and the drain electrode 5 '. Therefore, a short circuit occurs between the gate electrode 2 and the source electrode 5 or the drain electrode 5 '.
本発明の目的は、上述のように動作半導体層の表面処理
工程において、下層のゲート絶縁膜を貫通しゲート電極
に到達する貫通孔を生じることのない、薄膜トランジス
タの改良された形成方法を提供することにある。It is an object of the present invention to provide an improved method for forming a thin film transistor, which does not form a through hole penetrating the lower gate insulating film and reaching the gate electrode in the surface treatment step of the operating semiconductor layer as described above. Especially.
薄膜トランジスタの形成方法では、ゲート絶縁膜を、動
作半導体層の表面処理工程に使用する弗酸溶液に溶解し
ない絶縁材料からなる下層絶縁膜とシリコン化合物から
なる上層絶縁膜を順に積層して形成する構成が採られて
いる。In the method of forming a thin film transistor, the gate insulating film is formed by sequentially stacking a lower insulating film made of an insulating material that is insoluble in the hydrofluoric acid solution used in the surface treatment step of the operating semiconductor layer and an upper insulating film made of a silicon compound. Is taken.
本発明の薄膜トランジスタ形成方法はゲート絶縁膜の下
層絶縁膜にHF系エッチング液に溶解しない材料を用いる
ため、活性層にピンホールがあっても、活性層の表面処
理に用いられるHF系エッチング液によるエッチングは上
層絶縁膜で停止するので、ソース,ドレイン電極からゲ
ート電極に到達する貫通孔は形成されない。Since the thin film transistor forming method of the present invention uses a material that does not dissolve in the HF-based etching solution for the lower insulating film of the gate insulating film, even if there are pinholes in the active layer, the HF-based etching solution used for the surface treatment of the active layer is used. Since the etching stops at the upper insulating film, the through holes reaching the gate electrode from the source / drain electrodes are not formed.
しかも動作半導体層と接触する上層絶縁膜は、従来のゲ
ート絶縁膜と同一材料を用いているので、動作半導体層
との界面特性を損なう虞もない。Moreover, since the upper insulating film that is in contact with the operating semiconductor layer is made of the same material as that of the conventional gate insulating film, there is no fear of impairing the interface characteristics with the operating semiconductor layer.
以下本発明の一実施例を、第1図を用いて説明する。 An embodiment of the present invention will be described below with reference to FIG.
同図において、1はガラス基板のような透明絶縁性基
板、2は例えばクロム(Cr)よりなるゲート電極、31は
HF系のエッチング液に溶解しない絶縁膜よりなる下層絶
縁膜、32はシリコン(Si)化合物よりなる上層絶縁膜、
5はa−Siのような半導体よりなる動作半導体層、5,
5′はAlのような導電性材料よりなるソース及びドレイ
ン電極である。In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate electrode made of, for example, chromium (Cr), and 31 is
A lower layer insulating film made of an insulating film that does not dissolve in an HF-based etching solution, 32 an upper layer insulating film made of a silicon (Si) compound,
5 is an operating semiconductor layer made of a semiconductor such as a-Si,
Reference numeral 5'denotes source and drain electrodes made of a conductive material such as Al.
上記下層絶縁膜31は、HF系のエッチング液に溶解しない
絶縁膜であれば良く、例えばポリイミド樹脂をスピン・
コーティング法によって塗布することにより形成でき
る。The lower insulating film 31 may be an insulating film that does not dissolve in an HF-based etching solution, such as a polyimide resin spin-coated.
It can be formed by applying by a coating method.
上層絶縁膜32は、Siの化合物からなる絶縁膜で、例えば
SiO2(二酸化シリコン)や窒化シリコン(SiN)等を、
周知のプラズマ化学気相成長法によって成膜することに
より形成できる。The upper insulating film 32 is an insulating film made of a compound of Si, for example,
SiO 2 (silicon dioxide), silicon nitride (SiN), etc.
It can be formed by forming a film by a well-known plasma chemical vapor deposition method.
このようにして本実施例ではゲート絶縁膜3を、ポリイ
ミド樹脂のようなHF系のエッチング液に溶解しない絶縁
材料よりなる下層絶縁膜31と、シリコン化合物からなる
上層絶縁膜32ととを積層して形成したものである。In this way, in this embodiment, the gate insulating film 3 is formed by laminating the lower layer insulating film 31 made of an insulating material such as polyimide resin which is not dissolved in an HF-based etching solution and the upper layer insulating film 32 made of a silicon compound. It was formed.
これ以外の他の部分は、前記第2図に示した従来の薄膜
トランジスタの構成と変わるところはない。即ち、上記
上層絶縁膜32の上に、a−Siよりなる動作半導体層4,そ
の上にソース電極5及びドレイン電極5′を形成して本
実施例の薄膜トランジスタが完成する。Other parts than this are the same as the structure of the conventional thin film transistor shown in FIG. That is, the operating semiconductor layer 4 made of a-Si and the source electrode 5 and the drain electrode 5'are formed on the upper insulating film 32 to complete the thin film transistor of this embodiment.
このように本実施例の薄膜トランジスタは、下層絶縁膜
31がHF系のエッチング液に溶解しない絶縁材料をもって
形成されているので、その製造工程途中のソース電極5
及びドレイン電極5′の形成に先立つ動作半導体層4の
表面処理において、たとえ動作半導体層4にピンホール
が存在し、上層絶縁膜32はHF系のエッチング液によりエ
ッチングされて貫通孔が生じても、下層絶縁膜31はおか
されず、貫通孔の形成はここで停止する。As described above, the thin film transistor of this embodiment has a lower insulating film.
Since 31 is formed of an insulating material that does not dissolve in the HF-based etching solution, the source electrode 5 during the manufacturing process
In the surface treatment of the operating semiconductor layer 4 prior to the formation of the drain electrode 5 ′, even if a pinhole exists in the operating semiconductor layer 4 and the upper insulating film 32 is etched by an HF-based etching solution to form a through hole. The lower insulating film 31 is not removed, and the formation of the through hole is stopped here.
従ってこの後、ソース電極5及びドレイン電極5′の形
成工程において、上層絶縁膜32に形成された貫通孔に導
電性材料をが充填されても、これは下層絶縁膜31表面ま
でしか到達せず、ゲート電極2が短絡されることはな
い。Therefore, even if the through hole formed in the upper insulating film 32 is filled with the conductive material in the step of forming the source electrode 5 and the drain electrode 5 ′ thereafter, this can reach only the surface of the lower insulating film 31. The gate electrode 2 is never short-circuited.
なお本実施例の構造では、動作半導体層4と接触する上
層絶縁膜32の材料にはSi化合物を用いているので、両者
の界面特性は従来構造の薄膜トランジスタと同様で、何
の悪影響もない。In the structure of this embodiment, since the Si compound is used as the material of the upper insulating film 32 in contact with the operating semiconductor layer 4, the interface characteristics between them are the same as those of the thin film transistor of the conventional structure, and there is no adverse effect.
以上説明した如く本発明によれば、HF系のエッチング液
を用いることによるゲート電極とソース電極,またはド
レイン電極間の短絡欠陥の発生がなくなる。As described above, according to the present invention, the occurrence of short-circuit defects between the gate electrode and the source electrode or the drain electrode due to the use of the HF-based etching solution is eliminated.
【図面の簡単な説明】 第1図は本発明一実施例の構成説明図、 第2図は従来構造説明図である。 図において、1は透明絶縁性基板、2はゲート電極、3
はゲート絶縁膜、4は動作半導体層、5及び5′はそれ
ぞれソース電極及びドレイン電極、31は下層絶縁膜、32
は上層絶縁膜を示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural explanatory view of an embodiment of the present invention, and FIG. 2 is a conventional structural explanatory view. In the figure, 1 is a transparent insulating substrate, 2 is a gate electrode, 3
Is a gate insulating film, 4 is an operating semiconductor layer, 5 and 5'are source and drain electrodes, 31 is a lower insulating film, and 32 is a lower insulating film.
Indicates an upper insulating film.
Claims (1)
該ゲート電極を覆うように弗酸溶液に溶解しない絶縁材
料からなる下層絶縁膜とシリコン化合物からなる上層絶
縁膜を順に積層してゲート絶縁膜を形成し、その上に動
作半導体層を形成し、該動作半導体層を弗酸溶液により
表面処理してからその表面に前記ゲート電極に対応して
ソース電極及びドレイン電極を形成する工程を含んでな
ることを特徴とする薄膜トランジスタの形成方法。1. After forming a gate electrode on an insulating substrate,
A lower insulating film made of an insulating material that does not dissolve in a hydrofluoric acid solution and an upper insulating film made of a silicon compound are sequentially stacked so as to cover the gate electrode to form a gate insulating film, and an operating semiconductor layer is formed thereon. A method of forming a thin film transistor, comprising a step of surface-treating the operating semiconductor layer with a hydrofluoric acid solution and then forming a source electrode and a drain electrode corresponding to the gate electrode on the surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61245039A JPH0787248B2 (en) | 1986-10-14 | 1986-10-14 | Method of forming thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61245039A JPH0787248B2 (en) | 1986-10-14 | 1986-10-14 | Method of forming thin film transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6398152A JPS6398152A (en) | 1988-04-28 |
JPH0787248B2 true JPH0787248B2 (en) | 1995-09-20 |
Family
ID=17127673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61245039A Expired - Fee Related JPH0787248B2 (en) | 1986-10-14 | 1986-10-14 | Method of forming thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0787248B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07114284B2 (en) * | 1988-07-29 | 1995-12-06 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
JPH03196678A (en) * | 1989-12-26 | 1991-08-28 | Sanyo Electric Co Ltd | Thin film transistor and manufacture of the same |
-
1986
- 1986-10-14 JP JP61245039A patent/JPH0787248B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS6398152A (en) | 1988-04-28 |
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