JPH0787234B2 - Lead frame - Google Patents

Description

The present invention relates to a lead frame used in a semiconductor device such as an IC (semiconductor integrated circuit).

“Conventional Technology” In mounting semiconductor devices such as ICs, highly reliable and inexpensive mounting methods are desired. However, according to the recent increase in the scale of semiconductor integrated circuits, it will be mounted.
As the number of pins and the pitch of IC packages are accelerating, a situation has arisen where precision soldering technology corresponding to this is not progressing.

In other words, when soldering terminals of ICs with a large number of pins and a narrow pitch, it is extremely difficult to stably supply a certain amount of solder to the fine soldering parts. On the other hand, it is the current situation that most of the work is done by hand.

However, in the manual work, when the solder is supplied to the fine portion, the amount of the supplied solder is not constant. For this reason, when the amount of solder supplied is small, the strength of the joint becomes insufficient, and when the amount of solder is excessive, adjacent terminals are joined by a bridge of solder and short circuit occurs. Was there.

Therefore, as a method of mounting a semiconductor device of this type on a substrate, the terminals of the semiconductor device, for example, the leads of the IC are preliminarily subjected to solder plating, and when the substrate is joined to the circuit, solder is externally applied to the joint portion. The method of supplying and joining from is adopted.

Here, the solder plating applied to the terminals of the semiconductor device is provided for the purpose of improving the wettability with the solder supplied from the outside, and is formed with a thickness of about several μm. However, since the soldering strength is insufficient only with the solder plating having such a thickness, the insufficient solder is supplied from the outside by the method described below to perform the joining work.

As a solder supply method, a method of using a thread solder, a method of previously applying a solder paste to a pad of a substrate to which terminals are joined by screen printing, a method of applying a solder paste to a pad of a substrate by a dispenser, a melting There is a method of immersing the board in a solder bath.

However, in an IC with a multi-pin body such as QFP that has a narrow lead interval, for example, an IC with a lead interval of 0.65 mm or less, if the amount of solder supplied is too small, the lead will not flow after reflow (melting). A bridge due to the solder between occurs,
Further, if the amount of solder is insufficient, the bonding strength will be insufficient, and it has been extremely difficult to supply an appropriate amount of solder.

Therefore, the applicant of the present application has proposed a method of attaching an appropriate amount of solder to the leads by applying thick film solder plating to the leads of the IC, as described below.

FIG. 3 shows a jig 1 for applying electric solder plating to many leads 6 of a multi-pin package IC such as QFP. The jig 1 is composed of a square upper frame 3 made of metal such as brass, a non-conductive lower frame 2 and screws 4.

Then, as shown in FIG. 4, between the lower frame 2 and the upper frame 3, the lead of the main body portion 5 of the multi-pin package IC such as QFP is provided.
After picking 6,6, ... and fixing them with screws 4, the jig 1 is dipped in the solder plating bath A so that most of the leads 6,6 ,. And the jig 1 is used as a cathode and the solder ingot 7 is used as an anode for electroplating.

[Problems to be Solved by the Invention] By the way, when the solder plating of the QFP leads is performed as described above, the regularity of the lead arrangement is lost at the four corners of the QFP, so that the leads near the four corners may be different. There is a tendency that the plating thickness becomes thicker than that of the lead. Therefore, when the QFP is mounted on the printed circuit board, there is a problem that the leads in the vicinity of the four corners of the QFP may be bridged by the solder. Moreover, since the lead plating thickness is not constant, there is a problem in that the mounting strength when mounting the QFP lacks stability. Further, not only in QFP but also in other packages, if there is a portion where lead intervals are not equal, there is a problem that the plating thickness changes at that portion.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a lead frame capable of electrodepositing a solder plating layer having a uniform thickness on each lead.

"Means for Solving the Problem" The present invention is to electrically connect a semiconductor element mounting portion and electrodes of a semiconductor element mounted on the semiconductor element mounting portion,
In a lead frame having the other end extending to the outside of the semiconductor device main body, each lead being plated with solder for mounting, in addition to the plurality of leads, separated from the semiconductor device after solder plating An auxiliary lead is provided for ensuring that the distance between the auxiliary lead and a lead adjacent thereto is equal to that of each of the plurality of leads, and the plurality of leads are provided along at least one side of the semiconductor device. It is characterized in that the auxiliary lead is arranged adjacent to the leads at both ends of the side and outside thereof.

[Operation] According to the above configuration, each of the plurality of leads used in the semiconductor device has a uniform interval between the adjacent leads. Therefore, when solder plating is applied to the lead frame having the above structure, a solder plating layer having a uniform film thickness is deposited on each lead regardless of whether it is an end portion or not.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a semiconductor integrated circuit using a QFP lead frame 10 according to an embodiment of the present invention. In this figure, mounting of a semiconductor chip on an island (semiconductor chip mounting portion) (not shown) of the lead frame 10 and wire bonding between each electrode pad of the semiconductor chip and the leads 6, 6, ... The state where the main body portion 5 is formed is shown. The lead frame 10 according to this embodiment has eight auxiliary leads 6a to 6b which are not connected to the electrode pads of the semiconductor chip, on the outside of the eight leads 6,6, ... Positioned at the corners of the QFP. is doing. Here, the distance between the auxiliary leads 6a to 6h and the adjacent lead 6 is the same as the arrangement distance of the other leads 6, 6, .... That is, the leads 6, 6, ... At the four corners also have constant intervals between adjacent leads, like the leads 6, 6 ,. In FIG. 1, auxiliary leads 6a, leads 6, 6, arranged on one side shown in the lower part of FIG.
..., the auxiliary leads 6b are the same for the other sides, whose tip portions are not separated from the adjacent leads and are integrated, and the auxiliary leads at both ends and the leads sandwiched between them.
The tips of 6, 6, ... Are not separated but are integrated. At each of the four corners of the main body portion 5, the respective base portions of the auxiliary leads 6b and 6c are connected to the outer peripheral frame 10b via the connecting portion 11, and the respective base portions of the auxiliary leads 6b and 6e are connected to the outer peripheral frame via the connecting portion 12. 10a, each of the bases of the auxiliary leads 6f and 6g is connected to the outer peripheral frame 10a via the connecting portion 13, and each of the bases of the auxiliary leads 6h and 6a is connected to the outer peripheral frame 10b via the molded resin gate 14. ing. That is, all the leads 6, 6, ..., the auxiliary leads 6a ~
6h and the lead frame 10 are electrically short-circuited.

Before performing thick film solder plating on the leads, lead forming is performed, and the leads 6, 6, ... And the auxiliary leads 6a to 6h are bent into a predetermined shape as shown in FIG. After that, connect the cathode to the lead frame 10 and
, And the auxiliary leads 6a to 6h are immersed in an electroplating solution in a state where the anode is arranged to perform electroplating. As a result, the leads 6, 6, ... And the auxiliary leads 6a-
The solder plating layer is electrodeposited at 6h. Here, the auxiliary leads 6a to 6h located at the end of each side have a thicker plating thickness than the others, but all the leads 6, 6, ... Which are not auxiliary leads have a uniform plating thickness.

When the solder plating is completed, the leads 6, 6, ... And the auxiliary leads 6a to 6h are cut at their tip ends to separate the leads from each other. Further, each of the connecting portions 11 to 13 and the mold resin gate 14 is cut at the boundary portion with the main body portion 5. As a result, the semiconductor integrated circuit having only the leads 6, 6, ... On the four sides of the main body 5 is separated from the lead frame 10. In this way, a semiconductor integrated circuit can be obtained in which all leads 6, 6, ... Are plated with thick-film solder with a uniform thickness.

[Advantages of the Invention] As described above, according to the present invention, the semiconductor element mounting portion, one end is electrically connected to the electrode of the semiconductor element mounted on the semiconductor mounting portion, and the other end is the semiconductor device main body. A lead frame having a plurality of leads extending to the outside of the lead frame, auxiliary leads to be removed after solder plating are provided at both ends in addition to the plurality of leads. Since the distance between the lead and the lead is uniform, it is possible to form a solder plating layer with a uniform thickness on each lead when used as a lead frame of a semiconductor device, and to obtain stable mounting strength during mounting. It is possible to obtain the effect that a semiconductor device to be manufactured can be manufactured.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit using a lead according to an embodiment of the present invention, FIG. 2 is a perspective view showing a shape after lead forming of the embodiment, and FIG. 3 is a conventional solder plating treatment. FIG. 4 is a perspective view showing the structure of the tool, and FIG. 4 is a view for explaining solder plating using the conventional solder plating jig shown in FIG. 10 ... Lead frame, 6 ... Lead, 6a-6h ... Auxiliary lead.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsuka Ota 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Yamaha Stock Company (56) References JP-A-2-220468 (JP, A) JP-A-1- 270335 (JP, A)

Claims (1)

[Claims] 1. A semiconductor element mounting portion and an electrode of a semiconductor element mounted on the semiconductor element mounting portion are electrically connected to each other,
A lead frame having a plurality of leads extending to the outside of the semiconductor device body at the other end, wherein each lead is solder-plated for mounting, in addition to the plurality of leads, separated from the semiconductor device after solder-plating. An auxiliary lead for providing a gap between the auxiliary lead and a lead adjacent to the auxiliary lead is made uniform with that of each of the plurality of leads, and the plurality of leads are provided along at least one side of the semiconductor device. The lead frame is provided, and the auxiliary lead is arranged outside the lead adjacent to the lead at both ends of the side.